diff options
Diffstat (limited to 'drivers/net/qede/base/ecore_rt_defs.h')
| -rw-r--r-- | drivers/net/qede/base/ecore_rt_defs.h | 599 |
1 files changed, 302 insertions, 297 deletions
diff --git a/drivers/net/qede/base/ecore_rt_defs.h b/drivers/net/qede/base/ecore_rt_defs.h index 1d085815..721b8c15 100644 --- a/drivers/net/qede/base/ecore_rt_defs.h +++ b/drivers/net/qede/base/ecore_rt_defs.h @@ -1,9 +1,7 @@ -/* - * Copyright (c) 2016 QLogic Corporation. +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright (c) 2016 - 2018 Cavium Inc. * All rights reserved. - * www.qlogic.com - * - * See LICENSE.qede_pmd for copyright and licensing details. + * www.cavium.com */ #ifndef __RT_DEFS_H__ @@ -205,329 +203,336 @@ #define QM_REG_MAXPQSIZETXSEL_63_RT_OFFSET 34082 #define QM_REG_BASEADDROTHERPQ_RT_OFFSET 34083 #define QM_REG_BASEADDROTHERPQ_RT_SIZE 128 -#define QM_REG_AFULLQMBYPTHRPFWFQ_RT_OFFSET 34211 -#define QM_REG_AFULLQMBYPTHRVPWFQ_RT_OFFSET 34212 -#define QM_REG_AFULLQMBYPTHRPFRL_RT_OFFSET 34213 -#define QM_REG_AFULLQMBYPTHRGLBLRL_RT_OFFSET 34214 -#define QM_REG_AFULLOPRTNSTCCRDMASK_RT_OFFSET 34215 -#define QM_REG_WRROTHERPQGRP_0_RT_OFFSET 34216 -#define QM_REG_WRROTHERPQGRP_1_RT_OFFSET 34217 -#define QM_REG_WRROTHERPQGRP_2_RT_OFFSET 34218 -#define QM_REG_WRROTHERPQGRP_3_RT_OFFSET 34219 -#define QM_REG_WRROTHERPQGRP_4_RT_OFFSET 34220 -#define QM_REG_WRROTHERPQGRP_5_RT_OFFSET 34221 -#define QM_REG_WRROTHERPQGRP_6_RT_OFFSET 34222 -#define QM_REG_WRROTHERPQGRP_7_RT_OFFSET 34223 -#define QM_REG_WRROTHERPQGRP_8_RT_OFFSET 34224 -#define QM_REG_WRROTHERPQGRP_9_RT_OFFSET 34225 -#define QM_REG_WRROTHERPQGRP_10_RT_OFFSET 34226 -#define QM_REG_WRROTHERPQGRP_11_RT_OFFSET 34227 -#define QM_REG_WRROTHERPQGRP_12_RT_OFFSET 34228 -#define QM_REG_WRROTHERPQGRP_13_RT_OFFSET 34229 -#define QM_REG_WRROTHERPQGRP_14_RT_OFFSET 34230 -#define QM_REG_WRROTHERPQGRP_15_RT_OFFSET 34231 -#define QM_REG_WRROTHERGRPWEIGHT_0_RT_OFFSET 34232 -#define QM_REG_WRROTHERGRPWEIGHT_1_RT_OFFSET 34233 -#define QM_REG_WRROTHERGRPWEIGHT_2_RT_OFFSET 34234 -#define QM_REG_WRROTHERGRPWEIGHT_3_RT_OFFSET 34235 -#define QM_REG_WRRTXGRPWEIGHT_0_RT_OFFSET 34236 -#define QM_REG_WRRTXGRPWEIGHT_1_RT_OFFSET 34237 -#define QM_REG_PQTX2PF_0_RT_OFFSET 34238 -#define QM_REG_PQTX2PF_1_RT_OFFSET 34239 -#define QM_REG_PQTX2PF_2_RT_OFFSET 34240 -#define QM_REG_PQTX2PF_3_RT_OFFSET 34241 -#define QM_REG_PQTX2PF_4_RT_OFFSET 34242 -#define QM_REG_PQTX2PF_5_RT_OFFSET 34243 -#define QM_REG_PQTX2PF_6_RT_OFFSET 34244 -#define QM_REG_PQTX2PF_7_RT_OFFSET 34245 -#define QM_REG_PQTX2PF_8_RT_OFFSET 34246 -#define QM_REG_PQTX2PF_9_RT_OFFSET 34247 -#define QM_REG_PQTX2PF_10_RT_OFFSET 34248 -#define QM_REG_PQTX2PF_11_RT_OFFSET 34249 -#define QM_REG_PQTX2PF_12_RT_OFFSET 34250 -#define QM_REG_PQTX2PF_13_RT_OFFSET 34251 -#define QM_REG_PQTX2PF_14_RT_OFFSET 34252 -#define QM_REG_PQTX2PF_15_RT_OFFSET 34253 -#define QM_REG_PQTX2PF_16_RT_OFFSET 34254 -#define QM_REG_PQTX2PF_17_RT_OFFSET 34255 -#define QM_REG_PQTX2PF_18_RT_OFFSET 34256 -#define QM_REG_PQTX2PF_19_RT_OFFSET 34257 -#define QM_REG_PQTX2PF_20_RT_OFFSET 34258 -#define QM_REG_PQTX2PF_21_RT_OFFSET 34259 -#define QM_REG_PQTX2PF_22_RT_OFFSET 34260 -#define QM_REG_PQTX2PF_23_RT_OFFSET 34261 -#define QM_REG_PQTX2PF_24_RT_OFFSET 34262 -#define QM_REG_PQTX2PF_25_RT_OFFSET 34263 -#define QM_REG_PQTX2PF_26_RT_OFFSET 34264 -#define QM_REG_PQTX2PF_27_RT_OFFSET 34265 -#define QM_REG_PQTX2PF_28_RT_OFFSET 34266 -#define QM_REG_PQTX2PF_29_RT_OFFSET 34267 -#define QM_REG_PQTX2PF_30_RT_OFFSET 34268 -#define QM_REG_PQTX2PF_31_RT_OFFSET 34269 -#define QM_REG_PQTX2PF_32_RT_OFFSET 34270 -#define QM_REG_PQTX2PF_33_RT_OFFSET 34271 -#define QM_REG_PQTX2PF_34_RT_OFFSET 34272 -#define QM_REG_PQTX2PF_35_RT_OFFSET 34273 -#define QM_REG_PQTX2PF_36_RT_OFFSET 34274 -#define QM_REG_PQTX2PF_37_RT_OFFSET 34275 -#define QM_REG_PQTX2PF_38_RT_OFFSET 34276 -#define QM_REG_PQTX2PF_39_RT_OFFSET 34277 -#define QM_REG_PQTX2PF_40_RT_OFFSET 34278 -#define QM_REG_PQTX2PF_41_RT_OFFSET 34279 -#define QM_REG_PQTX2PF_42_RT_OFFSET 34280 -#define QM_REG_PQTX2PF_43_RT_OFFSET 34281 -#define QM_REG_PQTX2PF_44_RT_OFFSET 34282 -#define QM_REG_PQTX2PF_45_RT_OFFSET 34283 -#define QM_REG_PQTX2PF_46_RT_OFFSET 34284 -#define QM_REG_PQTX2PF_47_RT_OFFSET 34285 -#define QM_REG_PQTX2PF_48_RT_OFFSET 34286 -#define QM_REG_PQTX2PF_49_RT_OFFSET 34287 -#define QM_REG_PQTX2PF_50_RT_OFFSET 34288 -#define QM_REG_PQTX2PF_51_RT_OFFSET 34289 -#define QM_REG_PQTX2PF_52_RT_OFFSET 34290 -#define QM_REG_PQTX2PF_53_RT_OFFSET 34291 -#define QM_REG_PQTX2PF_54_RT_OFFSET 34292 -#define QM_REG_PQTX2PF_55_RT_OFFSET 34293 -#define QM_REG_PQTX2PF_56_RT_OFFSET 34294 -#define QM_REG_PQTX2PF_57_RT_OFFSET 34295 -#define QM_REG_PQTX2PF_58_RT_OFFSET 34296 -#define QM_REG_PQTX2PF_59_RT_OFFSET 34297 -#define QM_REG_PQTX2PF_60_RT_OFFSET 34298 -#define QM_REG_PQTX2PF_61_RT_OFFSET 34299 -#define QM_REG_PQTX2PF_62_RT_OFFSET 34300 -#define QM_REG_PQTX2PF_63_RT_OFFSET 34301 -#define QM_REG_PQOTHER2PF_0_RT_OFFSET 34302 -#define QM_REG_PQOTHER2PF_1_RT_OFFSET 34303 -#define QM_REG_PQOTHER2PF_2_RT_OFFSET 34304 -#define QM_REG_PQOTHER2PF_3_RT_OFFSET 34305 -#define QM_REG_PQOTHER2PF_4_RT_OFFSET 34306 -#define QM_REG_PQOTHER2PF_5_RT_OFFSET 34307 -#define QM_REG_PQOTHER2PF_6_RT_OFFSET 34308 -#define QM_REG_PQOTHER2PF_7_RT_OFFSET 34309 -#define QM_REG_PQOTHER2PF_8_RT_OFFSET 34310 -#define QM_REG_PQOTHER2PF_9_RT_OFFSET 34311 -#define QM_REG_PQOTHER2PF_10_RT_OFFSET 34312 -#define QM_REG_PQOTHER2PF_11_RT_OFFSET 34313 -#define QM_REG_PQOTHER2PF_12_RT_OFFSET 34314 -#define QM_REG_PQOTHER2PF_13_RT_OFFSET 34315 -#define QM_REG_PQOTHER2PF_14_RT_OFFSET 34316 -#define QM_REG_PQOTHER2PF_15_RT_OFFSET 34317 -#define QM_REG_RLGLBLPERIOD_0_RT_OFFSET 34318 -#define QM_REG_RLGLBLPERIOD_1_RT_OFFSET 34319 -#define QM_REG_RLGLBLPERIODTIMER_0_RT_OFFSET 34320 -#define QM_REG_RLGLBLPERIODTIMER_1_RT_OFFSET 34321 -#define QM_REG_RLGLBLPERIODSEL_0_RT_OFFSET 34322 -#define QM_REG_RLGLBLPERIODSEL_1_RT_OFFSET 34323 -#define QM_REG_RLGLBLPERIODSEL_2_RT_OFFSET 34324 -#define QM_REG_RLGLBLPERIODSEL_3_RT_OFFSET 34325 -#define QM_REG_RLGLBLPERIODSEL_4_RT_OFFSET 34326 -#define QM_REG_RLGLBLPERIODSEL_5_RT_OFFSET 34327 -#define QM_REG_RLGLBLPERIODSEL_6_RT_OFFSET 34328 -#define QM_REG_RLGLBLPERIODSEL_7_RT_OFFSET 34329 -#define QM_REG_RLGLBLINCVAL_RT_OFFSET 34330 +#define QM_REG_PTRTBLOTHER_RT_OFFSET 34211 +#define QM_REG_PTRTBLOTHER_RT_SIZE 256 +#define QM_REG_AFULLQMBYPTHRPFWFQ_RT_OFFSET 34467 +#define QM_REG_AFULLQMBYPTHRVPWFQ_RT_OFFSET 34468 +#define QM_REG_AFULLQMBYPTHRPFRL_RT_OFFSET 34469 +#define QM_REG_AFULLQMBYPTHRGLBLRL_RT_OFFSET 34470 +#define QM_REG_AFULLOPRTNSTCCRDMASK_RT_OFFSET 34471 +#define QM_REG_WRROTHERPQGRP_0_RT_OFFSET 34472 +#define QM_REG_WRROTHERPQGRP_1_RT_OFFSET 34473 +#define QM_REG_WRROTHERPQGRP_2_RT_OFFSET 34474 +#define QM_REG_WRROTHERPQGRP_3_RT_OFFSET 34475 +#define QM_REG_WRROTHERPQGRP_4_RT_OFFSET 34476 +#define QM_REG_WRROTHERPQGRP_5_RT_OFFSET 34477 +#define QM_REG_WRROTHERPQGRP_6_RT_OFFSET 34478 +#define QM_REG_WRROTHERPQGRP_7_RT_OFFSET 34479 +#define QM_REG_WRROTHERPQGRP_8_RT_OFFSET 34480 +#define QM_REG_WRROTHERPQGRP_9_RT_OFFSET 34481 +#define QM_REG_WRROTHERPQGRP_10_RT_OFFSET 34482 +#define QM_REG_WRROTHERPQGRP_11_RT_OFFSET 34483 +#define QM_REG_WRROTHERPQGRP_12_RT_OFFSET 34484 +#define QM_REG_WRROTHERPQGRP_13_RT_OFFSET 34485 +#define QM_REG_WRROTHERPQGRP_14_RT_OFFSET 34486 +#define QM_REG_WRROTHERPQGRP_15_RT_OFFSET 34487 +#define QM_REG_WRROTHERGRPWEIGHT_0_RT_OFFSET 34488 +#define QM_REG_WRROTHERGRPWEIGHT_1_RT_OFFSET 34489 +#define QM_REG_WRROTHERGRPWEIGHT_2_RT_OFFSET 34490 +#define QM_REG_WRROTHERGRPWEIGHT_3_RT_OFFSET 34491 +#define QM_REG_WRRTXGRPWEIGHT_0_RT_OFFSET 34492 +#define QM_REG_WRRTXGRPWEIGHT_1_RT_OFFSET 34493 +#define QM_REG_PQTX2PF_0_RT_OFFSET 34494 +#define QM_REG_PQTX2PF_1_RT_OFFSET 34495 +#define QM_REG_PQTX2PF_2_RT_OFFSET 34496 +#define QM_REG_PQTX2PF_3_RT_OFFSET 34497 +#define QM_REG_PQTX2PF_4_RT_OFFSET 34498 +#define QM_REG_PQTX2PF_5_RT_OFFSET 34499 +#define QM_REG_PQTX2PF_6_RT_OFFSET 34500 +#define QM_REG_PQTX2PF_7_RT_OFFSET 34501 +#define QM_REG_PQTX2PF_8_RT_OFFSET 34502 +#define QM_REG_PQTX2PF_9_RT_OFFSET 34503 +#define QM_REG_PQTX2PF_10_RT_OFFSET 34504 +#define QM_REG_PQTX2PF_11_RT_OFFSET 34505 +#define QM_REG_PQTX2PF_12_RT_OFFSET 34506 +#define QM_REG_PQTX2PF_13_RT_OFFSET 34507 +#define QM_REG_PQTX2PF_14_RT_OFFSET 34508 +#define QM_REG_PQTX2PF_15_RT_OFFSET 34509 +#define QM_REG_PQTX2PF_16_RT_OFFSET 34510 +#define QM_REG_PQTX2PF_17_RT_OFFSET 34511 +#define QM_REG_PQTX2PF_18_RT_OFFSET 34512 +#define QM_REG_PQTX2PF_19_RT_OFFSET 34513 +#define QM_REG_PQTX2PF_20_RT_OFFSET 34514 +#define QM_REG_PQTX2PF_21_RT_OFFSET 34515 +#define QM_REG_PQTX2PF_22_RT_OFFSET 34516 +#define QM_REG_PQTX2PF_23_RT_OFFSET 34517 +#define QM_REG_PQTX2PF_24_RT_OFFSET 34518 +#define QM_REG_PQTX2PF_25_RT_OFFSET 34519 +#define QM_REG_PQTX2PF_26_RT_OFFSET 34520 +#define QM_REG_PQTX2PF_27_RT_OFFSET 34521 +#define QM_REG_PQTX2PF_28_RT_OFFSET 34522 +#define QM_REG_PQTX2PF_29_RT_OFFSET 34523 +#define QM_REG_PQTX2PF_30_RT_OFFSET 34524 +#define QM_REG_PQTX2PF_31_RT_OFFSET 34525 +#define QM_REG_PQTX2PF_32_RT_OFFSET 34526 +#define QM_REG_PQTX2PF_33_RT_OFFSET 34527 +#define QM_REG_PQTX2PF_34_RT_OFFSET 34528 +#define QM_REG_PQTX2PF_35_RT_OFFSET 34529 +#define QM_REG_PQTX2PF_36_RT_OFFSET 34530 +#define QM_REG_PQTX2PF_37_RT_OFFSET 34531 +#define QM_REG_PQTX2PF_38_RT_OFFSET 34532 +#define QM_REG_PQTX2PF_39_RT_OFFSET 34533 +#define QM_REG_PQTX2PF_40_RT_OFFSET 34534 +#define QM_REG_PQTX2PF_41_RT_OFFSET 34535 +#define QM_REG_PQTX2PF_42_RT_OFFSET 34536 +#define QM_REG_PQTX2PF_43_RT_OFFSET 34537 +#define QM_REG_PQTX2PF_44_RT_OFFSET 34538 +#define QM_REG_PQTX2PF_45_RT_OFFSET 34539 +#define QM_REG_PQTX2PF_46_RT_OFFSET 34540 +#define QM_REG_PQTX2PF_47_RT_OFFSET 34541 +#define QM_REG_PQTX2PF_48_RT_OFFSET 34542 +#define QM_REG_PQTX2PF_49_RT_OFFSET 34543 +#define QM_REG_PQTX2PF_50_RT_OFFSET 34544 +#define QM_REG_PQTX2PF_51_RT_OFFSET 34545 +#define QM_REG_PQTX2PF_52_RT_OFFSET 34546 +#define QM_REG_PQTX2PF_53_RT_OFFSET 34547 +#define QM_REG_PQTX2PF_54_RT_OFFSET 34548 +#define QM_REG_PQTX2PF_55_RT_OFFSET 34549 +#define QM_REG_PQTX2PF_56_RT_OFFSET 34550 +#define QM_REG_PQTX2PF_57_RT_OFFSET 34551 +#define QM_REG_PQTX2PF_58_RT_OFFSET 34552 +#define QM_REG_PQTX2PF_59_RT_OFFSET 34553 +#define QM_REG_PQTX2PF_60_RT_OFFSET 34554 +#define QM_REG_PQTX2PF_61_RT_OFFSET 34555 +#define QM_REG_PQTX2PF_62_RT_OFFSET 34556 +#define QM_REG_PQTX2PF_63_RT_OFFSET 34557 +#define QM_REG_PQOTHER2PF_0_RT_OFFSET 34558 +#define QM_REG_PQOTHER2PF_1_RT_OFFSET 34559 +#define QM_REG_PQOTHER2PF_2_RT_OFFSET 34560 +#define QM_REG_PQOTHER2PF_3_RT_OFFSET 34561 +#define QM_REG_PQOTHER2PF_4_RT_OFFSET 34562 +#define QM_REG_PQOTHER2PF_5_RT_OFFSET 34563 +#define QM_REG_PQOTHER2PF_6_RT_OFFSET 34564 +#define QM_REG_PQOTHER2PF_7_RT_OFFSET 34565 +#define QM_REG_PQOTHER2PF_8_RT_OFFSET 34566 +#define QM_REG_PQOTHER2PF_9_RT_OFFSET 34567 +#define QM_REG_PQOTHER2PF_10_RT_OFFSET 34568 +#define QM_REG_PQOTHER2PF_11_RT_OFFSET 34569 +#define QM_REG_PQOTHER2PF_12_RT_OFFSET 34570 +#define QM_REG_PQOTHER2PF_13_RT_OFFSET 34571 +#define QM_REG_PQOTHER2PF_14_RT_OFFSET 34572 +#define QM_REG_PQOTHER2PF_15_RT_OFFSET 34573 +#define QM_REG_RLGLBLPERIOD_0_RT_OFFSET 34574 +#define QM_REG_RLGLBLPERIOD_1_RT_OFFSET 34575 +#define QM_REG_RLGLBLPERIODTIMER_0_RT_OFFSET 34576 +#define QM_REG_RLGLBLPERIODTIMER_1_RT_OFFSET 34577 +#define QM_REG_RLGLBLPERIODSEL_0_RT_OFFSET 34578 +#define QM_REG_RLGLBLPERIODSEL_1_RT_OFFSET 34579 +#define QM_REG_RLGLBLPERIODSEL_2_RT_OFFSET 34580 +#define QM_REG_RLGLBLPERIODSEL_3_RT_OFFSET 34581 +#define QM_REG_RLGLBLPERIODSEL_4_RT_OFFSET 34582 +#define QM_REG_RLGLBLPERIODSEL_5_RT_OFFSET 34583 +#define QM_REG_RLGLBLPERIODSEL_6_RT_OFFSET 34584 +#define QM_REG_RLGLBLPERIODSEL_7_RT_OFFSET 34585 +#define QM_REG_RLGLBLINCVAL_RT_OFFSET 34586 #define QM_REG_RLGLBLINCVAL_RT_SIZE 256 -#define QM_REG_RLGLBLUPPERBOUND_RT_OFFSET 34586 +#define QM_REG_RLGLBLUPPERBOUND_RT_OFFSET 34842 #define QM_REG_RLGLBLUPPERBOUND_RT_SIZE 256 -#define QM_REG_RLGLBLCRD_RT_OFFSET 34842 +#define QM_REG_RLGLBLCRD_RT_OFFSET 35098 #define QM_REG_RLGLBLCRD_RT_SIZE 256 -#define QM_REG_RLGLBLENABLE_RT_OFFSET 35098 -#define QM_REG_RLPFPERIOD_RT_OFFSET 35099 -#define QM_REG_RLPFPERIODTIMER_RT_OFFSET 35100 -#define QM_REG_RLPFINCVAL_RT_OFFSET 35101 +#define QM_REG_RLGLBLENABLE_RT_OFFSET 35354 +#define QM_REG_RLPFPERIOD_RT_OFFSET 35355 +#define QM_REG_RLPFPERIODTIMER_RT_OFFSET 35356 +#define QM_REG_RLPFINCVAL_RT_OFFSET 35357 #define QM_REG_RLPFINCVAL_RT_SIZE 16 -#define QM_REG_RLPFUPPERBOUND_RT_OFFSET 35117 +#define QM_REG_RLPFUPPERBOUND_RT_OFFSET 35373 #define QM_REG_RLPFUPPERBOUND_RT_SIZE 16 -#define QM_REG_RLPFCRD_RT_OFFSET 35133 +#define QM_REG_RLPFCRD_RT_OFFSET 35389 #define QM_REG_RLPFCRD_RT_SIZE 16 -#define QM_REG_RLPFENABLE_RT_OFFSET 35149 -#define QM_REG_RLPFVOQENABLE_RT_OFFSET 35150 -#define QM_REG_WFQPFWEIGHT_RT_OFFSET 35151 +#define QM_REG_RLPFENABLE_RT_OFFSET 35405 +#define QM_REG_RLPFVOQENABLE_RT_OFFSET 35406 +#define QM_REG_WFQPFWEIGHT_RT_OFFSET 35407 #define QM_REG_WFQPFWEIGHT_RT_SIZE 16 -#define QM_REG_WFQPFUPPERBOUND_RT_OFFSET 35167 +#define QM_REG_WFQPFUPPERBOUND_RT_OFFSET 35423 #define QM_REG_WFQPFUPPERBOUND_RT_SIZE 16 -#define QM_REG_WFQPFCRD_RT_OFFSET 35183 +#define QM_REG_WFQPFCRD_RT_OFFSET 35439 #define QM_REG_WFQPFCRD_RT_SIZE 256 -#define QM_REG_WFQPFENABLE_RT_OFFSET 35439 -#define QM_REG_WFQVPENABLE_RT_OFFSET 35440 -#define QM_REG_BASEADDRTXPQ_RT_OFFSET 35441 +#define QM_REG_WFQPFENABLE_RT_OFFSET 35695 +#define QM_REG_WFQVPENABLE_RT_OFFSET 35696 +#define QM_REG_BASEADDRTXPQ_RT_OFFSET 35697 #define QM_REG_BASEADDRTXPQ_RT_SIZE 512 -#define QM_REG_TXPQMAP_RT_OFFSET 35953 +#define QM_REG_TXPQMAP_RT_OFFSET 36209 #define QM_REG_TXPQMAP_RT_SIZE 512 -#define QM_REG_WFQVPWEIGHT_RT_OFFSET 36465 +#define QM_REG_WFQVPWEIGHT_RT_OFFSET 36721 #define QM_REG_WFQVPWEIGHT_RT_SIZE 512 -#define QM_REG_WFQVPCRD_RT_OFFSET 36977 +#define QM_REG_WFQVPCRD_RT_OFFSET 37233 #define QM_REG_WFQVPCRD_RT_SIZE 512 -#define QM_REG_WFQVPMAP_RT_OFFSET 37489 +#define QM_REG_WFQVPMAP_RT_OFFSET 37745 #define QM_REG_WFQVPMAP_RT_SIZE 512 -#define QM_REG_WFQPFCRD_MSB_RT_OFFSET 38001 +#define QM_REG_PTRTBLTX_RT_OFFSET 38257 +#define QM_REG_PTRTBLTX_RT_SIZE 1024 +#define QM_REG_WFQPFCRD_MSB_RT_OFFSET 39281 #define QM_REG_WFQPFCRD_MSB_RT_SIZE 320 -#define QM_REG_VOQCRDLINE_RT_OFFSET 38321 +#define QM_REG_VOQCRDLINE_RT_OFFSET 39601 #define QM_REG_VOQCRDLINE_RT_SIZE 36 -#define QM_REG_VOQINITCRDLINE_RT_OFFSET 38357 +#define QM_REG_VOQINITCRDLINE_RT_OFFSET 39637 #define QM_REG_VOQINITCRDLINE_RT_SIZE 36 -#define QM_REG_RLPFVOQENABLE_MSB_RT_OFFSET 38393 -#define NIG_REG_TAG_ETHERTYPE_0_RT_OFFSET 38394 -#define NIG_REG_BRB_GATE_DNTFWD_PORT_RT_OFFSET 38395 -#define NIG_REG_OUTER_TAG_VALUE_LIST0_RT_OFFSET 38396 -#define NIG_REG_OUTER_TAG_VALUE_LIST1_RT_OFFSET 38397 -#define NIG_REG_OUTER_TAG_VALUE_LIST2_RT_OFFSET 38398 -#define NIG_REG_OUTER_TAG_VALUE_LIST3_RT_OFFSET 38399 -#define NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET 38400 -#define NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET 38401 +#define QM_REG_RLPFVOQENABLE_MSB_RT_OFFSET 39673 +#define NIG_REG_TAG_ETHERTYPE_0_RT_OFFSET 39674 +#define NIG_REG_BRB_GATE_DNTFWD_PORT_RT_OFFSET 39675 +#define NIG_REG_OUTER_TAG_VALUE_LIST0_RT_OFFSET 39676 +#define NIG_REG_OUTER_TAG_VALUE_LIST1_RT_OFFSET 39677 +#define NIG_REG_OUTER_TAG_VALUE_LIST2_RT_OFFSET 39678 +#define NIG_REG_OUTER_TAG_VALUE_LIST3_RT_OFFSET 39679 +#define NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET 39680 +#define NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET 39681 #define NIG_REG_LLH_FUNC_TAG_EN_RT_SIZE 4 -#define NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET 38405 +#define NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET 39685 #define NIG_REG_LLH_FUNC_TAG_VALUE_RT_SIZE 4 -#define NIG_REG_LLH_FUNC_FILTER_VALUE_RT_OFFSET 38409 +#define NIG_REG_LLH_FUNC_FILTER_VALUE_RT_OFFSET 39689 #define NIG_REG_LLH_FUNC_FILTER_VALUE_RT_SIZE 32 -#define NIG_REG_LLH_FUNC_FILTER_EN_RT_OFFSET 38441 +#define NIG_REG_LLH_FUNC_FILTER_EN_RT_OFFSET 39721 #define NIG_REG_LLH_FUNC_FILTER_EN_RT_SIZE 16 -#define NIG_REG_LLH_FUNC_FILTER_MODE_RT_OFFSET 38457 +#define NIG_REG_LLH_FUNC_FILTER_MODE_RT_OFFSET 39737 #define NIG_REG_LLH_FUNC_FILTER_MODE_RT_SIZE 16 -#define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_RT_OFFSET 38473 +#define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_RT_OFFSET 39753 #define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_RT_SIZE 16 -#define NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_OFFSET 38489 +#define NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_OFFSET 39769 #define NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_SIZE 16 -#define NIG_REG_TX_EDPM_CTRL_RT_OFFSET 38505 -#define NIG_REG_ROCE_DUPLICATE_TO_HOST_RT_OFFSET 38506 -#define NIG_REG_PPF_TO_ENGINE_SEL_RT_OFFSET 38507 +#define NIG_REG_TX_EDPM_CTRL_RT_OFFSET 39785 +#define NIG_REG_ROCE_DUPLICATE_TO_HOST_RT_OFFSET 39786 +#define NIG_REG_PPF_TO_ENGINE_SEL_RT_OFFSET 39787 #define NIG_REG_PPF_TO_ENGINE_SEL_RT_SIZE 8 -#define NIG_REG_LLH_PF_CLS_FUNC_FILTER_VALUE_RT_OFFSET 38515 +#define NIG_REG_LLH_PF_CLS_FUNC_FILTER_VALUE_RT_OFFSET 39795 #define NIG_REG_LLH_PF_CLS_FUNC_FILTER_VALUE_RT_SIZE 1024 -#define NIG_REG_LLH_PF_CLS_FUNC_FILTER_EN_RT_OFFSET 39539 +#define NIG_REG_LLH_PF_CLS_FUNC_FILTER_EN_RT_OFFSET 40819 #define NIG_REG_LLH_PF_CLS_FUNC_FILTER_EN_RT_SIZE 512 -#define NIG_REG_LLH_PF_CLS_FUNC_FILTER_MODE_RT_OFFSET 40051 +#define NIG_REG_LLH_PF_CLS_FUNC_FILTER_MODE_RT_OFFSET 41331 #define NIG_REG_LLH_PF_CLS_FUNC_FILTER_MODE_RT_SIZE 512 -#define NIG_REG_LLH_PF_CLS_FUNC_FILTER_PROTOCOL_TYPE_RT_OFFSET 40563 +#define NIG_REG_LLH_PF_CLS_FUNC_FILTER_PROTOCOL_TYPE_RT_OFFSET 41843 #define NIG_REG_LLH_PF_CLS_FUNC_FILTER_PROTOCOL_TYPE_RT_SIZE 512 -#define NIG_REG_LLH_PF_CLS_FUNC_FILTER_HDR_SEL_RT_OFFSET 41075 +#define NIG_REG_LLH_PF_CLS_FUNC_FILTER_HDR_SEL_RT_OFFSET 42355 #define NIG_REG_LLH_PF_CLS_FUNC_FILTER_HDR_SEL_RT_SIZE 512 -#define NIG_REG_LLH_PF_CLS_FILTERS_MAP_RT_OFFSET 41587 +#define NIG_REG_LLH_PF_CLS_FILTERS_MAP_RT_OFFSET 42867 #define NIG_REG_LLH_PF_CLS_FILTERS_MAP_RT_SIZE 32 -#define CDU_REG_CID_ADDR_PARAMS_RT_OFFSET 41619 -#define CDU_REG_SEGMENT0_PARAMS_RT_OFFSET 41620 -#define CDU_REG_SEGMENT1_PARAMS_RT_OFFSET 41621 -#define CDU_REG_PF_SEG0_TYPE_OFFSET_RT_OFFSET 41622 -#define CDU_REG_PF_SEG1_TYPE_OFFSET_RT_OFFSET 41623 -#define CDU_REG_PF_SEG2_TYPE_OFFSET_RT_OFFSET 41624 -#define CDU_REG_PF_SEG3_TYPE_OFFSET_RT_OFFSET 41625 -#define CDU_REG_PF_FL_SEG0_TYPE_OFFSET_RT_OFFSET 41626 -#define CDU_REG_PF_FL_SEG1_TYPE_OFFSET_RT_OFFSET 41627 -#define CDU_REG_PF_FL_SEG2_TYPE_OFFSET_RT_OFFSET 41628 -#define CDU_REG_PF_FL_SEG3_TYPE_OFFSET_RT_OFFSET 41629 -#define CDU_REG_VF_SEG_TYPE_OFFSET_RT_OFFSET 41630 -#define CDU_REG_VF_FL_SEG_TYPE_OFFSET_RT_OFFSET 41631 -#define PBF_REG_TAG_ETHERTYPE_0_RT_OFFSET 41632 -#define PBF_REG_BTB_SHARED_AREA_SIZE_RT_OFFSET 41633 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ0_RT_OFFSET 41634 -#define PBF_REG_BTB_GUARANTEED_VOQ0_RT_OFFSET 41635 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ0_RT_OFFSET 41636 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ1_RT_OFFSET 41637 -#define PBF_REG_BTB_GUARANTEED_VOQ1_RT_OFFSET 41638 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ1_RT_OFFSET 41639 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ2_RT_OFFSET 41640 -#define PBF_REG_BTB_GUARANTEED_VOQ2_RT_OFFSET 41641 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ2_RT_OFFSET 41642 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ3_RT_OFFSET 41643 -#define PBF_REG_BTB_GUARANTEED_VOQ3_RT_OFFSET 41644 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ3_RT_OFFSET 41645 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ4_RT_OFFSET 41646 -#define PBF_REG_BTB_GUARANTEED_VOQ4_RT_OFFSET 41647 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ4_RT_OFFSET 41648 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ5_RT_OFFSET 41649 -#define PBF_REG_BTB_GUARANTEED_VOQ5_RT_OFFSET 41650 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ5_RT_OFFSET 41651 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ6_RT_OFFSET 41652 -#define PBF_REG_BTB_GUARANTEED_VOQ6_RT_OFFSET 41653 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ6_RT_OFFSET 41654 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ7_RT_OFFSET 41655 -#define PBF_REG_BTB_GUARANTEED_VOQ7_RT_OFFSET 41656 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ7_RT_OFFSET 41657 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ8_RT_OFFSET 41658 -#define PBF_REG_BTB_GUARANTEED_VOQ8_RT_OFFSET 41659 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ8_RT_OFFSET 41660 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ9_RT_OFFSET 41661 -#define PBF_REG_BTB_GUARANTEED_VOQ9_RT_OFFSET 41662 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ9_RT_OFFSET 41663 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ10_RT_OFFSET 41664 -#define PBF_REG_BTB_GUARANTEED_VOQ10_RT_OFFSET 41665 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ10_RT_OFFSET 41666 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ11_RT_OFFSET 41667 -#define PBF_REG_BTB_GUARANTEED_VOQ11_RT_OFFSET 41668 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ11_RT_OFFSET 41669 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ12_RT_OFFSET 41670 -#define PBF_REG_BTB_GUARANTEED_VOQ12_RT_OFFSET 41671 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ12_RT_OFFSET 41672 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ13_RT_OFFSET 41673 -#define PBF_REG_BTB_GUARANTEED_VOQ13_RT_OFFSET 41674 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ13_RT_OFFSET 41675 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ14_RT_OFFSET 41676 -#define PBF_REG_BTB_GUARANTEED_VOQ14_RT_OFFSET 41677 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ14_RT_OFFSET 41678 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ15_RT_OFFSET 41679 -#define PBF_REG_BTB_GUARANTEED_VOQ15_RT_OFFSET 41680 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ15_RT_OFFSET 41681 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ16_RT_OFFSET 41682 -#define PBF_REG_BTB_GUARANTEED_VOQ16_RT_OFFSET 41683 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ16_RT_OFFSET 41684 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ17_RT_OFFSET 41685 -#define PBF_REG_BTB_GUARANTEED_VOQ17_RT_OFFSET 41686 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ17_RT_OFFSET 41687 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ18_RT_OFFSET 41688 -#define PBF_REG_BTB_GUARANTEED_VOQ18_RT_OFFSET 41689 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ18_RT_OFFSET 41690 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ19_RT_OFFSET 41691 -#define PBF_REG_BTB_GUARANTEED_VOQ19_RT_OFFSET 41692 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ19_RT_OFFSET 41693 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ20_RT_OFFSET 41694 -#define PBF_REG_BTB_GUARANTEED_VOQ20_RT_OFFSET 41695 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ20_RT_OFFSET 41696 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ21_RT_OFFSET 41697 -#define PBF_REG_BTB_GUARANTEED_VOQ21_RT_OFFSET 41698 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ21_RT_OFFSET 41699 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ22_RT_OFFSET 41700 -#define PBF_REG_BTB_GUARANTEED_VOQ22_RT_OFFSET 41701 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ22_RT_OFFSET 41702 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ23_RT_OFFSET 41703 -#define PBF_REG_BTB_GUARANTEED_VOQ23_RT_OFFSET 41704 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ23_RT_OFFSET 41705 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ24_RT_OFFSET 41706 -#define PBF_REG_BTB_GUARANTEED_VOQ24_RT_OFFSET 41707 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ24_RT_OFFSET 41708 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ25_RT_OFFSET 41709 -#define PBF_REG_BTB_GUARANTEED_VOQ25_RT_OFFSET 41710 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ25_RT_OFFSET 41711 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ26_RT_OFFSET 41712 -#define PBF_REG_BTB_GUARANTEED_VOQ26_RT_OFFSET 41713 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ26_RT_OFFSET 41714 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ27_RT_OFFSET 41715 -#define PBF_REG_BTB_GUARANTEED_VOQ27_RT_OFFSET 41716 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ27_RT_OFFSET 41717 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ28_RT_OFFSET 41718 -#define PBF_REG_BTB_GUARANTEED_VOQ28_RT_OFFSET 41719 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ28_RT_OFFSET 41720 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ29_RT_OFFSET 41721 -#define PBF_REG_BTB_GUARANTEED_VOQ29_RT_OFFSET 41722 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ29_RT_OFFSET 41723 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ30_RT_OFFSET 41724 -#define PBF_REG_BTB_GUARANTEED_VOQ30_RT_OFFSET 41725 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ30_RT_OFFSET 41726 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ31_RT_OFFSET 41727 -#define PBF_REG_BTB_GUARANTEED_VOQ31_RT_OFFSET 41728 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ31_RT_OFFSET 41729 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ32_RT_OFFSET 41730 -#define PBF_REG_BTB_GUARANTEED_VOQ32_RT_OFFSET 41731 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ32_RT_OFFSET 41732 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ33_RT_OFFSET 41733 -#define PBF_REG_BTB_GUARANTEED_VOQ33_RT_OFFSET 41734 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ33_RT_OFFSET 41735 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ34_RT_OFFSET 41736 -#define PBF_REG_BTB_GUARANTEED_VOQ34_RT_OFFSET 41737 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ34_RT_OFFSET 41738 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ35_RT_OFFSET 41739 -#define PBF_REG_BTB_GUARANTEED_VOQ35_RT_OFFSET 41740 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ35_RT_OFFSET 41741 -#define XCM_REG_CON_PHY_Q3_RT_OFFSET 41742 +#define CDU_REG_CID_ADDR_PARAMS_RT_OFFSET 42899 +#define CDU_REG_SEGMENT0_PARAMS_RT_OFFSET 42900 +#define CDU_REG_SEGMENT1_PARAMS_RT_OFFSET 42901 +#define CDU_REG_PF_SEG0_TYPE_OFFSET_RT_OFFSET 42902 +#define CDU_REG_PF_SEG1_TYPE_OFFSET_RT_OFFSET 42903 +#define CDU_REG_PF_SEG2_TYPE_OFFSET_RT_OFFSET 42904 +#define CDU_REG_PF_SEG3_TYPE_OFFSET_RT_OFFSET 42905 +#define CDU_REG_PF_FL_SEG0_TYPE_OFFSET_RT_OFFSET 42906 +#define CDU_REG_PF_FL_SEG1_TYPE_OFFSET_RT_OFFSET 42907 +#define CDU_REG_PF_FL_SEG2_TYPE_OFFSET_RT_OFFSET 42908 +#define CDU_REG_PF_FL_SEG3_TYPE_OFFSET_RT_OFFSET 42909 +#define CDU_REG_VF_SEG_TYPE_OFFSET_RT_OFFSET 42910 +#define CDU_REG_VF_FL_SEG_TYPE_OFFSET_RT_OFFSET 42911 +#define PBF_REG_TAG_ETHERTYPE_0_RT_OFFSET 42912 +#define PBF_REG_BTB_SHARED_AREA_SIZE_RT_OFFSET 42913 +#define PBF_REG_YCMD_QS_NUM_LINES_VOQ0_RT_OFFSET 42914 +#define PBF_REG_BTB_GUARANTEED_VOQ0_RT_OFFSET 42915 +#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ0_RT_OFFSET 42916 +#define PBF_REG_YCMD_QS_NUM_LINES_VOQ1_RT_OFFSET 42917 +#define PBF_REG_BTB_GUARANTEED_VOQ1_RT_OFFSET 42918 +#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ1_RT_OFFSET 42919 +#define PBF_REG_YCMD_QS_NUM_LINES_VOQ2_RT_OFFSET 42920 +#define PBF_REG_BTB_GUARANTEED_VOQ2_RT_OFFSET 42921 +#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ2_RT_OFFSET 42922 +#define PBF_REG_YCMD_QS_NUM_LINES_VOQ3_RT_OFFSET 42923 +#define PBF_REG_BTB_GUARANTEED_VOQ3_RT_OFFSET 42924 +#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ3_RT_OFFSET 42925 +#define PBF_REG_YCMD_QS_NUM_LINES_VOQ4_RT_OFFSET 42926 +#define PBF_REG_BTB_GUARANTEED_VOQ4_RT_OFFSET 42927 +#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ4_RT_OFFSET 42928 +#define PBF_REG_YCMD_QS_NUM_LINES_VOQ5_RT_OFFSET 42929 +#define PBF_REG_BTB_GUARANTEED_VOQ5_RT_OFFSET 42930 +#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ5_RT_OFFSET 42931 +#define PBF_REG_YCMD_QS_NUM_LINES_VOQ6_RT_OFFSET 42932 +#define PBF_REG_BTB_GUARANTEED_VOQ6_RT_OFFSET 42933 +#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ6_RT_OFFSET 42934 +#define PBF_REG_YCMD_QS_NUM_LINES_VOQ7_RT_OFFSET 42935 +#define PBF_REG_BTB_GUARANTEED_VOQ7_RT_OFFSET 42936 +#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ7_RT_OFFSET 42937 +#define PBF_REG_YCMD_QS_NUM_LINES_VOQ8_RT_OFFSET 42938 +#define PBF_REG_BTB_GUARANTEED_VOQ8_RT_OFFSET 42939 +#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ8_RT_OFFSET 42940 +#define PBF_REG_YCMD_QS_NUM_LINES_VOQ9_RT_OFFSET 42941 +#define PBF_REG_BTB_GUARANTEED_VOQ9_RT_OFFSET 42942 +#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ9_RT_OFFSET 42943 +#define PBF_REG_YCMD_QS_NUM_LINES_VOQ10_RT_OFFSET 42944 +#define PBF_REG_BTB_GUARANTEED_VOQ10_RT_OFFSET 42945 +#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ10_RT_OFFSET 42946 +#define PBF_REG_YCMD_QS_NUM_LINES_VOQ11_RT_OFFSET 42947 +#define PBF_REG_BTB_GUARANTEED_VOQ11_RT_OFFSET 42948 +#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ11_RT_OFFSET 42949 +#define PBF_REG_YCMD_QS_NUM_LINES_VOQ12_RT_OFFSET 42950 +#define PBF_REG_BTB_GUARANTEED_VOQ12_RT_OFFSET 42951 +#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ12_RT_OFFSET 42952 +#define PBF_REG_YCMD_QS_NUM_LINES_VOQ13_RT_OFFSET 42953 +#define PBF_REG_BTB_GUARANTEED_VOQ13_RT_OFFSET 42954 +#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ13_RT_OFFSET 42955 +#define PBF_REG_YCMD_QS_NUM_LINES_VOQ14_RT_OFFSET 42956 +#define PBF_REG_BTB_GUARANTEED_VOQ14_RT_OFFSET 42957 +#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ14_RT_OFFSET 42958 +#define PBF_REG_YCMD_QS_NUM_LINES_VOQ15_RT_OFFSET 42959 +#define PBF_REG_BTB_GUARANTEED_VOQ15_RT_OFFSET 42960 +#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ15_RT_OFFSET 42961 +#define PBF_REG_YCMD_QS_NUM_LINES_VOQ16_RT_OFFSET 42962 +#define PBF_REG_BTB_GUARANTEED_VOQ16_RT_OFFSET 42963 +#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ16_RT_OFFSET 42964 +#define PBF_REG_YCMD_QS_NUM_LINES_VOQ17_RT_OFFSET 42965 +#define PBF_REG_BTB_GUARANTEED_VOQ17_RT_OFFSET 42966 +#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ17_RT_OFFSET 42967 +#define PBF_REG_YCMD_QS_NUM_LINES_VOQ18_RT_OFFSET 42968 +#define PBF_REG_BTB_GUARANTEED_VOQ18_RT_OFFSET 42969 +#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ18_RT_OFFSET 42970 +#define PBF_REG_YCMD_QS_NUM_LINES_VOQ19_RT_OFFSET 42971 +#define PBF_REG_BTB_GUARANTEED_VOQ19_RT_OFFSET 42972 +#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ19_RT_OFFSET 42973 +#define PBF_REG_YCMD_QS_NUM_LINES_VOQ20_RT_OFFSET 42974 +#define PBF_REG_BTB_GUARANTEED_VOQ20_RT_OFFSET 42975 +#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ20_RT_OFFSET 42976 +#define PBF_REG_YCMD_QS_NUM_LINES_VOQ21_RT_OFFSET 42977 +#define PBF_REG_BTB_GUARANTEED_VOQ21_RT_OFFSET 42978 +#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ21_RT_OFFSET 42979 +#define PBF_REG_YCMD_QS_NUM_LINES_VOQ22_RT_OFFSET 42980 +#define PBF_REG_BTB_GUARANTEED_VOQ22_RT_OFFSET 42981 +#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ22_RT_OFFSET 42982 +#define PBF_REG_YCMD_QS_NUM_LINES_VOQ23_RT_OFFSET 42983 +#define PBF_REG_BTB_GUARANTEED_VOQ23_RT_OFFSET 42984 +#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ23_RT_OFFSET 42985 +#define PBF_REG_YCMD_QS_NUM_LINES_VOQ24_RT_OFFSET 42986 +#define PBF_REG_BTB_GUARANTEED_VOQ24_RT_OFFSET 42987 +#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ24_RT_OFFSET 42988 +#define PBF_REG_YCMD_QS_NUM_LINES_VOQ25_RT_OFFSET 42989 +#define PBF_REG_BTB_GUARANTEED_VOQ25_RT_OFFSET 42990 +#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ25_RT_OFFSET 42991 +#define PBF_REG_YCMD_QS_NUM_LINES_VOQ26_RT_OFFSET 42992 +#define PBF_REG_BTB_GUARANTEED_VOQ26_RT_OFFSET 42993 +#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ26_RT_OFFSET 42994 +#define PBF_REG_YCMD_QS_NUM_LINES_VOQ27_RT_OFFSET 42995 +#define PBF_REG_BTB_GUARANTEED_VOQ27_RT_OFFSET 42996 +#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ27_RT_OFFSET 42997 +#define PBF_REG_YCMD_QS_NUM_LINES_VOQ28_RT_OFFSET 42998 +#define PBF_REG_BTB_GUARANTEED_VOQ28_RT_OFFSET 42999 +#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ28_RT_OFFSET 43000 +#define PBF_REG_YCMD_QS_NUM_LINES_VOQ29_RT_OFFSET 43001 +#define PBF_REG_BTB_GUARANTEED_VOQ29_RT_OFFSET 43002 +#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ29_RT_OFFSET 43003 +#define PBF_REG_YCMD_QS_NUM_LINES_VOQ30_RT_OFFSET 43004 +#define PBF_REG_BTB_GUARANTEED_VOQ30_RT_OFFSET 43005 +#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ30_RT_OFFSET 43006 +#define PBF_REG_YCMD_QS_NUM_LINES_VOQ31_RT_OFFSET 43007 +#define PBF_REG_BTB_GUARANTEED_VOQ31_RT_OFFSET 43008 +#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ31_RT_OFFSET 43009 +#define PBF_REG_YCMD_QS_NUM_LINES_VOQ32_RT_OFFSET 43010 +#define PBF_REG_BTB_GUARANTEED_VOQ32_RT_OFFSET 43011 +#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ32_RT_OFFSET 43012 +#define PBF_REG_YCMD_QS_NUM_LINES_VOQ33_RT_OFFSET 43013 +#define PBF_REG_BTB_GUARANTEED_VOQ33_RT_OFFSET 43014 +#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ33_RT_OFFSET 43015 +#define PBF_REG_YCMD_QS_NUM_LINES_VOQ34_RT_OFFSET 43016 +#define PBF_REG_BTB_GUARANTEED_VOQ34_RT_OFFSET 43017 +#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ34_RT_OFFSET 43018 +#define PBF_REG_YCMD_QS_NUM_LINES_VOQ35_RT_OFFSET 43019 +#define PBF_REG_BTB_GUARANTEED_VOQ35_RT_OFFSET 43020 +#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ35_RT_OFFSET 43021 +#define XCM_REG_CON_PHY_Q3_RT_OFFSET 43022 -#define RUNTIME_ARRAY_SIZE 41743 +#define RUNTIME_ARRAY_SIZE 43023 + +/* Init Callbacks */ +#define DMAE_READY_CB 0 #endif /* __RT_DEFS_H__ */ |