diff options
Diffstat (limited to 'drivers/net/qede/base/reg_addr.h')
| -rw-r--r-- | drivers/net/qede/base/reg_addr.h | 76 |
1 files changed, 51 insertions, 25 deletions
diff --git a/drivers/net/qede/base/reg_addr.h b/drivers/net/qede/base/reg_addr.h index 402f6204..be59f773 100644 --- a/drivers/net/qede/base/reg_addr.h +++ b/drivers/net/qede/base/reg_addr.h @@ -8,13 +8,13 @@ 0 #define CDU_REG_CID_ADDR_PARAMS_CONTEXT_SIZE ( \ - 0xfff << 0) + 0xfffUL << 0) #define CDU_REG_CID_ADDR_PARAMS_BLOCK_WASTE_SHIFT \ 12 #define CDU_REG_CID_ADDR_PARAMS_BLOCK_WASTE ( \ - 0xfff << 12) + 0xfffUL << 12) #define CDU_REG_CID_ADDR_PARAMS_NCIB_SHIFT \ 24 @@ -322,6 +322,21 @@ 0x180820UL #define IGU_REG_ATTN_MSG_ADDR_H \ 0x180824UL +#define IGU_REG_LEADING_EDGE_LATCH \ + 0x18082cUL +#define IGU_REG_TRAILING_EDGE_LATCH \ + 0x180830UL +#define IGU_REG_ATTENTION_ACK_BITS \ + 0x180838UL +#define IGU_REG_PBA_STS_PF \ + 0x180d20UL +#define IGU_REG_PF_FUNCTIONAL_CLEANUP \ + 0x181210UL +#define IGU_REG_STATISTIC_NUM_OF_INTA_ASSERTED \ + 0x18042cUL +#define IGU_REG_PBA_STS_PF_SIZE 5 +#define IGU_REG_PBA_STS_PF \ + 0x180d20UL #define MISC_REG_AEU_GENERAL_ATTN_0 \ 0x008400UL #define CAU_REG_SB_ADDR_MEMORY \ @@ -351,9 +366,9 @@ #define IGU_REG_COMMAND_REG_CTRL \ 0x180848UL #define IGU_REG_BLOCK_CONFIGURATION_VF_CLEANUP_EN ( \ - 0x1 << 1) + 0x1UL << 1) #define IGU_REG_BLOCK_CONFIGURATION_PXP_TPH_INTERFACE_EN ( \ - 0x1 << 0) + 0x1UL << 0) #define IGU_REG_MAPPING_MEMORY \ 0x184000UL #define MISCS_REG_GENERIC_POR_0 \ @@ -361,7 +376,7 @@ #define MCP_REG_NVM_CFG4 \ 0xe0642cUL #define MCP_REG_NVM_CFG4_FLASH_SIZE ( \ - 0x7 << 0) + 0x7UL << 0) #define MCP_REG_NVM_CFG4_FLASH_SIZE_SHIFT \ 0 #define CCFC_REG_STRONG_ENABLE_VF 0x2e070cUL @@ -394,7 +409,7 @@ #define XMAC_REG_TX_CTRL_LO 0x210020UL #define XMAC_REG_CTRL 0x210000UL #define XMAC_REG_RX_CTRL 0x210030UL -#define XMAC_REG_RX_CTRL_PROCESS_VARIABLE_PREAMBLE (0x1 << 12) +#define XMAC_REG_RX_CTRL_PROCESS_VARIABLE_PREAMBLE (0x1UL << 12) #define MISC_REG_CLK_100G_MODE 0x008c10UL #define MISC_REG_OPTE_MODE 0x008c0cUL #define NIG_REG_LLH_ENG_CLS_TCP_4_TUPLE_SEARCH 0x501b84UL @@ -424,16 +439,16 @@ #define NIG_REG_LLH_FUNC_FILTER_EN 0x501a80UL #define NIG_REG_LLH_FUNC_FILTER_EN_SIZE 16 #define NIG_REG_LLH_FUNC_FILTER_VALUE 0x501a00UL -#define XMAC_REG_CTRL_TX_EN (0x1 << 0) -#define XMAC_REG_CTRL_RX_EN (0x1 << 1) +#define XMAC_REG_CTRL_TX_EN (0x1UL << 0) +#define XMAC_REG_CTRL_RX_EN (0x1UL << 1) #define CDU_REG_SEGMENT0_PARAMS_T0_TID_SIZE (0xffUL << 24) /* @DPDK */ -#define CDU_REG_SEGMENT0_PARAMS_T0_TID_BLOCK_WASTE (0xff << 16) +#define CDU_REG_SEGMENT0_PARAMS_T0_TID_BLOCK_WASTE (0xffUL << 16) #define CDU_REG_SEGMENT0_PARAMS_T0_TID_BLOCK_WASTE_SHIFT 16 -#define CDU_REG_SEGMENT1_PARAMS_T1_TID_BLOCK_WASTE (0xff << 16) +#define CDU_REG_SEGMENT1_PARAMS_T1_TID_BLOCK_WASTE (0xffUL << 16) #define CDU_REG_SEGMENT1_PARAMS_T1_TID_SIZE (0xffUL << 24) /* @DPDK */ -#define CDU_REG_SEGMENT1_PARAMS_T1_NUM_TIDS_IN_BLOCK (0xfff << 0) +#define CDU_REG_SEGMENT1_PARAMS_T1_NUM_TIDS_IN_BLOCK (0xfffUL << 0) #define CDU_REG_SEGMENT1_PARAMS_T1_NUM_TIDS_IN_BLOCK_SHIFT 0 -#define CDU_REG_SEGMENT0_PARAMS_T0_NUM_TIDS_IN_BLOCK (0xfff << 0) +#define CDU_REG_SEGMENT0_PARAMS_T0_NUM_TIDS_IN_BLOCK (0xfffUL << 0) #define CDU_REG_SEGMENT0_PARAMS_T0_NUM_TIDS_IN_BLOCK_SHIFT 0 #define PSWRQ2_REG_ILT_MEMORY 0x260000UL #define QM_REG_WFQPFWEIGHT 0x2f4e80UL @@ -521,7 +536,7 @@ #define MISC_REG_AEU_GENERAL_ATTN_35 0x00848cUL #define MCP_REG_CPU_STATE 0xe05004UL #define MCP_REG_CPU_MODE 0xe05000UL -#define MCP_REG_CPU_MODE_SOFT_HALT (0x1 << 10) +#define MCP_REG_CPU_MODE_SOFT_HALT (0x1UL << 10) #define MCP_REG_CPU_EVENT_MASK 0xe05008UL #define PSWHST_REG_VF_DISABLED_ERROR_VALID 0x2a0060UL #define PSWHST_REG_VF_DISABLED_ERROR_ADDRESS 0x2a0064UL @@ -550,15 +565,15 @@ #define PGLUE_B_REG_VF_ILT_ERR_ADD_63_32 0x2aae78UL #define PGLUE_B_REG_VF_ILT_ERR_DETAILS 0x2aae7cUL #define PGLUE_B_REG_LATCHED_ERRORS_CLR 0x2aa3bcUL -#define NIG_REG_INT_MASK_3_P0_LB_TC1_PAUSE_TOO_LONG_INT (0x1 << 10) +#define NIG_REG_INT_MASK_3_P0_LB_TC1_PAUSE_TOO_LONG_INT (0x1UL << 10) #define DORQ_REG_DB_DROP_REASON 0x100a2cUL #define DORQ_REG_DB_DROP_DETAILS 0x100a24UL #define TM_REG_INT_STS_1 0x2c0190UL -#define TM_REG_INT_STS_1_PEND_TASK_SCAN (0x1 << 6) -#define TM_REG_INT_STS_1_PEND_CONN_SCAN (0x1 << 5) +#define TM_REG_INT_STS_1_PEND_TASK_SCAN (0x1UL << 6) +#define TM_REG_INT_STS_1_PEND_CONN_SCAN (0x1UL << 5) #define TM_REG_INT_MASK_1 0x2c0194UL -#define TM_REG_INT_MASK_1_PEND_CONN_SCAN (0x1 << 5) -#define TM_REG_INT_MASK_1_PEND_TASK_SCAN (0x1 << 6) +#define TM_REG_INT_MASK_1_PEND_CONN_SCAN (0x1UL << 5) +#define TM_REG_INT_MASK_1_PEND_TASK_SCAN (0x1UL << 6) #define MISC_REG_AEU_AFTER_INVERT_1_IGU 0x0087b4UL #define MISC_REG_AEU_ENABLE4_IGU_OUT_0 0x0084a8UL #define MISC_REG_AEU_ENABLE3_IGU_OUT_0 0x0084a4UL @@ -1172,10 +1187,10 @@ #define XMAC_REG_RX_MAX_SIZE_BB 0x210040UL #define XMAC_REG_TX_CTRL_LO_BB 0x210020UL #define XMAC_REG_CTRL_BB 0x210000UL -#define XMAC_REG_CTRL_TX_EN_BB (0x1 << 0) -#define XMAC_REG_CTRL_RX_EN_BB (0x1 << 1) +#define XMAC_REG_CTRL_TX_EN_BB (0x1UL << 0) +#define XMAC_REG_CTRL_RX_EN_BB (0x1UL << 1) #define XMAC_REG_RX_CTRL_BB 0x210030UL -#define XMAC_REG_RX_CTRL_PROCESS_VARIABLE_PREAMBLE_BB (0x1 << 12) +#define XMAC_REG_RX_CTRL_PROCESS_VARIABLE_PREAMBLE_BB (0x1UL << 12) #define PGLUE_B_REG_PGL_ADDR_E8_F0_K2_E5 0x2aaf98UL #define PGLUE_B_REG_PGL_ADDR_EC_F0_K2_E5 0x2aaf9cUL @@ -1202,15 +1217,26 @@ #define DORQ_REG_DPM_FORCE_ABORT 0x1009d8UL #define DORQ_REG_PF_OVFL_STICKY 0x1009d0UL #define DORQ_REG_INT_STS 0x100180UL - #define DORQ_REG_INT_STS_DB_DROP (0x1 << 1) - #define DORQ_REG_INT_STS_DORQ_FIFO_OVFL_ERR (0x1 << 2) - #define DORQ_REG_INT_STS_DORQ_FIFO_AFULL (0x1 << 3) + #define DORQ_REG_INT_STS_DB_DROP (0x1UL << 1) + #define DORQ_REG_INT_STS_DORQ_FIFO_OVFL_ERR (0x1UL << 2) + #define DORQ_REG_INT_STS_DORQ_FIFO_AFULL (0x1UL << 3) #define DORQ_REG_DB_DROP_DETAILS_REL 0x100a28UL #define DORQ_REG_INT_STS_WR 0x100188UL #define DORQ_REG_DB_DROP_DETAILS_REASON 0x100a20UL #define MCP_REG_CPU_PROGRAM_COUNTER 0xe0501cUL - #define MCP_REG_CPU_STATE_SOFT_HALTED (0x1 << 10) + #define MCP_REG_CPU_STATE_SOFT_HALTED (0x1UL << 10) #define PRS_REG_SEARCH_TENANT_ID 0x1f044cUL #define PGLUE_B_REG_VF_BAR1_SIZE 0x2aae68UL #define RSS_REG_RSS_RAM_MASK 0x238c10UL + +#define NIG_REG_LLH_FUNC_TAG_EN 0x5019b0UL +#define NIG_REG_LLH_FUNC_TAG_VALUE 0x5019d0UL +#define DORQ_REG_TAG1_OVRD_MODE 0x1008b4UL +#define DORQ_REG_PF_PCP_BB_K2 0x1008c4UL +#define DORQ_REG_PF_EXT_VID_BB_K2 0x1008c8UL +#define PRS_REG_SEARCH_NON_IP_AS_GFT 0x1f11c0UL +#define NIG_REG_LLH_PPFID2PFID_TBL_0 0x501970UL +#define NIG_REG_PPF_TO_ENGINE_SEL 0x508900UL +#define NIG_REG_LLH_ENG_CLS_ROCE_QP_SEL 0x501b98UL +#define NIG_REG_LLH_FUNC_FILTER_HDR_SEL_BB_K2 0x501b40UL |