diff options
Diffstat (limited to 'drivers/net/qede/base')
23 files changed, 1243 insertions, 851 deletions
diff --git a/drivers/net/qede/base/bcm_osal.c b/drivers/net/qede/base/bcm_osal.c index 3f895cd4..2603a8b3 100644 --- a/drivers/net/qede/base/bcm_osal.c +++ b/drivers/net/qede/base/bcm_osal.c @@ -16,6 +16,10 @@ #include "ecore_mcp_api.h" #include "ecore_l2_api.h" +/* Array of memzone pointers */ +static const struct rte_memzone *ecore_mz_mapping[RTE_MAX_MEMZONE]; +/* Counter to track current memzone allocated */ +uint16_t ecore_mz_count; unsigned long qede_log2_align(unsigned long n) { @@ -118,6 +122,13 @@ void *osal_dma_alloc_coherent(struct ecore_dev *p_dev, uint32_t core_id = rte_lcore_id(); unsigned int socket_id; + if (ecore_mz_count >= RTE_MAX_MEMZONE) { + DP_ERR(p_dev, "Memzone allocation count exceeds %u\n", + RTE_MAX_MEMZONE); + *phys = 0; + return OSAL_NULL; + } + OSAL_MEM_ZERO(mz_name, sizeof(*mz_name)); snprintf(mz_name, sizeof(mz_name) - 1, "%lx", (unsigned long)rte_get_timer_cycles()); @@ -134,9 +145,11 @@ void *osal_dma_alloc_coherent(struct ecore_dev *p_dev, return OSAL_NULL; } *phys = mz->phys_addr; - DP_VERBOSE(p_dev, ECORE_MSG_PROBE, - "size=%zu phys=0x%" PRIx64 " virt=%p on socket=%u\n", - mz->len, mz->phys_addr, mz->addr, socket_id); + ecore_mz_mapping[ecore_mz_count++] = mz; + DP_VERBOSE(p_dev, ECORE_MSG_SP, + "Allocated dma memory size=%zu phys=0x%lx" + " virt=%p core=%d\n", + mz->len, (unsigned long)mz->phys_addr, mz->addr, core_id); return mz->addr; } @@ -148,6 +161,13 @@ void *osal_dma_alloc_coherent_aligned(struct ecore_dev *p_dev, uint32_t core_id = rte_lcore_id(); unsigned int socket_id; + if (ecore_mz_count >= RTE_MAX_MEMZONE) { + DP_ERR(p_dev, "Memzone allocation count exceeds %u\n", + RTE_MAX_MEMZONE); + *phys = 0; + return OSAL_NULL; + } + OSAL_MEM_ZERO(mz_name, sizeof(*mz_name)); snprintf(mz_name, sizeof(mz_name) - 1, "%lx", (unsigned long)rte_get_timer_cycles()); @@ -163,12 +183,30 @@ void *osal_dma_alloc_coherent_aligned(struct ecore_dev *p_dev, return OSAL_NULL; } *phys = mz->phys_addr; - DP_VERBOSE(p_dev, ECORE_MSG_PROBE, - "aligned memory size=%zu phys=0x%" PRIx64 " virt=%p core=%d\n", - mz->len, mz->phys_addr, mz->addr, core_id); + ecore_mz_mapping[ecore_mz_count++] = mz; + DP_VERBOSE(p_dev, ECORE_MSG_SP, + "Allocated aligned dma memory size=%zu phys=0x%lx" + " virt=%p core=%d\n", + mz->len, (unsigned long)mz->phys_addr, mz->addr, core_id); return mz->addr; } +void osal_dma_free_mem(struct ecore_dev *p_dev, dma_addr_t phys) +{ + uint16_t j; + + for (j = 0 ; j < ecore_mz_count; j++) { + if (phys == ecore_mz_mapping[j]->phys_addr) { + DP_VERBOSE(p_dev, ECORE_MSG_SP, + "Free memzone %s\n", ecore_mz_mapping[j]->name); + rte_memzone_free(ecore_mz_mapping[j]); + return; + } + } + + DP_ERR(p_dev, "Unexpected memory free request\n"); +} + #ifdef CONFIG_ECORE_ZIPPED_FW u32 qede_unzip_data(struct ecore_hwfn *p_hwfn, u32 input_len, u8 *input_buf, u32 max_size, u8 *unzip_buf) @@ -211,11 +249,46 @@ qede_get_mcp_proto_stats(struct ecore_dev *edev, if (type == ECORE_MCP_LAN_STATS) { ecore_get_vport_stats(edev, &lan_stats); - stats->lan_stats.ucast_rx_pkts = lan_stats.rx_ucast_pkts; - stats->lan_stats.ucast_tx_pkts = lan_stats.tx_ucast_pkts; + + /* @DPDK */ + stats->lan_stats.ucast_rx_pkts = lan_stats.common.rx_ucast_pkts; + stats->lan_stats.ucast_tx_pkts = lan_stats.common.tx_ucast_pkts; + stats->lan_stats.fcs_err = -1; } else { DP_INFO(edev, "Statistics request type %d not supported\n", type); } } + +void +qede_hw_err_notify(struct ecore_hwfn *p_hwfn, enum ecore_hw_err_type err_type) +{ + char err_str[64]; + + switch (err_type) { + case ECORE_HW_ERR_FAN_FAIL: + strcpy(err_str, "Fan Failure"); + break; + case ECORE_HW_ERR_MFW_RESP_FAIL: + strcpy(err_str, "MFW Response Failure"); + break; + case ECORE_HW_ERR_HW_ATTN: + strcpy(err_str, "HW Attention"); + break; + case ECORE_HW_ERR_DMAE_FAIL: + strcpy(err_str, "DMAE Failure"); + break; + case ECORE_HW_ERR_RAMROD_FAIL: + strcpy(err_str, "Ramrod Failure"); + break; + case ECORE_HW_ERR_FW_ASSERT: + strcpy(err_str, "FW Assertion"); + break; + default: + strcpy(err_str, "Unknown"); + } + + DP_ERR(p_hwfn, "HW error occurred [%s]\n", err_str); + ecore_int_attn_clr_enable(p_hwfn->p_dev, true); +} diff --git a/drivers/net/qede/base/bcm_osal.h b/drivers/net/qede/base/bcm_osal.h index 32c9b251..3acf8f7c 100644 --- a/drivers/net/qede/base/bcm_osal.h +++ b/drivers/net/qede/base/bcm_osal.h @@ -27,6 +27,7 @@ struct ecore_vf_acquire_sw_info; struct vf_pf_resc_request; enum ecore_mcp_protocol_type; union ecore_mcp_protocol_stats; +enum ecore_hw_err_type; void qed_link_update(struct ecore_hwfn *hwfn); @@ -107,14 +108,16 @@ void *osal_dma_alloc_coherent(struct ecore_dev *, dma_addr_t *, size_t); void *osal_dma_alloc_coherent_aligned(struct ecore_dev *, dma_addr_t *, size_t, int); +void osal_dma_free_mem(struct ecore_dev *edev, dma_addr_t phys); + #define OSAL_DMA_ALLOC_COHERENT(dev, phys, size) \ osal_dma_alloc_coherent(dev, phys, size) #define OSAL_DMA_ALLOC_COHERENT_ALIGNED(dev, phys, size, align) \ osal_dma_alloc_coherent_aligned(dev, phys, size, align) -/* TODO: */ -#define OSAL_DMA_FREE_COHERENT(dev, virt, phys, size) nothing +#define OSAL_DMA_FREE_COHERENT(dev, virt, phys, size) \ + osal_dma_free_mem(dev, phys) /* HW reads/writes */ @@ -348,6 +351,8 @@ u32 qede_unzip_data(struct ecore_hwfn *p_hwfn, u32 input_len, u8 *input_buf, u32 max_size, u8 *unzip_buf); void qede_vf_fill_driver_data(struct ecore_hwfn *, struct vf_pf_resc_request *, struct ecore_vf_acquire_sw_info *); +void qede_hw_err_notify(struct ecore_hwfn *p_hwfn, + enum ecore_hw_err_type err_type); #define OSAL_VF_FILL_ACQUIRE_RESC_REQ(_dev_p, _resc_req, _os_info) \ qede_vf_fill_driver_data(_dev_p, _resc_req, _os_info) @@ -356,7 +361,8 @@ void qede_vf_fill_driver_data(struct ecore_hwfn *, struct vf_pf_resc_request *, /* TODO: */ #define OSAL_SCHEDULE_RECOVERY_HANDLER(hwfn) nothing -#define OSAL_HW_ERROR_OCCURRED(hwfn, err_type) nothing +#define OSAL_HW_ERROR_OCCURRED(hwfn, err_type) \ + qede_hw_err_notify(hwfn, err_type) #define OSAL_NVM_IS_ACCESS_ENABLED(hwfn) (1) #define OSAL_NUM_ACTIVE_CPU() 0 @@ -421,6 +427,9 @@ void qede_get_mcp_proto_stats(struct ecore_dev *, enum ecore_mcp_protocol_type, qede_get_mcp_proto_stats(dev, type, stats) #define OSAL_SLOWPATH_IRQ_REQ(p_hwfn) (0) +#define OSAL_CRC32(crc, buf, length) 0 +#define OSAL_CRC8_POPULATE(table, polynomial) nothing +#define OSAL_CRC8(table, pdata, nbytes, crc) 0 #define OSAL_MFW_TLV_REQ(p_hwfn) (0) #define OSAL_MFW_FILL_TLV_DATA(type, buf, data) (0) #define OSAL_PF_VALIDATE_MODIFY_TUNN_CONFIG(p_hwfn, mask, b_update, tunn) 0 diff --git a/drivers/net/qede/base/common_hsi.h b/drivers/net/qede/base/common_hsi.h index cbcde227..bfe50e1f 100644 --- a/drivers/net/qede/base/common_hsi.h +++ b/drivers/net/qede/base/common_hsi.h @@ -97,8 +97,8 @@ #define FW_MAJOR_VERSION 8 -#define FW_MINOR_VERSION 18 -#define FW_REVISION_VERSION 9 +#define FW_MINOR_VERSION 20 +#define FW_REVISION_VERSION 0 #define FW_ENGINEERING_VERSION 0 /***********************/ @@ -913,24 +913,25 @@ struct db_l2_dpm_data { __le16 bd_prod /* bd producer value to update */; __le32 params; /* Size in QWORD-s of the DPM burst */ -#define DB_L2_DPM_DATA_SIZE_MASK 0x3F -#define DB_L2_DPM_DATA_SIZE_SHIFT 0 +#define DB_L2_DPM_DATA_SIZE_MASK 0x3F +#define DB_L2_DPM_DATA_SIZE_SHIFT 0 /* Type of DPM transaction (DPM_L2_INLINE or DPM_L2_BD) (use enum db_dpm_type) */ -#define DB_L2_DPM_DATA_DPM_TYPE_MASK 0x3 -#define DB_L2_DPM_DATA_DPM_TYPE_SHIFT 6 -#define DB_L2_DPM_DATA_NUM_BDS_MASK 0xFF /* number of BD-s */ -#define DB_L2_DPM_DATA_NUM_BDS_SHIFT 8 +#define DB_L2_DPM_DATA_DPM_TYPE_MASK 0x3 +#define DB_L2_DPM_DATA_DPM_TYPE_SHIFT 6 +#define DB_L2_DPM_DATA_NUM_BDS_MASK 0xFF /* number of BD-s */ +#define DB_L2_DPM_DATA_NUM_BDS_SHIFT 8 /* size of the packet to be transmitted in bytes */ -#define DB_L2_DPM_DATA_PKT_SIZE_MASK 0x7FF -#define DB_L2_DPM_DATA_PKT_SIZE_SHIFT 16 -#define DB_L2_DPM_DATA_RESERVED0_MASK 0x1 -#define DB_L2_DPM_DATA_RESERVED0_SHIFT 27 +#define DB_L2_DPM_DATA_PKT_SIZE_MASK 0x7FF +#define DB_L2_DPM_DATA_PKT_SIZE_SHIFT 16 +#define DB_L2_DPM_DATA_RESERVED0_MASK 0x1 +#define DB_L2_DPM_DATA_RESERVED0_SHIFT 27 /* In DPM_L2_BD mode: the number of SGE-s */ -#define DB_L2_DPM_DATA_SGE_NUM_MASK 0x7 -#define DB_L2_DPM_DATA_SGE_NUM_SHIFT 28 -#define DB_L2_DPM_DATA_RESERVED1_MASK 0x1 -#define DB_L2_DPM_DATA_RESERVED1_SHIFT 31 +#define DB_L2_DPM_DATA_SGE_NUM_MASK 0x7 +#define DB_L2_DPM_DATA_SGE_NUM_SHIFT 28 +/* Flag indicating whether to enable GFS search */ +#define DB_L2_DPM_DATA_RESERVED1_MASK 0x1 +#define DB_L2_DPM_DATA_RESERVED1_SHIFT 31 }; /* @@ -989,26 +990,29 @@ struct db_pwm_addr { struct db_rdma_dpm_params { __le32 params; /* Size in QWORD-s of the DPM burst */ -#define DB_RDMA_DPM_PARAMS_SIZE_MASK 0x3F -#define DB_RDMA_DPM_PARAMS_SIZE_SHIFT 0 +#define DB_RDMA_DPM_PARAMS_SIZE_MASK 0x3F +#define DB_RDMA_DPM_PARAMS_SIZE_SHIFT 0 /* Type of DPM transacation (DPM_RDMA) (use enum db_dpm_type) */ -#define DB_RDMA_DPM_PARAMS_DPM_TYPE_MASK 0x3 -#define DB_RDMA_DPM_PARAMS_DPM_TYPE_SHIFT 6 +#define DB_RDMA_DPM_PARAMS_DPM_TYPE_MASK 0x3 +#define DB_RDMA_DPM_PARAMS_DPM_TYPE_SHIFT 6 /* opcode for RDMA operation */ -#define DB_RDMA_DPM_PARAMS_OPCODE_MASK 0xFF -#define DB_RDMA_DPM_PARAMS_OPCODE_SHIFT 8 +#define DB_RDMA_DPM_PARAMS_OPCODE_MASK 0xFF +#define DB_RDMA_DPM_PARAMS_OPCODE_SHIFT 8 /* the size of the WQE payload in bytes */ -#define DB_RDMA_DPM_PARAMS_WQE_SIZE_MASK 0x7FF -#define DB_RDMA_DPM_PARAMS_WQE_SIZE_SHIFT 16 -#define DB_RDMA_DPM_PARAMS_RESERVED0_MASK 0x1 -#define DB_RDMA_DPM_PARAMS_RESERVED0_SHIFT 27 +#define DB_RDMA_DPM_PARAMS_WQE_SIZE_MASK 0x7FF +#define DB_RDMA_DPM_PARAMS_WQE_SIZE_SHIFT 16 +#define DB_RDMA_DPM_PARAMS_RESERVED0_MASK 0x1 +#define DB_RDMA_DPM_PARAMS_RESERVED0_SHIFT 27 /* RoCE completion flag */ -#define DB_RDMA_DPM_PARAMS_COMPLETION_FLG_MASK 0x1 -#define DB_RDMA_DPM_PARAMS_COMPLETION_FLG_SHIFT 28 -#define DB_RDMA_DPM_PARAMS_S_FLG_MASK 0x1 /* RoCE S flag */ -#define DB_RDMA_DPM_PARAMS_S_FLG_SHIFT 29 -#define DB_RDMA_DPM_PARAMS_RESERVED1_MASK 0x3 -#define DB_RDMA_DPM_PARAMS_RESERVED1_SHIFT 30 +#define DB_RDMA_DPM_PARAMS_COMPLETION_FLG_MASK 0x1 +#define DB_RDMA_DPM_PARAMS_COMPLETION_FLG_SHIFT 28 +#define DB_RDMA_DPM_PARAMS_S_FLG_MASK 0x1 /* RoCE S flag */ +#define DB_RDMA_DPM_PARAMS_S_FLG_SHIFT 29 +#define DB_RDMA_DPM_PARAMS_RESERVED1_MASK 0x3 +#define DB_RDMA_DPM_PARAMS_RESERVED1_SHIFT 30 +/* Connection type is iWARP */ +#define DB_RDMA_DPM_PARAMS_CONN_TYPE_IS_IWARP_MASK 0x1 +#define DB_RDMA_DPM_PARAMS_CONN_TYPE_IS_IWARP_SHIFT 31 }; /* diff --git a/drivers/net/qede/base/ecore.h b/drivers/net/qede/base/ecore.h index 80b11a4c..0d68a9bc 100644 --- a/drivers/net/qede/base/ecore.h +++ b/drivers/net/qede/base/ecore.h @@ -31,7 +31,7 @@ #define ECORE_MAJOR_VERSION 8 #define ECORE_MINOR_VERSION 18 #define ECORE_REVISION_VERSION 7 -#define ECORE_ENGINEERING_VERSION 0 +#define ECORE_ENGINEERING_VERSION 1 #define ECORE_VERSION \ ((ECORE_MAJOR_VERSION << 24) | (ECORE_MINOR_VERSION << 16) | \ @@ -770,7 +770,7 @@ struct ecore_dev { bool attn_clr_en; /* Indicates whether allowing the MFW to collect a crash dump */ - bool mdump_en; + bool allow_mdump; /* Indicates if the reg_fifo is checked after any register access */ bool chk_reg_fifo; diff --git a/drivers/net/qede/base/ecore_dev.c b/drivers/net/qede/base/ecore_dev.c index 865103c6..65b89b8f 100644 --- a/drivers/net/qede/base/ecore_dev.c +++ b/drivers/net/qede/base/ecore_dev.c @@ -1080,7 +1080,7 @@ enum _ecore_status_t ecore_final_cleanup(struct ecore_hwfn *p_hwfn, } DP_VERBOSE(p_hwfn, ECORE_MSG_IOV, - "Sending final cleanup for PFVF[%d] [Command %08x\n]", + "Sending final cleanup for PFVF[%d] [Command %08x]\n", id, command); ecore_wr(p_hwfn, p_ptt, XSDM_REG_OPERATION_GEN, command); @@ -1776,13 +1776,6 @@ ecore_hw_init_pf(struct ecore_hwfn *p_hwfn, /* perform debug configuration when chip is out of reset */ OSAL_BEFORE_PF_START((void *)p_hwfn->p_dev, p_hwfn->my_id); - /* Cleanup chip from previous driver if such remains exist */ - rc = ecore_final_cleanup(p_hwfn, p_ptt, rel_pf_id, false); - if (rc != ECORE_SUCCESS) { - ecore_hw_err_notify(p_hwfn, ECORE_HW_ERR_RAMROD_FAIL); - return rc; - } - /* PF Init sequence */ rc = ecore_init_run(p_hwfn, p_ptt, PHASE_PF, rel_pf_id, hw_mode); if (rc) @@ -1866,17 +1859,17 @@ ecore_hw_init_pf(struct ecore_hwfn *p_hwfn, return rc; } -static enum _ecore_status_t -ecore_change_pci_hwfn(struct ecore_hwfn *p_hwfn, - struct ecore_ptt *p_ptt, u8 enable) +enum _ecore_status_t ecore_pglueb_set_pfid_enable(struct ecore_hwfn *p_hwfn, + struct ecore_ptt *p_ptt, + bool b_enable) { - u32 delay_idx = 0, val, set_val = enable ? 1 : 0; + u32 delay_idx = 0, val, set_val = b_enable ? 1 : 0; - /* Change PF in PXP */ + /* Configure the PF's internal FID_enable for master transactions */ ecore_wr(p_hwfn, p_ptt, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, set_val); - /* wait until value is set - try for 1 second every 50us */ + /* Wait until value is set - try for 1 second every 50us */ for (delay_idx = 0; delay_idx < 20000; delay_idx++) { val = ecore_rd(p_hwfn, p_ptt, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER); @@ -1918,14 +1911,21 @@ enum _ecore_status_t ecore_vf_start(struct ecore_hwfn *p_hwfn, return ECORE_SUCCESS; } +static void ecore_pglueb_clear_err(struct ecore_hwfn *p_hwfn, + struct ecore_ptt *p_ptt) +{ + ecore_wr(p_hwfn, p_ptt, PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR, + 1 << p_hwfn->abs_pf_id); +} + enum _ecore_status_t ecore_hw_init(struct ecore_dev *p_dev, struct ecore_hw_init_params *p_params) { struct ecore_load_req_params load_req_params; - u32 load_code, param, drv_mb_param; + u32 load_code, resp, param, drv_mb_param; bool b_default_mtu = true; struct ecore_hwfn *p_hwfn; - enum _ecore_status_t rc = ECORE_SUCCESS, mfw_rc; + enum _ecore_status_t rc = ECORE_SUCCESS; int i; if ((p_params->int_mode == ECORE_INT_MODE_MSI) && @@ -1942,7 +1942,7 @@ enum _ecore_status_t ecore_hw_init(struct ecore_dev *p_dev, } for_each_hwfn(p_dev, i) { - struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i]; + p_hwfn = &p_dev->hwfns[i]; /* If management didn't provide a default, set one of our own */ if (!p_hwfn->hw_info.mtu) { @@ -1955,11 +1955,6 @@ enum _ecore_status_t ecore_hw_init(struct ecore_dev *p_dev, continue; } - /* Enable DMAE in PXP */ - rc = ecore_change_pci_hwfn(p_hwfn, p_hwfn->p_main_ptt, true); - if (rc != ECORE_SUCCESS) - return rc; - rc = ecore_calc_hw_mode(p_hwfn); if (rc != ECORE_SUCCESS) return rc; @@ -2009,6 +2004,30 @@ enum _ecore_status_t ecore_hw_init(struct ecore_dev *p_dev, qm_lock_init = true; } + /* Clean up chip from previous driver if such remains exist. + * This is not needed when the PF is the first one on the + * engine, since afterwards we are going to init the FW. + */ + if (load_code != FW_MSG_CODE_DRV_LOAD_ENGINE) { + rc = ecore_final_cleanup(p_hwfn, p_hwfn->p_main_ptt, + p_hwfn->rel_pf_id, false); + if (rc != ECORE_SUCCESS) { + ecore_hw_err_notify(p_hwfn, + ECORE_HW_ERR_RAMROD_FAIL); + goto load_err; + } + } + + /* Log and clean previous pglue_b errors if such exist */ + ecore_pglueb_rbc_attn_handler(p_hwfn, p_hwfn->p_main_ptt); + ecore_pglueb_clear_err(p_hwfn, p_hwfn->p_main_ptt); + + /* Enable the PF's internal FID_enable in the PXP */ + rc = ecore_pglueb_set_pfid_enable(p_hwfn, p_hwfn->p_main_ptt, + true); + if (rc != ECORE_SUCCESS) + goto load_err; + switch (load_code) { case FW_MSG_CODE_DRV_LOAD_ENGINE: rc = ecore_hw_init_common(p_hwfn, p_hwfn->p_main_ptt, @@ -2037,35 +2056,28 @@ enum _ecore_status_t ecore_hw_init(struct ecore_dev *p_dev, break; } - if (rc != ECORE_SUCCESS) + if (rc != ECORE_SUCCESS) { DP_NOTICE(p_hwfn, true, "init phase failed for loadcode 0x%x (rc %d)\n", load_code, rc); + goto load_err; + } - /* ACK mfw regardless of success or failure of initialization */ - mfw_rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt, - DRV_MSG_CODE_LOAD_DONE, - 0, &load_code, ¶m); + rc = ecore_mcp_load_done(p_hwfn, p_hwfn->p_main_ptt); if (rc != ECORE_SUCCESS) return rc; - if (mfw_rc != ECORE_SUCCESS) { - DP_NOTICE(p_hwfn, true, - "Failed sending a LOAD_DONE command\n"); - return mfw_rc; - } - /* send DCBX attention request command */ DP_VERBOSE(p_hwfn, ECORE_MSG_DCB, "sending phony dcbx set command to trigger DCBx attention handling\n"); - mfw_rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt, - DRV_MSG_CODE_SET_DCBX, - 1 << DRV_MB_PARAM_DCBX_NOTIFY_SHIFT, - &load_code, ¶m); - if (mfw_rc != ECORE_SUCCESS) { + rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt, + DRV_MSG_CODE_SET_DCBX, + 1 << DRV_MB_PARAM_DCBX_NOTIFY_SHIFT, &resp, + ¶m); + if (rc != ECORE_SUCCESS) { DP_NOTICE(p_hwfn, true, "Failed to send DCBX attention request\n"); - return mfw_rc; + return rc; } p_hwfn->hw_init_done = true; @@ -2076,7 +2088,7 @@ enum _ecore_status_t ecore_hw_init(struct ecore_dev *p_dev, drv_mb_param = STORM_FW_VERSION; rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt, DRV_MSG_CODE_OV_UPDATE_STORM_FW_VER, - drv_mb_param, &load_code, ¶m); + drv_mb_param, &resp, ¶m); if (rc != ECORE_SUCCESS) DP_INFO(p_hwfn, "Failed to update firmware version\n"); @@ -2094,6 +2106,14 @@ enum _ecore_status_t ecore_hw_init(struct ecore_dev *p_dev, } return rc; + +load_err: + /* The MFW load lock should be released regardless of success or failure + * of initialization. + * TODO: replace this with an attempt to send cancel_load. + */ + ecore_mcp_load_done(p_hwfn, p_hwfn->p_main_ptt); + return rc; } #define ECORE_HW_STOP_RETRY_LIMIT (10) @@ -2261,18 +2281,20 @@ enum _ecore_status_t ecore_hw_stop(struct ecore_dev *p_dev) } } /* hwfn loop */ - if (IS_PF(p_dev)) { + if (IS_PF(p_dev) && !p_dev->recov_in_prog) { p_hwfn = ECORE_LEADING_HWFN(p_dev); p_ptt = ECORE_LEADING_HWFN(p_dev)->p_main_ptt; - /* Disable DMAE in PXP - in CMT, this should only be done for - * first hw-function, and only after all transactions have - * stopped for all active hw-functions. - */ - rc = ecore_change_pci_hwfn(p_hwfn, p_ptt, false); + /* Clear the PF's internal FID_enable in the PXP. + * In CMT this should only be done for first hw-function, and + * only after all transactions have stopped for all active + * hw-functions. + */ + rc = ecore_pglueb_set_pfid_enable(p_hwfn, p_hwfn->p_main_ptt, + false); if (rc != ECORE_SUCCESS) { DP_NOTICE(p_hwfn, true, - "ecore_change_pci_hwfn failed. rc = %d.\n", + "ecore_pglueb_set_pfid_enable() failed. rc = %d.\n", rc); rc2 = ECORE_UNKNOWN_ERROR; } @@ -2370,9 +2392,8 @@ static void ecore_hw_hwfn_prepare(struct ecore_hwfn *p_hwfn) PGLUE_B_REG_PGL_ADDR_94_F0_BB, 0); } - /* Clean Previous errors if such exist */ - ecore_wr(p_hwfn, p_hwfn->p_main_ptt, - PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR, 1 << p_hwfn->abs_pf_id); + /* Clean previous pglue_b errors if such exist */ + ecore_pglueb_clear_err(p_hwfn, p_hwfn->p_main_ptt); /* enable internal target-read */ ecore_wr(p_hwfn, p_hwfn->p_main_ptt, @@ -3565,6 +3586,7 @@ enum _ecore_status_t ecore_hw_prepare(struct ecore_dev *p_dev, enum _ecore_status_t rc; p_dev->chk_reg_fifo = p_params->chk_reg_fifo; + p_dev->allow_mdump = p_params->allow_mdump; if (p_params->b_relaxed_probe) p_params->p_relaxed_res = ECORE_HW_PREPARE_SUCCESS; @@ -3718,7 +3740,7 @@ static void ecore_chain_free_pbl(struct ecore_dev *p_dev, if (!p_chain->b_external_pbl) OSAL_DMA_FREE_COHERENT(p_dev, p_chain->pbl_sp.p_virt_table, p_chain->pbl_sp.p_phys_table, pbl_size); - out: +out: OSAL_VFREE(p_dev, p_chain->pbl.pp_virt_addr_tbl); } @@ -3994,92 +4016,182 @@ enum _ecore_status_t ecore_fw_rss_eng(struct ecore_hwfn *p_hwfn, return ECORE_SUCCESS; } -enum _ecore_status_t ecore_llh_add_mac_filter(struct ecore_hwfn *p_hwfn, - struct ecore_ptt *p_ptt, - u8 *p_filter) +static enum _ecore_status_t +ecore_llh_add_mac_filter_bb_ah(struct ecore_hwfn *p_hwfn, + struct ecore_ptt *p_ptt, u32 high, u32 low, + u32 *p_entry_num) { - u32 high, low, en; + u32 en; int i; - if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn))) - return ECORE_SUCCESS; - - high = p_filter[1] | (p_filter[0] << 8); - low = p_filter[5] | (p_filter[4] << 8) | - (p_filter[3] << 16) | (p_filter[2] << 24); - /* Find a free entry and utilize it */ for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) { en = ecore_rd(p_hwfn, p_ptt, - NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32)); + NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 + + i * sizeof(u32)); if (en) continue; ecore_wr(p_hwfn, p_ptt, - NIG_REG_LLH_FUNC_FILTER_VALUE + + NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 + 2 * i * sizeof(u32), low); ecore_wr(p_hwfn, p_ptt, - NIG_REG_LLH_FUNC_FILTER_VALUE + + NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 + (2 * i + 1) * sizeof(u32), high); ecore_wr(p_hwfn, p_ptt, - NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 0); + NIG_REG_LLH_FUNC_FILTER_MODE_BB_K2 + + i * sizeof(u32), 0); ecore_wr(p_hwfn, p_ptt, - NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE + + NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_BB_K2 + i * sizeof(u32), 0); ecore_wr(p_hwfn, p_ptt, - NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 1); + NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 + + i * sizeof(u32), 1); break; } - if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) { - DP_NOTICE(p_hwfn, false, - "Failed to find an empty LLH filter to utilize\n"); - return ECORE_INVAL; - } - DP_VERBOSE(p_hwfn, ECORE_MSG_HW, - "MAC: %x:%x:%x:%x:%x:%x is added at %d\n", - p_filter[0], p_filter[1], p_filter[2], - p_filter[3], p_filter[4], p_filter[5], i); + if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) + return ECORE_NORESOURCES; + + *p_entry_num = i; return ECORE_SUCCESS; } -void ecore_llh_remove_mac_filter(struct ecore_hwfn *p_hwfn, - struct ecore_ptt *p_ptt, u8 *p_filter) +enum _ecore_status_t ecore_llh_add_mac_filter(struct ecore_hwfn *p_hwfn, + struct ecore_ptt *p_ptt, u8 *p_filter) { - u32 high, low; - int i; + u32 high, low, entry_num; + enum _ecore_status_t rc; if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn))) - return; + return ECORE_SUCCESS; high = p_filter[1] | (p_filter[0] << 8); low = p_filter[5] | (p_filter[4] << 8) | - (p_filter[3] << 16) | (p_filter[2] << 24); + (p_filter[3] << 16) | (p_filter[2] << 24); + + if (ECORE_IS_BB(p_hwfn->p_dev) || ECORE_IS_AH(p_hwfn->p_dev)) + rc = ecore_llh_add_mac_filter_bb_ah(p_hwfn, p_ptt, high, low, + &entry_num); + if (rc != ECORE_SUCCESS) { + DP_NOTICE(p_hwfn, false, + "Failed to find an empty LLH filter to utilize\n"); + return rc; + } + + DP_VERBOSE(p_hwfn, ECORE_MSG_HW, + "MAC: %02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx is added at %d\n", + p_filter[0], p_filter[1], p_filter[2], p_filter[3], + p_filter[4], p_filter[5], entry_num); + + return ECORE_SUCCESS; +} + +static enum _ecore_status_t +ecore_llh_remove_mac_filter_bb_ah(struct ecore_hwfn *p_hwfn, + struct ecore_ptt *p_ptt, u32 high, u32 low, + u32 *p_entry_num) +{ + int i; /* Find the entry and clean it */ for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) { if (ecore_rd(p_hwfn, p_ptt, - NIG_REG_LLH_FUNC_FILTER_VALUE + + NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 + 2 * i * sizeof(u32)) != low) continue; if (ecore_rd(p_hwfn, p_ptt, - NIG_REG_LLH_FUNC_FILTER_VALUE + + NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 + (2 * i + 1) * sizeof(u32)) != high) continue; ecore_wr(p_hwfn, p_ptt, - NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 0); + NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 + i * sizeof(u32), 0); ecore_wr(p_hwfn, p_ptt, - NIG_REG_LLH_FUNC_FILTER_VALUE + + NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 + 2 * i * sizeof(u32), 0); ecore_wr(p_hwfn, p_ptt, - NIG_REG_LLH_FUNC_FILTER_VALUE + + NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 + (2 * i + 1) * sizeof(u32), 0); break; } + if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) + return ECORE_INVAL; + + *p_entry_num = i; + + return ECORE_SUCCESS; +} + +void ecore_llh_remove_mac_filter(struct ecore_hwfn *p_hwfn, + struct ecore_ptt *p_ptt, u8 *p_filter) +{ + u32 high, low, entry_num; + enum _ecore_status_t rc; + + if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn))) + return; + + high = p_filter[1] | (p_filter[0] << 8); + low = p_filter[5] | (p_filter[4] << 8) | + (p_filter[3] << 16) | (p_filter[2] << 24); + + if (ECORE_IS_BB(p_hwfn->p_dev) || ECORE_IS_AH(p_hwfn->p_dev)) + rc = ecore_llh_remove_mac_filter_bb_ah(p_hwfn, p_ptt, high, + low, &entry_num); + if (rc != ECORE_SUCCESS) { DP_NOTICE(p_hwfn, false, "Tried to remove a non-configured filter\n"); + return; + } + + + DP_VERBOSE(p_hwfn, ECORE_MSG_HW, + "MAC: %02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx was removed from %d\n", + p_filter[0], p_filter[1], p_filter[2], p_filter[3], + p_filter[4], p_filter[5], entry_num); +} + +static enum _ecore_status_t +ecore_llh_add_protocol_filter_bb_ah(struct ecore_hwfn *p_hwfn, + struct ecore_ptt *p_ptt, + enum ecore_llh_port_filter_type_t type, + u32 high, u32 low, u32 *p_entry_num) +{ + u32 en; + int i; + + /* Find a free entry and utilize it */ + for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) { + en = ecore_rd(p_hwfn, p_ptt, + NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 + + i * sizeof(u32)); + if (en) + continue; + ecore_wr(p_hwfn, p_ptt, + NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 + + 2 * i * sizeof(u32), low); + ecore_wr(p_hwfn, p_ptt, + NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 + + (2 * i + 1) * sizeof(u32), high); + ecore_wr(p_hwfn, p_ptt, + NIG_REG_LLH_FUNC_FILTER_MODE_BB_K2 + + i * sizeof(u32), 1); + ecore_wr(p_hwfn, p_ptt, + NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_BB_K2 + + i * sizeof(u32), 1 << type); + ecore_wr(p_hwfn, p_ptt, + NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 + i * sizeof(u32), 1); + break; + } + + if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) + return ECORE_NORESOURCES; + + *p_entry_num = i; + + return ECORE_SUCCESS; } enum _ecore_status_t @@ -4089,14 +4201,15 @@ ecore_llh_add_protocol_filter(struct ecore_hwfn *p_hwfn, u16 dest_port, enum ecore_llh_port_filter_type_t type) { - u32 high, low, en; - int i; + u32 high, low, entry_num; + enum _ecore_status_t rc; if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn))) return ECORE_SUCCESS; high = 0; low = 0; + switch (type) { case ECORE_LLH_FILTER_ETHERTYPE: high = source_port_or_eth_type; @@ -4118,67 +4231,109 @@ ecore_llh_add_protocol_filter(struct ecore_hwfn *p_hwfn, "Non valid LLH protocol filter type %d\n", type); return ECORE_INVAL; } - /* Find a free entry and utilize it */ - for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) { - en = ecore_rd(p_hwfn, p_ptt, - NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32)); - if (en) - continue; - ecore_wr(p_hwfn, p_ptt, - NIG_REG_LLH_FUNC_FILTER_VALUE + - 2 * i * sizeof(u32), low); - ecore_wr(p_hwfn, p_ptt, - NIG_REG_LLH_FUNC_FILTER_VALUE + - (2 * i + 1) * sizeof(u32), high); - ecore_wr(p_hwfn, p_ptt, - NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 1); - ecore_wr(p_hwfn, p_ptt, - NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE + - i * sizeof(u32), 1 << type); - ecore_wr(p_hwfn, p_ptt, - NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 1); - break; - } - if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) { + + if (ECORE_IS_BB(p_hwfn->p_dev) || ECORE_IS_AH(p_hwfn->p_dev)) + rc = ecore_llh_add_protocol_filter_bb_ah(p_hwfn, p_ptt, type, + high, low, &entry_num); + if (rc != ECORE_SUCCESS) { DP_NOTICE(p_hwfn, false, "Failed to find an empty LLH filter to utilize\n"); - return ECORE_NORESOURCES; + return rc; } switch (type) { case ECORE_LLH_FILTER_ETHERTYPE: DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "ETH type %x is added at %d\n", - source_port_or_eth_type, i); + source_port_or_eth_type, entry_num); break; case ECORE_LLH_FILTER_TCP_SRC_PORT: DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "TCP src port %x is added at %d\n", - source_port_or_eth_type, i); + source_port_or_eth_type, entry_num); break; case ECORE_LLH_FILTER_UDP_SRC_PORT: DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "UDP src port %x is added at %d\n", - source_port_or_eth_type, i); + source_port_or_eth_type, entry_num); break; case ECORE_LLH_FILTER_TCP_DEST_PORT: DP_VERBOSE(p_hwfn, ECORE_MSG_HW, - "TCP dst port %x is added at %d\n", dest_port, i); + "TCP dst port %x is added at %d\n", dest_port, + entry_num); break; case ECORE_LLH_FILTER_UDP_DEST_PORT: DP_VERBOSE(p_hwfn, ECORE_MSG_HW, - "UDP dst port %x is added at %d\n", dest_port, i); + "UDP dst port %x is added at %d\n", dest_port, + entry_num); break; case ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT: DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "TCP src/dst ports %x/%x are added at %d\n", - source_port_or_eth_type, dest_port, i); + source_port_or_eth_type, dest_port, entry_num); break; case ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT: DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "UDP src/dst ports %x/%x are added at %d\n", - source_port_or_eth_type, dest_port, i); + source_port_or_eth_type, dest_port, entry_num); break; } + + return ECORE_SUCCESS; +} + +static enum _ecore_status_t +ecore_llh_remove_protocol_filter_bb_ah(struct ecore_hwfn *p_hwfn, + struct ecore_ptt *p_ptt, + enum ecore_llh_port_filter_type_t type, + u32 high, u32 low, u32 *p_entry_num) +{ + int i; + + /* Find the entry and clean it */ + for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) { + if (!ecore_rd(p_hwfn, p_ptt, + NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 + + i * sizeof(u32))) + continue; + if (!ecore_rd(p_hwfn, p_ptt, + NIG_REG_LLH_FUNC_FILTER_MODE_BB_K2 + + i * sizeof(u32))) + continue; + if (!(ecore_rd(p_hwfn, p_ptt, + NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_BB_K2 + + i * sizeof(u32)) & (1 << type))) + continue; + if (ecore_rd(p_hwfn, p_ptt, + NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 + + 2 * i * sizeof(u32)) != low) + continue; + if (ecore_rd(p_hwfn, p_ptt, + NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 + + (2 * i + 1) * sizeof(u32)) != high) + continue; + + ecore_wr(p_hwfn, p_ptt, + NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 + i * sizeof(u32), 0); + ecore_wr(p_hwfn, p_ptt, + NIG_REG_LLH_FUNC_FILTER_MODE_BB_K2 + + i * sizeof(u32), 0); + ecore_wr(p_hwfn, p_ptt, + NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_BB_K2 + + i * sizeof(u32), 0); + ecore_wr(p_hwfn, p_ptt, + NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 + + 2 * i * sizeof(u32), 0); + ecore_wr(p_hwfn, p_ptt, + NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 + + (2 * i + 1) * sizeof(u32), 0); + break; + } + + if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) + return ECORE_INVAL; + + *p_entry_num = i; + return ECORE_SUCCESS; } @@ -4189,14 +4344,15 @@ ecore_llh_remove_protocol_filter(struct ecore_hwfn *p_hwfn, u16 dest_port, enum ecore_llh_port_filter_type_t type) { - u32 high, low; - int i; + u32 high, low, entry_num; + enum _ecore_status_t rc; if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn))) return; high = 0; low = 0; + switch (type) { case ECORE_LLH_FILTER_ETHERTYPE: high = source_port_or_eth_type; @@ -4219,49 +4375,24 @@ ecore_llh_remove_protocol_filter(struct ecore_hwfn *p_hwfn, return; } - for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) { - if (!ecore_rd(p_hwfn, p_ptt, - NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32))) - continue; - if (!ecore_rd(p_hwfn, p_ptt, - NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32))) - continue; - if (!(ecore_rd(p_hwfn, p_ptt, - NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE + - i * sizeof(u32)) & (1 << type))) - continue; - if (ecore_rd(p_hwfn, p_ptt, - NIG_REG_LLH_FUNC_FILTER_VALUE + - 2 * i * sizeof(u32)) != low) - continue; - if (ecore_rd(p_hwfn, p_ptt, - NIG_REG_LLH_FUNC_FILTER_VALUE + - (2 * i + 1) * sizeof(u32)) != high) - continue; - - ecore_wr(p_hwfn, p_ptt, - NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 0); - ecore_wr(p_hwfn, p_ptt, - NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 0); - ecore_wr(p_hwfn, p_ptt, - NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE + - i * sizeof(u32), 0); - ecore_wr(p_hwfn, p_ptt, - NIG_REG_LLH_FUNC_FILTER_VALUE + - 2 * i * sizeof(u32), 0); - ecore_wr(p_hwfn, p_ptt, - NIG_REG_LLH_FUNC_FILTER_VALUE + - (2 * i + 1) * sizeof(u32), 0); - break; + if (ECORE_IS_BB(p_hwfn->p_dev) || ECORE_IS_AH(p_hwfn->p_dev)) + rc = ecore_llh_remove_protocol_filter_bb_ah(p_hwfn, p_ptt, type, + high, low, + &entry_num); + if (rc != ECORE_SUCCESS) { + DP_NOTICE(p_hwfn, false, + "Tried to remove a non-configured filter [type %d, source_port_or_eth_type 0x%x, dest_port 0x%x]\n", + type, source_port_or_eth_type, dest_port); + return; } - if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) - DP_NOTICE(p_hwfn, false, - "Tried to remove a non-configured filter\n"); + DP_VERBOSE(p_hwfn, ECORE_MSG_HW, + "Protocol filter [type %d, source_port_or_eth_type 0x%x, dest_port 0x%x] was removed from %d\n", + type, source_port_or_eth_type, dest_port, entry_num); } -void ecore_llh_clear_all_filters(struct ecore_hwfn *p_hwfn, - struct ecore_ptt *p_ptt) +static void ecore_llh_clear_all_filters_bb_ah(struct ecore_hwfn *p_hwfn, + struct ecore_ptt *p_ptt) { int i; @@ -4270,16 +4401,27 @@ void ecore_llh_clear_all_filters(struct ecore_hwfn *p_hwfn, for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) { ecore_wr(p_hwfn, p_ptt, - NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 0); + NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 + + i * sizeof(u32), 0); ecore_wr(p_hwfn, p_ptt, - NIG_REG_LLH_FUNC_FILTER_VALUE + + NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 + 2 * i * sizeof(u32), 0); ecore_wr(p_hwfn, p_ptt, - NIG_REG_LLH_FUNC_FILTER_VALUE + + NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 + (2 * i + 1) * sizeof(u32), 0); } } +void ecore_llh_clear_all_filters(struct ecore_hwfn *p_hwfn, + struct ecore_ptt *p_ptt) +{ + if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn))) + return; + + if (ECORE_IS_BB(p_hwfn->p_dev) || ECORE_IS_AH(p_hwfn->p_dev)) + ecore_llh_clear_all_filters_bb_ah(p_hwfn, p_ptt); +} + enum _ecore_status_t ecore_llh_set_function_as_default(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt) @@ -4396,7 +4538,7 @@ enum _ecore_status_t ecore_set_rxq_coalesce(struct ecore_hwfn *p_hwfn, if (rc != ECORE_SUCCESS) goto out; - out: +out: return rc; } @@ -4434,7 +4576,7 @@ enum _ecore_status_t ecore_set_txq_coalesce(struct ecore_hwfn *p_hwfn, rc = ecore_set_coalesce(p_hwfn, p_ptt, address, ð_qzone, sizeof(struct xstorm_eth_queue_zone), timeset); - out: +out: return rc; } diff --git a/drivers/net/qede/base/ecore_dev_api.h b/drivers/net/qede/base/ecore_dev_api.h index e64a768d..9126cf95 100644 --- a/drivers/net/qede/base/ecore_dev_api.h +++ b/drivers/net/qede/base/ecore_dev_api.h @@ -186,6 +186,9 @@ struct ecore_hw_prepare_params { /* The OS Epoch time in seconds */ u32 epoch; + /* Allow the MFW to collect a crash dump */ + bool allow_mdump; + /* Allow prepare to pass even if some initializations are failing. * If set, the `p_prepare_res' field would be set with the return, * and might allow probe to pass even if there are certain issues. @@ -238,7 +241,7 @@ void ecore_ptt_release(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt); #ifndef __EXTRACT__LINUX__ -struct ecore_eth_stats { +struct ecore_eth_stats_common { u64 no_buff_discards; u64 packet_too_big_discard; u64 ttl0_discard; @@ -270,11 +273,6 @@ struct ecore_eth_stats { u64 rx_256_to_511_byte_packets; u64 rx_512_to_1023_byte_packets; u64 rx_1024_to_1518_byte_packets; - u64 rx_1519_to_1522_byte_packets; - u64 rx_1519_to_2047_byte_packets; - u64 rx_2048_to_4095_byte_packets; - u64 rx_4096_to_9216_byte_packets; - u64 rx_9217_to_16383_byte_packets; u64 rx_crc_errors; u64 rx_mac_crtl_frames; u64 rx_pause_frames; @@ -291,14 +289,8 @@ struct ecore_eth_stats { u64 tx_256_to_511_byte_packets; u64 tx_512_to_1023_byte_packets; u64 tx_1024_to_1518_byte_packets; - u64 tx_1519_to_2047_byte_packets; - u64 tx_2048_to_4095_byte_packets; - u64 tx_4096_to_9216_byte_packets; - u64 tx_9217_to_16383_byte_packets; u64 tx_pause_frames; u64 tx_pfc_frames; - u64 tx_lpi_entry_count; - u64 tx_total_collisions; u64 brb_truncates; u64 brb_discards; u64 rx_mac_bytes; @@ -312,6 +304,33 @@ struct ecore_eth_stats { u64 tx_mac_bc_packets; u64 tx_mac_ctrl_frames; }; + +struct ecore_eth_stats_bb { + u64 rx_1519_to_1522_byte_packets; + u64 rx_1519_to_2047_byte_packets; + u64 rx_2048_to_4095_byte_packets; + u64 rx_4096_to_9216_byte_packets; + u64 rx_9217_to_16383_byte_packets; + u64 tx_1519_to_2047_byte_packets; + u64 tx_2048_to_4095_byte_packets; + u64 tx_4096_to_9216_byte_packets; + u64 tx_9217_to_16383_byte_packets; + u64 tx_lpi_entry_count; + u64 tx_total_collisions; +}; + +struct ecore_eth_stats_ah { + u64 rx_1519_to_max_byte_packets; + u64 tx_1519_to_max_byte_packets; +}; + +struct ecore_eth_stats { + struct ecore_eth_stats_common common; + union { + struct ecore_eth_stats_bb bb; + struct ecore_eth_stats_ah ah; + }; +}; #endif enum ecore_dmae_address_type_t { @@ -581,4 +600,16 @@ enum _ecore_status_t ecore_set_queue_coalesce(struct ecore_hwfn *p_hwfn, u16 rx_coal, u16 tx_coal, void *p_handle); +/** + * @brief ecore_pglueb_set_pfid_enable - Enable or disable PCI BUS MASTER + * + * @param p_hwfn + * @param p_ptt + * @param b_enable - true/false + * + * @return enum _ecore_status_t + */ +enum _ecore_status_t ecore_pglueb_set_pfid_enable(struct ecore_hwfn *p_hwfn, + struct ecore_ptt *p_ptt, + bool b_enable); #endif diff --git a/drivers/net/qede/base/ecore_hsi_common.h b/drivers/net/qede/base/ecore_hsi_common.h index 3042ed55..5c2a08f9 100644 --- a/drivers/net/qede/base/ecore_hsi_common.h +++ b/drivers/net/qede/base/ecore_hsi_common.h @@ -856,7 +856,8 @@ struct core_rx_gsi_offload_cqe { __le16 vlan /* 802.1q VLAN tag */; __le32 src_mac_addrhi /* hi 4 bytes source mac address */; __le16 src_mac_addrlo /* lo 2 bytes of source mac address */; - u8 reserved1[2]; +/* These are the lower 16 bit of QP id in RoCE BTH header */ + __le16 qp_id; __le32 gid_dst[4] /* Gid destination address */; }; @@ -998,11 +999,9 @@ struct core_tx_bd { */ #define CORE_TX_BD_L4_HDR_OFFSET_W_MASK 0x3FFF #define CORE_TX_BD_L4_HDR_OFFSET_W_SHIFT 0 -/* Packet destination - Network, LB (use enum core_tx_dest) */ -#define CORE_TX_BD_TX_DST_MASK 0x1 +/* Packet destination - Network, Loopback or Drop (use enum core_tx_dest) */ +#define CORE_TX_BD_TX_DST_MASK 0x3 #define CORE_TX_BD_TX_DST_SHIFT 14 -#define CORE_TX_BD_RESERVED_MASK 0x1 -#define CORE_TX_BD_RESERVED_SHIFT 15 }; @@ -1011,8 +1010,10 @@ struct core_tx_bd { * Light L2 TX Destination */ enum core_tx_dest { - CORE_TX_DEST_NW /* Light L2 TX Destination to the Network */, - CORE_TX_DEST_LB /* Light L2 TX Destination to the Loopback */, + CORE_TX_DEST_NW /* TX Destination to the Network */, + CORE_TX_DEST_LB /* TX Destination to the Loopback */, + CORE_TX_DEST_RESERVED, + CORE_TX_DEST_DROP /* TX Drop */, MAX_CORE_TX_DEST }; @@ -1337,20 +1338,14 @@ struct pf_start_tunnel_config { * FW will use a default port */ u8 set_geneve_udp_port_flg; - u8 tx_enable_vxlan /* If set, enable VXLAN tunnel in TX path. */; -/* If set, enable l2 GENEVE tunnel in TX path. */ - u8 tx_enable_l2geneve; -/* If set, enable IP GENEVE tunnel in TX path. */ - u8 tx_enable_ipgeneve; - u8 tx_enable_l2gre /* If set, enable l2 GRE tunnel in TX path. */; - u8 tx_enable_ipgre /* If set, enable IP GRE tunnel in TX path. */; - u8 tunnel_clss_vxlan /* Classification scheme for VXLAN tunnel. */; -/* Classification scheme for l2 GENEVE tunnel. */ + u8 tunnel_clss_vxlan /* Rx classification scheme for VXLAN tunnel. */; +/* Rx classification scheme for l2 GENEVE tunnel. */ u8 tunnel_clss_l2geneve; -/* Classification scheme for ip GENEVE tunnel. */ +/* Rx classification scheme for ip GENEVE tunnel. */ u8 tunnel_clss_ipgeneve; - u8 tunnel_clss_l2gre /* Classification scheme for l2 GRE tunnel. */; - u8 tunnel_clss_ipgre /* Classification scheme for ip GRE tunnel. */; + u8 tunnel_clss_l2gre /* Rx classification scheme for l2 GRE tunnel. */; + u8 tunnel_clss_ipgre /* Rx classification scheme for ip GRE tunnel. */; + u8 reserved; /* VXLAN tunnel UDP destination port. Valid if set_vxlan_udp_port_flg=1 */ __le16 vxlan_udp_port; /* GENEVE tunnel UDP destination port. Valid if set_geneve_udp_port_flg=1 */ @@ -1366,6 +1361,7 @@ struct pf_start_ramrod_data { struct regpair consolid_q_pbl_addr; /* tunnel configuration. */ struct pf_start_tunnel_config tunnel_config; + __le32 reserved; __le16 event_ring_sb_id /* Status block ID */; /* All VfIds owned by Pf will be from baseVfId till baseVfId+numVfs */ u8 base_vf_id; @@ -1425,19 +1421,10 @@ struct pf_update_tunnel_config { * unicast outer MAC in NPAR mode. */ u8 update_rx_def_non_ucast_clss; -/* Update TX per PF tunnel classification scheme. used by pf update. */ - u8 update_tx_pf_clss; /* Update VXLAN tunnel UDP destination port. */ u8 set_vxlan_udp_port_flg; /* Update GENEVE tunnel UDP destination port. */ u8 set_geneve_udp_port_flg; - u8 tx_enable_vxlan /* If set, enable VXLAN tunnel in TX path. */; -/* If set, enable l2 GENEVE tunnel in TX path. */ - u8 tx_enable_l2geneve; -/* If set, enable IP GENEVE tunnel in TX path. */ - u8 tx_enable_ipgeneve; - u8 tx_enable_l2gre /* If set, enable l2 GRE tunnel in TX path. */; - u8 tx_enable_ipgre /* If set, enable IP GRE tunnel in TX path. */; u8 tunnel_clss_vxlan /* Classification scheme for VXLAN tunnel. */; /* Classification scheme for l2 GENEVE tunnel. */ u8 tunnel_clss_l2geneve; @@ -1447,7 +1434,7 @@ struct pf_update_tunnel_config { u8 tunnel_clss_ipgre /* Classification scheme for ip GRE tunnel. */; __le16 vxlan_udp_port /* VXLAN tunnel UDP destination port. */; __le16 geneve_udp_port /* GENEVE tunnel UDP destination port. */; - __le16 reserved[2]; + __le16 reserved; }; /* diff --git a/drivers/net/qede/base/ecore_hsi_debug_tools.h b/drivers/net/qede/base/ecore_hsi_debug_tools.h index 917e8f4c..7443ff9d 100644 --- a/drivers/net/qede/base/ecore_hsi_debug_tools.h +++ b/drivers/net/qede/base/ecore_hsi_debug_tools.h @@ -67,6 +67,8 @@ enum block_addr { GRCBASE_MULD = 0x4e0000, GRCBASE_YULD = 0x4c8000, GRCBASE_XYLD = 0x4c0000, + GRCBASE_PTLD = 0x590000, + GRCBASE_YPLD = 0x5b0000, GRCBASE_PRM = 0x230000, GRCBASE_PBF_PB1 = 0xda0000, GRCBASE_PBF_PB2 = 0xda4000, @@ -80,6 +82,10 @@ enum block_addr { GRCBASE_TCFC = 0x2d0000, GRCBASE_IGU = 0x180000, GRCBASE_CAU = 0x1c0000, + GRCBASE_RGFS = 0xf00000, + GRCBASE_RGSRC = 0x320000, + GRCBASE_TGFS = 0xd00000, + GRCBASE_TGSRC = 0x322000, GRCBASE_UMAC = 0x51000, GRCBASE_XMAC = 0x210000, GRCBASE_DBG = 0x10000, @@ -93,12 +99,6 @@ enum block_addr { GRCBASE_PHY_PCIE = 0x620000, GRCBASE_LED = 0x6b8000, GRCBASE_AVS_WRAP = 0x6b0000, - GRCBASE_RGFS = 0x1fa0000, - GRCBASE_RGSRC = 0x1fa8000, - GRCBASE_TGFS = 0x1fb0000, - GRCBASE_TGSRC = 0x1fb8000, - GRCBASE_PTLD = 0x1fc0000, - GRCBASE_YPLD = 0x1fe0000, GRCBASE_MISC_AEU = 0x8000, GRCBASE_BAR0_MAP = 0x1c00000, MAX_BLOCK_ADDR @@ -159,6 +159,8 @@ enum block_id { BLOCK_MULD, BLOCK_YULD, BLOCK_XYLD, + BLOCK_PTLD, + BLOCK_YPLD, BLOCK_PRM, BLOCK_PBF_PB1, BLOCK_PBF_PB2, @@ -172,6 +174,10 @@ enum block_id { BLOCK_TCFC, BLOCK_IGU, BLOCK_CAU, + BLOCK_RGFS, + BLOCK_RGSRC, + BLOCK_TGFS, + BLOCK_TGSRC, BLOCK_UMAC, BLOCK_XMAC, BLOCK_DBG, @@ -185,12 +191,6 @@ enum block_id { BLOCK_PHY_PCIE, BLOCK_LED, BLOCK_AVS_WRAP, - BLOCK_RGFS, - BLOCK_RGSRC, - BLOCK_TGFS, - BLOCK_TGSRC, - BLOCK_PTLD, - BLOCK_YPLD, BLOCK_MISC_AEU, BLOCK_BAR0_MAP, MAX_BLOCK_ID diff --git a/drivers/net/qede/base/ecore_hsi_init_func.h b/drivers/net/qede/base/ecore_hsi_init_func.h index fca74791..48b0048f 100644 --- a/drivers/net/qede/base/ecore_hsi_init_func.h +++ b/drivers/net/qede/base/ecore_hsi_init_func.h @@ -15,6 +15,10 @@ /* Number of VLAN priorities */ #define NUM_OF_VLAN_PRIORITIES 8 +/* Size of CRC8 lookup table */ +#ifndef LINUX_REMOVE +#define CRC8_TABLE_SIZE 256 +#endif /* * BRB RAM init requirements diff --git a/drivers/net/qede/base/ecore_init_fw_funcs.c b/drivers/net/qede/base/ecore_init_fw_funcs.c index 004ab351..b5ef173e 100644 --- a/drivers/net/qede/base/ecore_init_fw_funcs.c +++ b/drivers/net/qede/base/ecore_init_fw_funcs.c @@ -1590,7 +1590,8 @@ void ecore_set_rfs_mode_enable(struct ecore_hwfn *p_hwfn, /* Filters are per PF!! */ SET_FIELD(camLine.cam_line_mapped.camline, - GFT_CAM_LINE_MAPPED_PF_ID_MASK, 1); + GFT_CAM_LINE_MAPPED_PF_ID_MASK, + GFT_CAM_LINE_MAPPED_PF_ID_MASK_MASK); SET_FIELD(camLine.cam_line_mapped.camline, GFT_CAM_LINE_MAPPED_PF_ID, pf_id); @@ -1644,8 +1645,9 @@ void ecore_set_rfs_mode_enable(struct ecore_hwfn *p_hwfn, i * REG_SIZE, *(ramLinePointer + i)); /* Set default profile so that no filter match will happen */ - ramLine.lo = 0xffff; - ramLine.hi = 0xffff; + ramLine.lo = 0xffffffff; + ramLine.hi = 0x3ff; + for (i = 0; i < RAM_LINE_SIZE / REG_SIZE; i++) ecore_wr(p_hwfn, p_ptt, PRS_REG_GFT_PROFILE_MASK_RAM + RAM_LINE_SIZE * PRS_GFT_CAM_LINES_NO_MATCH + @@ -1722,40 +1724,30 @@ u32 ecore_get_mstorm_eth_vf_prods_offset(struct ecore_hwfn *p_hwfn, return offset; } -/* Calculate CRC8 of first 4 bytes in buf */ -static u8 ecore_calc_crc8(const u8 *buf) -{ - u32 i, j, crc = 0xff << 8; - - /* CRC-8 polynomial */ - #define POLY 0x1070 - - for (j = 0; j < 4; j++, buf++) { - crc ^= (*buf << 8); - for (i = 0; i < 8; i++) { - if (crc & 0x8000) - crc ^= (POLY << 3); - - crc <<= 1; - } - } - - return (u8)(crc >> 8); -} +#ifndef LINUX_REMOVE +#define CRC8_INIT_VALUE 0xFF +#define CRC8_TABLE_SIZE 256 +#endif +static u8 cdu_crc8_table[CRC8_TABLE_SIZE]; -/* Calculate and return CDU validation byte per conneciton type / region / +/* Calculate and return CDU validation byte per connection type / region / * cid */ -static u8 ecore_calc_cdu_validation_byte(u8 conn_type, u8 region, - u32 cid) +static u8 ecore_calc_cdu_validation_byte(struct ecore_hwfn *p_hwfn, + u8 conn_type, + u8 region, u32 cid) { const u8 validation_cfg = CDU_VALIDATION_DEFAULT_CFG; + + static u8 crc8_table_valid; /*automatically initialized to 0*/ u8 crc, validation_byte = 0; u32 validation_string = 0; - const u8 *data_to_crc_rev; - u8 data_to_crc[4]; + u32 data_to_crc; - data_to_crc_rev = (const u8 *)&validation_string; + if (crc8_table_valid == 0) { + OSAL_CRC8_POPULATE(cdu_crc8_table, 0x07); + crc8_table_valid = 1; + } /* * The CRC is calculated on the String-to-compress: @@ -1772,13 +1764,22 @@ static u8 ecore_calc_cdu_validation_byte(u8 conn_type, u8 region, if ((validation_cfg >> CDU_CONTEXT_VALIDATION_CFG_USE_TYPE) & 1) validation_string |= (conn_type & 0xF); - /* Convert to big-endian (ntoh())*/ - data_to_crc[0] = data_to_crc_rev[3]; - data_to_crc[1] = data_to_crc_rev[2]; - data_to_crc[2] = data_to_crc_rev[1]; - data_to_crc[3] = data_to_crc_rev[0]; - - crc = ecore_calc_crc8(data_to_crc); + /* Convert to big-endian and calculate CRC8*/ + data_to_crc = OSAL_BE32_TO_CPU(validation_string); + + crc = OSAL_CRC8(cdu_crc8_table, (u8 *)&data_to_crc, sizeof(data_to_crc), + CRC8_INIT_VALUE); + + /* The validation byte [7:0] is composed: + * for type A validation + * [7] = active configuration bit + * [6:0] = crc[6:0] + * + * for type B validation + * [7] = active configuration bit + * [6:3] = connection_type[3:0] + * [2:0] = crc[2:0] + */ validation_byte |= ((validation_cfg >> CDU_CONTEXT_VALIDATION_CFG_USE_ACTIVE) & 1) << 7; @@ -1793,8 +1794,9 @@ static u8 ecore_calc_cdu_validation_byte(u8 conn_type, u8 region, } /* Calcualte and set validation bytes for session context */ -void ecore_calc_session_ctx_validation(void *p_ctx_mem, u16 ctx_size, - u8 ctx_type, u32 cid) +void ecore_calc_session_ctx_validation(struct ecore_hwfn *p_hwfn, + void *p_ctx_mem, + u16 ctx_size, u8 ctx_type, u32 cid) { u8 *x_val_ptr, *t_val_ptr, *u_val_ptr, *p_ctx; @@ -1805,14 +1807,14 @@ void ecore_calc_session_ctx_validation(void *p_ctx_mem, u16 ctx_size, OSAL_MEMSET(p_ctx, 0, ctx_size); - *x_val_ptr = ecore_calc_cdu_validation_byte(ctx_type, 3, cid); - *t_val_ptr = ecore_calc_cdu_validation_byte(ctx_type, 4, cid); - *u_val_ptr = ecore_calc_cdu_validation_byte(ctx_type, 5, cid); + *x_val_ptr = ecore_calc_cdu_validation_byte(p_hwfn, ctx_type, 3, cid); + *t_val_ptr = ecore_calc_cdu_validation_byte(p_hwfn, ctx_type, 4, cid); + *u_val_ptr = ecore_calc_cdu_validation_byte(p_hwfn, ctx_type, 5, cid); } /* Calcualte and set validation bytes for task context */ -void ecore_calc_task_ctx_validation(void *p_ctx_mem, u16 ctx_size, - u8 ctx_type, u32 tid) +void ecore_calc_task_ctx_validation(struct ecore_hwfn *p_hwfn, void *p_ctx_mem, + u16 ctx_size, u8 ctx_type, u32 tid) { u8 *p_ctx, *region1_val_ptr; @@ -1821,7 +1823,8 @@ void ecore_calc_task_ctx_validation(void *p_ctx_mem, u16 ctx_size, OSAL_MEMSET(p_ctx, 0, ctx_size); - *region1_val_ptr = ecore_calc_cdu_validation_byte(ctx_type, 1, tid); + *region1_val_ptr = ecore_calc_cdu_validation_byte(p_hwfn, ctx_type, + 1, tid); } /* Memset session context to 0 while preserving validation bytes */ @@ -1847,8 +1850,7 @@ void ecore_memset_session_ctx(void *p_ctx_mem, u32 ctx_size, u8 ctx_type) } /* Memset task context to 0 while preserving validation bytes */ -void ecore_memset_task_ctx(void *p_ctx_mem, const u32 ctx_size, - const u8 ctx_type) +void ecore_memset_task_ctx(void *p_ctx_mem, u32 ctx_size, u8 ctx_type) { u8 *p_ctx, *region1_val_ptr; u8 region1_val; diff --git a/drivers/net/qede/base/ecore_init_fw_funcs.h b/drivers/net/qede/base/ecore_init_fw_funcs.h index 4da3fc29..488dc005 100644 --- a/drivers/net/qede/base/ecore_init_fw_funcs.h +++ b/drivers/net/qede/base/ecore_init_fw_funcs.h @@ -424,48 +424,54 @@ void ecore_enable_context_validation(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt); /** * @brief ecore_calc_session_ctx_validation - Calcualte validation byte for - * session context. + * session context. * - * - * @param p_ctx_mem - pointer to context memory. - * @param ctx_size - context size. - * @param ctx_type - context type. - * @param cid - context cid. + * @param p_ctx_mem - pointer to context memory. + * @param ctx_size - context size. + * @param ctx_type - context type. + * @param cid - context cid. */ -void ecore_calc_session_ctx_validation(void *p_ctx_mem, u16 ctx_size, - u8 ctx_type, u32 cid); +void ecore_calc_session_ctx_validation(struct ecore_hwfn *p_hwfn, + void *p_ctx_mem, + u16 ctx_size, + u8 ctx_type, + u32 cid); /** * @brief ecore_calc_task_ctx_validation - Calcualte validation byte for task - * context. - * + * context. * - * @param p_ctx_mem - pointer to context memory. - * @param ctx_size - context size. - * @param ctx_type - context type. - * @param tid - context tid. + * @param p_hwfn - HW device data + * @param p_ctx_mem - pointer to context memory. + * @param ctx_size - context size. + * @param ctx_type - context type. + * @param tid - context tid. */ -void ecore_calc_task_ctx_validation(void *p_ctx_mem, u16 ctx_size, - u8 ctx_type, u32 tid); +void ecore_calc_task_ctx_validation(struct ecore_hwfn *p_hwfn, + void *p_ctx_mem, + u16 ctx_size, + u8 ctx_type, + u32 tid); /** * @brief ecore_memset_session_ctx - Memset session context to 0 while - * preserving validation bytes. + * preserving validation bytes. * - * - * @param p_ctx_mem - pointer to context memory. - * @param ctx_size - size to initialzie. - * @param ctx_type - context type. + * @param p_hwfn - HW device data + * @param p_ctx_mem - pointer to context memory. + * @param ctx_size - size to initialzie. + * @param ctx_type - context type. */ -void ecore_memset_session_ctx(void *p_ctx_mem, u32 ctx_size, +void ecore_memset_session_ctx(void *p_ctx_mem, + u32 ctx_size, u8 ctx_type); /** - * @brief ecore_memset_task_ctx - Memset session context to 0 while preserving - * validation bytes. - * + * @brief ecore_memset_task_ctx - Memset task context to 0 while preserving + * validation bytes. * - * @param p_ctx_mem - pointer to context memory. - * @param ctx_size - size to initialzie. - * @param ctx_type - context type. + * @param p_ctx_mem - pointer to context memory. + * @param ctx_size - size to initialzie. + * @param ctx_type - context type. */ -void ecore_memset_task_ctx(void *p_ctx_mem, u32 ctx_size, +void ecore_memset_task_ctx(void *p_ctx_mem, + u32 ctx_size, u8 ctx_type); #endif diff --git a/drivers/net/qede/base/ecore_int.c b/drivers/net/qede/base/ecore_int.c index 8dc4d150..b57c510c 100644 --- a/drivers/net/qede/base/ecore_int.c +++ b/drivers/net/qede/base/ecore_int.c @@ -284,122 +284,119 @@ out: #define ECORE_PGLUE_ATTENTION_ICPL_VALID (1 << 23) #define ECORE_PGLUE_ATTENTION_ZLR_VALID (1 << 25) #define ECORE_PGLUE_ATTENTION_ILT_VALID (1 << 23) -static enum _ecore_status_t ecore_pglub_rbc_attn_cb(struct ecore_hwfn *p_hwfn) + +enum _ecore_status_t ecore_pglueb_rbc_attn_handler(struct ecore_hwfn *p_hwfn, + struct ecore_ptt *p_ptt) { u32 tmp; - tmp = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt, - PGLUE_B_REG_TX_ERR_WR_DETAILS2); + tmp = ecore_rd(p_hwfn, p_ptt, PGLUE_B_REG_TX_ERR_WR_DETAILS2); if (tmp & ECORE_PGLUE_ATTENTION_VALID) { u32 addr_lo, addr_hi, details; - addr_lo = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt, + addr_lo = ecore_rd(p_hwfn, p_ptt, PGLUE_B_REG_TX_ERR_WR_ADD_31_0); - addr_hi = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt, + addr_hi = ecore_rd(p_hwfn, p_ptt, PGLUE_B_REG_TX_ERR_WR_ADD_63_32); - details = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt, + details = ecore_rd(p_hwfn, p_ptt, PGLUE_B_REG_TX_ERR_WR_DETAILS); - DP_INFO(p_hwfn, - "Illegal write by chip to [%08x:%08x] blocked." - "Details: %08x [PFID %02x, VFID %02x, VF_VALID %02x]" - " Details2 %08x [Was_error %02x BME deassert %02x" - " FID_enable deassert %02x]\n", - addr_hi, addr_lo, details, - (u8)((details & - ECORE_PGLUE_ATTENTION_DETAILS_PFID_MASK) >> - ECORE_PGLUE_ATTENTION_DETAILS_PFID_SHIFT), - (u8)((details & - ECORE_PGLUE_ATTENTION_DETAILS_VFID_MASK) >> - ECORE_PGLUE_ATTENTION_DETAILS_VFID_SHIFT), - (u8)((details & ECORE_PGLUE_ATTENTION_DETAILS_VF_VALID) - ? 1 : 0), tmp, - (u8)((tmp & ECORE_PGLUE_ATTENTION_DETAILS2_WAS_ERR) ? 1 - : 0), - (u8)((tmp & ECORE_PGLUE_ATTENTION_DETAILS2_BME) ? 1 : - 0), - (u8)((tmp & ECORE_PGLUE_ATTENTION_DETAILS2_FID_EN) ? 1 - : 0)); + DP_NOTICE(p_hwfn, false, + "Illegal write by chip to [%08x:%08x] blocked. Details: %08x [PFID %02x, VFID %02x, VF_VALID %02x] Details2 %08x [Was_error %02x BME deassert %02x FID_enable deassert %02x]\n", + addr_hi, addr_lo, details, + (u8)((details & + ECORE_PGLUE_ATTENTION_DETAILS_PFID_MASK) >> + ECORE_PGLUE_ATTENTION_DETAILS_PFID_SHIFT), + (u8)((details & + ECORE_PGLUE_ATTENTION_DETAILS_VFID_MASK) >> + ECORE_PGLUE_ATTENTION_DETAILS_VFID_SHIFT), + (u8)((details & + ECORE_PGLUE_ATTENTION_DETAILS_VF_VALID) ? 1 : 0), + tmp, + (u8)((tmp & ECORE_PGLUE_ATTENTION_DETAILS2_WAS_ERR) ? + 1 : 0), + (u8)((tmp & ECORE_PGLUE_ATTENTION_DETAILS2_BME) ? + 1 : 0), + (u8)((tmp & ECORE_PGLUE_ATTENTION_DETAILS2_FID_EN) ? + 1 : 0)); } - tmp = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt, - PGLUE_B_REG_TX_ERR_RD_DETAILS2); + tmp = ecore_rd(p_hwfn, p_ptt, PGLUE_B_REG_TX_ERR_RD_DETAILS2); if (tmp & ECORE_PGLUE_ATTENTION_RD_VALID) { u32 addr_lo, addr_hi, details; - addr_lo = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt, + addr_lo = ecore_rd(p_hwfn, p_ptt, PGLUE_B_REG_TX_ERR_RD_ADD_31_0); - addr_hi = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt, + addr_hi = ecore_rd(p_hwfn, p_ptt, PGLUE_B_REG_TX_ERR_RD_ADD_63_32); - details = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt, + details = ecore_rd(p_hwfn, p_ptt, PGLUE_B_REG_TX_ERR_RD_DETAILS); - DP_INFO(p_hwfn, - "Illegal read by chip from [%08x:%08x] blocked." - " Details: %08x [PFID %02x, VFID %02x, VF_VALID %02x]" - " Details2 %08x [Was_error %02x BME deassert %02x" - " FID_enable deassert %02x]\n", - addr_hi, addr_lo, details, - (u8)((details & - ECORE_PGLUE_ATTENTION_DETAILS_PFID_MASK) >> - ECORE_PGLUE_ATTENTION_DETAILS_PFID_SHIFT), - (u8)((details & - ECORE_PGLUE_ATTENTION_DETAILS_VFID_MASK) >> - ECORE_PGLUE_ATTENTION_DETAILS_VFID_SHIFT), - (u8)((details & ECORE_PGLUE_ATTENTION_DETAILS_VF_VALID) - ? 1 : 0), tmp, - (u8)((tmp & ECORE_PGLUE_ATTENTION_DETAILS2_WAS_ERR) ? 1 - : 0), - (u8)((tmp & ECORE_PGLUE_ATTENTION_DETAILS2_BME) ? 1 : - 0), - (u8)((tmp & ECORE_PGLUE_ATTENTION_DETAILS2_FID_EN) ? 1 - : 0)); + DP_NOTICE(p_hwfn, false, + "Illegal read by chip from [%08x:%08x] blocked. Details: %08x [PFID %02x, VFID %02x, VF_VALID %02x] Details2 %08x [Was_error %02x BME deassert %02x FID_enable deassert %02x]\n", + addr_hi, addr_lo, details, + (u8)((details & + ECORE_PGLUE_ATTENTION_DETAILS_PFID_MASK) >> + ECORE_PGLUE_ATTENTION_DETAILS_PFID_SHIFT), + (u8)((details & + ECORE_PGLUE_ATTENTION_DETAILS_VFID_MASK) >> + ECORE_PGLUE_ATTENTION_DETAILS_VFID_SHIFT), + (u8)((details & + ECORE_PGLUE_ATTENTION_DETAILS_VF_VALID) ? 1 : 0), + tmp, + (u8)((tmp & ECORE_PGLUE_ATTENTION_DETAILS2_WAS_ERR) ? + 1 : 0), + (u8)((tmp & ECORE_PGLUE_ATTENTION_DETAILS2_BME) ? + 1 : 0), + (u8)((tmp & ECORE_PGLUE_ATTENTION_DETAILS2_FID_EN) ? + 1 : 0)); } - tmp = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt, - PGLUE_B_REG_TX_ERR_WR_DETAILS_ICPL); + tmp = ecore_rd(p_hwfn, p_ptt, PGLUE_B_REG_TX_ERR_WR_DETAILS_ICPL); if (tmp & ECORE_PGLUE_ATTENTION_ICPL_VALID) - DP_INFO(p_hwfn, "ICPL error - %08x\n", tmp); + DP_NOTICE(p_hwfn, false, "ICPL erorr - %08x\n", tmp); - tmp = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt, - PGLUE_B_REG_MASTER_ZLR_ERR_DETAILS); + tmp = ecore_rd(p_hwfn, p_ptt, PGLUE_B_REG_MASTER_ZLR_ERR_DETAILS); if (tmp & ECORE_PGLUE_ATTENTION_ZLR_VALID) { u32 addr_hi, addr_lo; - addr_lo = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt, + addr_lo = ecore_rd(p_hwfn, p_ptt, PGLUE_B_REG_MASTER_ZLR_ERR_ADD_31_0); - addr_hi = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt, + addr_hi = ecore_rd(p_hwfn, p_ptt, PGLUE_B_REG_MASTER_ZLR_ERR_ADD_63_32); - DP_INFO(p_hwfn, "ICPL error - %08x [Address %08x:%08x]\n", - tmp, addr_hi, addr_lo); + DP_NOTICE(p_hwfn, false, + "ICPL erorr - %08x [Address %08x:%08x]\n", + tmp, addr_hi, addr_lo); } - tmp = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt, - PGLUE_B_REG_VF_ILT_ERR_DETAILS2); + tmp = ecore_rd(p_hwfn, p_ptt, PGLUE_B_REG_VF_ILT_ERR_DETAILS2); if (tmp & ECORE_PGLUE_ATTENTION_ILT_VALID) { u32 addr_hi, addr_lo, details; - addr_lo = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt, + addr_lo = ecore_rd(p_hwfn, p_ptt, PGLUE_B_REG_VF_ILT_ERR_ADD_31_0); - addr_hi = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt, + addr_hi = ecore_rd(p_hwfn, p_ptt, PGLUE_B_REG_VF_ILT_ERR_ADD_63_32); - details = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt, + details = ecore_rd(p_hwfn, p_ptt, PGLUE_B_REG_VF_ILT_ERR_DETAILS); - DP_INFO(p_hwfn, - "ILT error - Details %08x Details2 %08x" - " [Address %08x:%08x]\n", - details, tmp, addr_hi, addr_lo); + DP_NOTICE(p_hwfn, false, + "ILT error - Details %08x Details2 %08x [Address %08x:%08x]\n", + details, tmp, addr_hi, addr_lo); } /* Clear the indications */ - ecore_wr(p_hwfn, p_hwfn->p_dpc_ptt, - PGLUE_B_REG_LATCHED_ERRORS_CLR, (1 << 2)); + ecore_wr(p_hwfn, p_ptt, PGLUE_B_REG_LATCHED_ERRORS_CLR, (1 << 2)); return ECORE_SUCCESS; } +static enum _ecore_status_t ecore_pglueb_rbc_attn_cb(struct ecore_hwfn *p_hwfn) +{ + return ecore_pglueb_rbc_attn_handler(p_hwfn, p_hwfn->p_dpc_ptt); +} + static enum _ecore_status_t ecore_fw_assertion(struct ecore_hwfn *p_hwfn) { DP_NOTICE(p_hwfn, false, "FW assertion!\n"); @@ -505,7 +502,7 @@ static struct aeu_invert_reg aeu_descs[NUM_ATTN_REGS] = { { /* After Invert 2 */ {"PGLUE config_space", ATTENTION_SINGLE, OSAL_NULL, MAX_BLOCK_ID}, {"PGLUE misc_flr", ATTENTION_SINGLE, OSAL_NULL, MAX_BLOCK_ID}, - {"PGLUE B RBC", ATTENTION_PAR_INT, ecore_pglub_rbc_attn_cb, + {"PGLUE B RBC", ATTENTION_PAR_INT, ecore_pglueb_rbc_attn_cb, BLOCK_PGLUE_B}, {"PGLUE misc_mctp", ATTENTION_SINGLE, OSAL_NULL, MAX_BLOCK_ID}, {"Flash event", ATTENTION_SINGLE, OSAL_NULL, MAX_BLOCK_ID}, @@ -827,8 +824,9 @@ ecore_int_deassertion_aeu_bit(struct ecore_hwfn *p_hwfn, ATTN_TYPE_INTERRUPT, !b_fatal); } + /* @DPDK */ /* Reach assertion if attention is fatal */ - if (b_fatal) { + if (b_fatal || (strcmp(p_bit_name, "PGLUE B RBC") == 0)) { DP_NOTICE(p_hwfn, true, "`%s': Fatal attention\n", p_bit_name); @@ -842,7 +840,7 @@ ecore_int_deassertion_aeu_bit(struct ecore_hwfn *p_hwfn, u32 mask = ~bitmask; val = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en_reg); ecore_wr(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en_reg, (val & mask)); - DP_INFO(p_hwfn, "`%s' - Disabled future attentions\n", + DP_ERR(p_hwfn, "`%s' - Disabled future attentions\n", p_bit_name); } diff --git a/drivers/net/qede/base/ecore_int.h b/drivers/net/qede/base/ecore_int.h index 0c8929e3..067ed605 100644 --- a/drivers/net/qede/base/ecore_int.h +++ b/drivers/net/qede/base/ecore_int.h @@ -208,4 +208,7 @@ enum _ecore_status_t ecore_int_set_timer_res(struct ecore_hwfn *p_hwfn, #define ECORE_MAPPING_MEMORY_SIZE(dev) NUM_OF_SBS(dev) #endif +enum _ecore_status_t ecore_pglueb_rbc_attn_handler(struct ecore_hwfn *p_hwfn, + struct ecore_ptt *p_ptt); + #endif /* __ECORE_INT_H__ */ diff --git a/drivers/net/qede/base/ecore_iro_values.h b/drivers/net/qede/base/ecore_iro_values.h index 6764bfa6..bc8df8f8 100644 --- a/drivers/net/qede/base/ecore_iro_values.h +++ b/drivers/net/qede/base/ecore_iro_values.h @@ -27,7 +27,7 @@ static const struct iro iro_arr[49] = { /* USTORM_COMMON_QUEUE_CONS_OFFSET(queue_zone_id) */ { 0x84, 0x8, 0x0, 0x0, 0x2}, /* XSTORM_INTEG_TEST_DATA_OFFSET */ - { 0x4bc0, 0x0, 0x0, 0x0, 0x78}, + { 0x4c40, 0x0, 0x0, 0x0, 0x78}, /* YSTORM_INTEG_TEST_DATA_OFFSET */ { 0x3df0, 0x0, 0x0, 0x0, 0x78}, /* PSTORM_INTEG_TEST_DATA_OFFSET */ @@ -37,13 +37,13 @@ static const struct iro iro_arr[49] = { /* MSTORM_INTEG_TEST_DATA_OFFSET */ { 0x4990, 0x0, 0x0, 0x0, 0x78}, /* USTORM_INTEG_TEST_DATA_OFFSET */ - { 0x7e48, 0x0, 0x0, 0x0, 0x78}, + { 0x7f48, 0x0, 0x0, 0x0, 0x78}, /* TSTORM_LL2_RX_PRODS_OFFSET(core_rx_queue_id) */ { 0xa28, 0x8, 0x0, 0x0, 0x8}, /* CORE_LL2_TSTORM_PER_QUEUE_STAT_OFFSET(core_rx_queue_id) */ { 0x61f8, 0x10, 0x0, 0x0, 0x10}, /* CORE_LL2_USTORM_PER_QUEUE_STAT_OFFSET(core_rx_queue_id) */ - { 0xb820, 0x30, 0x0, 0x0, 0x30}, + { 0xbd20, 0x30, 0x0, 0x0, 0x30}, /* CORE_LL2_PSTORM_PER_QUEUE_STAT_OFFSET(core_tx_stats_id) */ { 0x95b8, 0x30, 0x0, 0x0, 0x30}, /* MSTORM_QUEUE_STAT_OFFSET(stat_counter_id) */ @@ -57,9 +57,9 @@ static const struct iro iro_arr[49] = { /* MSTORM_ETH_PF_STAT_OFFSET(pf_id) */ { 0x4ba0, 0x80, 0x0, 0x0, 0x20}, /* USTORM_QUEUE_STAT_OFFSET(stat_counter_id) */ - { 0x8050, 0x40, 0x0, 0x0, 0x30}, + { 0x8150, 0x40, 0x0, 0x0, 0x30}, /* USTORM_ETH_PF_STAT_OFFSET(pf_id) */ - { 0xe770, 0x60, 0x0, 0x0, 0x60}, + { 0xec70, 0x60, 0x0, 0x0, 0x60}, /* PSTORM_QUEUE_STAT_OFFSET(stat_counter_id) */ { 0x2b48, 0x80, 0x0, 0x0, 0x38}, /* PSTORM_ETH_PF_STAT_OFFSET(pf_id) */ @@ -89,7 +89,7 @@ static const struct iro iro_arr[49] = { /* MSTORM_ISCSI_RX_STATS_OFFSET(pf_id) */ { 0x12988, 0x10, 0x0, 0x0, 0x8}, /* USTORM_ISCSI_RX_STATS_OFFSET(pf_id) */ - { 0x11aa0, 0x38, 0x0, 0x0, 0x18}, + { 0x11fa0, 0x38, 0x0, 0x0, 0x18}, /* XSTORM_ISCSI_TX_STATS_OFFSET(pf_id) */ { 0xa8c0, 0x38, 0x0, 0x0, 0x10}, /* YSTORM_ISCSI_TX_STATS_OFFSET(pf_id) */ diff --git a/drivers/net/qede/base/ecore_l2.c b/drivers/net/qede/base/ecore_l2.c index 4ab8fd5f..e58b8fa0 100644 --- a/drivers/net/qede/base/ecore_l2.c +++ b/drivers/net/qede/base/ecore_l2.c @@ -1714,13 +1714,20 @@ static void __ecore_get_vport_pstats(struct ecore_hwfn *p_hwfn, OSAL_MEMSET(&pstats, 0, sizeof(pstats)); ecore_memcpy_from(p_hwfn, p_ptt, &pstats, pstats_addr, pstats_len); - p_stats->tx_ucast_bytes += HILO_64_REGPAIR(pstats.sent_ucast_bytes); - p_stats->tx_mcast_bytes += HILO_64_REGPAIR(pstats.sent_mcast_bytes); - p_stats->tx_bcast_bytes += HILO_64_REGPAIR(pstats.sent_bcast_bytes); - p_stats->tx_ucast_pkts += HILO_64_REGPAIR(pstats.sent_ucast_pkts); - p_stats->tx_mcast_pkts += HILO_64_REGPAIR(pstats.sent_mcast_pkts); - p_stats->tx_bcast_pkts += HILO_64_REGPAIR(pstats.sent_bcast_pkts); - p_stats->tx_err_drop_pkts += HILO_64_REGPAIR(pstats.error_drop_pkts); + p_stats->common.tx_ucast_bytes += + HILO_64_REGPAIR(pstats.sent_ucast_bytes); + p_stats->common.tx_mcast_bytes += + HILO_64_REGPAIR(pstats.sent_mcast_bytes); + p_stats->common.tx_bcast_bytes += + HILO_64_REGPAIR(pstats.sent_bcast_bytes); + p_stats->common.tx_ucast_pkts += + HILO_64_REGPAIR(pstats.sent_ucast_pkts); + p_stats->common.tx_mcast_pkts += + HILO_64_REGPAIR(pstats.sent_mcast_pkts); + p_stats->common.tx_bcast_pkts += + HILO_64_REGPAIR(pstats.sent_bcast_pkts); + p_stats->common.tx_err_drop_pkts += + HILO_64_REGPAIR(pstats.error_drop_pkts); } static void __ecore_get_vport_tstats(struct ecore_hwfn *p_hwfn, @@ -1746,10 +1753,10 @@ static void __ecore_get_vport_tstats(struct ecore_hwfn *p_hwfn, OSAL_MEMSET(&tstats, 0, sizeof(tstats)); ecore_memcpy_from(p_hwfn, p_ptt, &tstats, tstats_addr, tstats_len); - p_stats->mftag_filter_discards += - HILO_64_REGPAIR(tstats.mftag_filter_discard); - p_stats->mac_filter_discards += - HILO_64_REGPAIR(tstats.eth_mac_filter_discard); + p_stats->common.mftag_filter_discards += + HILO_64_REGPAIR(tstats.mftag_filter_discard); + p_stats->common.mac_filter_discards += + HILO_64_REGPAIR(tstats.eth_mac_filter_discard); } static void __ecore_get_vport_ustats_addrlen(struct ecore_hwfn *p_hwfn, @@ -1783,12 +1790,18 @@ static void __ecore_get_vport_ustats(struct ecore_hwfn *p_hwfn, OSAL_MEMSET(&ustats, 0, sizeof(ustats)); ecore_memcpy_from(p_hwfn, p_ptt, &ustats, ustats_addr, ustats_len); - p_stats->rx_ucast_bytes += HILO_64_REGPAIR(ustats.rcv_ucast_bytes); - p_stats->rx_mcast_bytes += HILO_64_REGPAIR(ustats.rcv_mcast_bytes); - p_stats->rx_bcast_bytes += HILO_64_REGPAIR(ustats.rcv_bcast_bytes); - p_stats->rx_ucast_pkts += HILO_64_REGPAIR(ustats.rcv_ucast_pkts); - p_stats->rx_mcast_pkts += HILO_64_REGPAIR(ustats.rcv_mcast_pkts); - p_stats->rx_bcast_pkts += HILO_64_REGPAIR(ustats.rcv_bcast_pkts); + p_stats->common.rx_ucast_bytes += + HILO_64_REGPAIR(ustats.rcv_ucast_bytes); + p_stats->common.rx_mcast_bytes += + HILO_64_REGPAIR(ustats.rcv_mcast_bytes); + p_stats->common.rx_bcast_bytes += + HILO_64_REGPAIR(ustats.rcv_bcast_bytes); + p_stats->common.rx_ucast_pkts += + HILO_64_REGPAIR(ustats.rcv_ucast_pkts); + p_stats->common.rx_mcast_pkts += + HILO_64_REGPAIR(ustats.rcv_mcast_pkts); + p_stats->common.rx_bcast_pkts += + HILO_64_REGPAIR(ustats.rcv_bcast_pkts); } static void __ecore_get_vport_mstats_addrlen(struct ecore_hwfn *p_hwfn, @@ -1822,23 +1835,27 @@ static void __ecore_get_vport_mstats(struct ecore_hwfn *p_hwfn, OSAL_MEMSET(&mstats, 0, sizeof(mstats)); ecore_memcpy_from(p_hwfn, p_ptt, &mstats, mstats_addr, mstats_len); - p_stats->no_buff_discards += HILO_64_REGPAIR(mstats.no_buff_discard); - p_stats->packet_too_big_discard += - HILO_64_REGPAIR(mstats.packet_too_big_discard); - p_stats->ttl0_discard += HILO_64_REGPAIR(mstats.ttl0_discard); - p_stats->tpa_coalesced_pkts += - HILO_64_REGPAIR(mstats.tpa_coalesced_pkts); - p_stats->tpa_coalesced_events += - HILO_64_REGPAIR(mstats.tpa_coalesced_events); - p_stats->tpa_aborts_num += HILO_64_REGPAIR(mstats.tpa_aborts_num); - p_stats->tpa_coalesced_bytes += - HILO_64_REGPAIR(mstats.tpa_coalesced_bytes); + p_stats->common.no_buff_discards += + HILO_64_REGPAIR(mstats.no_buff_discard); + p_stats->common.packet_too_big_discard += + HILO_64_REGPAIR(mstats.packet_too_big_discard); + p_stats->common.ttl0_discard += + HILO_64_REGPAIR(mstats.ttl0_discard); + p_stats->common.tpa_coalesced_pkts += + HILO_64_REGPAIR(mstats.tpa_coalesced_pkts); + p_stats->common.tpa_coalesced_events += + HILO_64_REGPAIR(mstats.tpa_coalesced_events); + p_stats->common.tpa_aborts_num += + HILO_64_REGPAIR(mstats.tpa_aborts_num); + p_stats->common.tpa_coalesced_bytes += + HILO_64_REGPAIR(mstats.tpa_coalesced_bytes); } static void __ecore_get_vport_port_stats(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt, struct ecore_eth_stats *p_stats) { + struct ecore_eth_stats_common *p_common = &p_stats->common; struct port_stats port_stats; int j; @@ -1849,54 +1866,75 @@ static void __ecore_get_vport_port_stats(struct ecore_hwfn *p_hwfn, OFFSETOF(struct public_port, stats), sizeof(port_stats)); - p_stats->rx_64_byte_packets += port_stats.eth.r64; - p_stats->rx_65_to_127_byte_packets += port_stats.eth.r127; - p_stats->rx_128_to_255_byte_packets += port_stats.eth.r255; - p_stats->rx_256_to_511_byte_packets += port_stats.eth.r511; - p_stats->rx_512_to_1023_byte_packets += port_stats.eth.r1023; - p_stats->rx_1024_to_1518_byte_packets += port_stats.eth.r1518; - p_stats->rx_1519_to_1522_byte_packets += port_stats.eth.r1522; - p_stats->rx_1519_to_2047_byte_packets += port_stats.eth.r2047; - p_stats->rx_2048_to_4095_byte_packets += port_stats.eth.r4095; - p_stats->rx_4096_to_9216_byte_packets += port_stats.eth.r9216; - p_stats->rx_9217_to_16383_byte_packets += port_stats.eth.r16383; - p_stats->rx_crc_errors += port_stats.eth.rfcs; - p_stats->rx_mac_crtl_frames += port_stats.eth.rxcf; - p_stats->rx_pause_frames += port_stats.eth.rxpf; - p_stats->rx_pfc_frames += port_stats.eth.rxpp; - p_stats->rx_align_errors += port_stats.eth.raln; - p_stats->rx_carrier_errors += port_stats.eth.rfcr; - p_stats->rx_oversize_packets += port_stats.eth.rovr; - p_stats->rx_jabbers += port_stats.eth.rjbr; - p_stats->rx_undersize_packets += port_stats.eth.rund; - p_stats->rx_fragments += port_stats.eth.rfrg; - p_stats->tx_64_byte_packets += port_stats.eth.t64; - p_stats->tx_65_to_127_byte_packets += port_stats.eth.t127; - p_stats->tx_128_to_255_byte_packets += port_stats.eth.t255; - p_stats->tx_256_to_511_byte_packets += port_stats.eth.t511; - p_stats->tx_512_to_1023_byte_packets += port_stats.eth.t1023; - p_stats->tx_1024_to_1518_byte_packets += port_stats.eth.t1518; - p_stats->tx_1519_to_2047_byte_packets += port_stats.eth.t2047; - p_stats->tx_2048_to_4095_byte_packets += port_stats.eth.t4095; - p_stats->tx_4096_to_9216_byte_packets += port_stats.eth.t9216; - p_stats->tx_9217_to_16383_byte_packets += port_stats.eth.t16383; - p_stats->tx_pause_frames += port_stats.eth.txpf; - p_stats->tx_pfc_frames += port_stats.eth.txpp; - p_stats->tx_lpi_entry_count += port_stats.eth.tlpiec; - p_stats->tx_total_collisions += port_stats.eth.tncl; - p_stats->rx_mac_bytes += port_stats.eth.rbyte; - p_stats->rx_mac_uc_packets += port_stats.eth.rxuca; - p_stats->rx_mac_mc_packets += port_stats.eth.rxmca; - p_stats->rx_mac_bc_packets += port_stats.eth.rxbca; - p_stats->rx_mac_frames_ok += port_stats.eth.rxpok; - p_stats->tx_mac_bytes += port_stats.eth.tbyte; - p_stats->tx_mac_uc_packets += port_stats.eth.txuca; - p_stats->tx_mac_mc_packets += port_stats.eth.txmca; - p_stats->tx_mac_bc_packets += port_stats.eth.txbca; - p_stats->tx_mac_ctrl_frames += port_stats.eth.txcf; + p_common->rx_64_byte_packets += port_stats.eth.r64; + p_common->rx_65_to_127_byte_packets += port_stats.eth.r127; + p_common->rx_128_to_255_byte_packets += port_stats.eth.r255; + p_common->rx_256_to_511_byte_packets += port_stats.eth.r511; + p_common->rx_512_to_1023_byte_packets += port_stats.eth.r1023; + p_common->rx_1024_to_1518_byte_packets += port_stats.eth.r1518; + p_common->rx_crc_errors += port_stats.eth.rfcs; + p_common->rx_mac_crtl_frames += port_stats.eth.rxcf; + p_common->rx_pause_frames += port_stats.eth.rxpf; + p_common->rx_pfc_frames += port_stats.eth.rxpp; + p_common->rx_align_errors += port_stats.eth.raln; + p_common->rx_carrier_errors += port_stats.eth.rfcr; + p_common->rx_oversize_packets += port_stats.eth.rovr; + p_common->rx_jabbers += port_stats.eth.rjbr; + p_common->rx_undersize_packets += port_stats.eth.rund; + p_common->rx_fragments += port_stats.eth.rfrg; + p_common->tx_64_byte_packets += port_stats.eth.t64; + p_common->tx_65_to_127_byte_packets += port_stats.eth.t127; + p_common->tx_128_to_255_byte_packets += port_stats.eth.t255; + p_common->tx_256_to_511_byte_packets += port_stats.eth.t511; + p_common->tx_512_to_1023_byte_packets += port_stats.eth.t1023; + p_common->tx_1024_to_1518_byte_packets += port_stats.eth.t1518; + p_common->tx_pause_frames += port_stats.eth.txpf; + p_common->tx_pfc_frames += port_stats.eth.txpp; + p_common->rx_mac_bytes += port_stats.eth.rbyte; + p_common->rx_mac_uc_packets += port_stats.eth.rxuca; + p_common->rx_mac_mc_packets += port_stats.eth.rxmca; + p_common->rx_mac_bc_packets += port_stats.eth.rxbca; + p_common->rx_mac_frames_ok += port_stats.eth.rxpok; + p_common->tx_mac_bytes += port_stats.eth.tbyte; + p_common->tx_mac_uc_packets += port_stats.eth.txuca; + p_common->tx_mac_mc_packets += port_stats.eth.txmca; + p_common->tx_mac_bc_packets += port_stats.eth.txbca; + p_common->tx_mac_ctrl_frames += port_stats.eth.txcf; for (j = 0; j < 8; j++) { - p_stats->brb_truncates += port_stats.brb.brb_truncate[j]; - p_stats->brb_discards += port_stats.brb.brb_discard[j]; + p_common->brb_truncates += port_stats.brb.brb_truncate[j]; + p_common->brb_discards += port_stats.brb.brb_discard[j]; + } + + if (ECORE_IS_BB(p_hwfn->p_dev)) { + struct ecore_eth_stats_bb *p_bb = &p_stats->bb; + + p_bb->rx_1519_to_1522_byte_packets += + port_stats.eth.u0.bb0.r1522; + p_bb->rx_1519_to_2047_byte_packets += + port_stats.eth.u0.bb0.r2047; + p_bb->rx_2048_to_4095_byte_packets += + port_stats.eth.u0.bb0.r4095; + p_bb->rx_4096_to_9216_byte_packets += + port_stats.eth.u0.bb0.r9216; + p_bb->rx_9217_to_16383_byte_packets += + port_stats.eth.u0.bb0.r16383; + p_bb->tx_1519_to_2047_byte_packets += + port_stats.eth.u1.bb1.t2047; + p_bb->tx_2048_to_4095_byte_packets += + port_stats.eth.u1.bb1.t4095; + p_bb->tx_4096_to_9216_byte_packets += + port_stats.eth.u1.bb1.t9216; + p_bb->tx_9217_to_16383_byte_packets += + port_stats.eth.u1.bb1.t16383; + p_bb->tx_lpi_entry_count += port_stats.eth.u2.bb2.tlpiec; + p_bb->tx_total_collisions += port_stats.eth.u2.bb2.tncl; + } else { + struct ecore_eth_stats_ah *p_ah = &p_stats->ah; + + p_ah->rx_1519_to_max_byte_packets += + port_stats.eth.u0.ah0.r1519_to_max; + p_ah->tx_1519_to_max_byte_packets = + port_stats.eth.u1.ah1.t1519_to_max; } } diff --git a/drivers/net/qede/base/ecore_mcp.c b/drivers/net/qede/base/ecore_mcp.c index a834ac74..88c5ceb0 100644 --- a/drivers/net/qede/base/ecore_mcp.c +++ b/drivers/net/qede/base/ecore_mcp.c @@ -893,6 +893,30 @@ enum _ecore_status_t ecore_mcp_load_req(struct ecore_hwfn *p_hwfn, return ECORE_SUCCESS; } +enum _ecore_status_t ecore_mcp_load_done(struct ecore_hwfn *p_hwfn, + struct ecore_ptt *p_ptt) +{ + u32 resp = 0, param = 0; + enum _ecore_status_t rc; + + rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_LOAD_DONE, 0, &resp, + ¶m); + if (rc != ECORE_SUCCESS) { + DP_NOTICE(p_hwfn, false, + "Failed to send a LOAD_DONE command, rc = %d\n", rc); + return rc; + } + +#define FW_MB_PARAM_LOAD_DONE_DID_EFUSE_ERROR (1 << 0) + + /* Check if there is a DID mismatch between nvm-cfg/efuse */ + if (param & FW_MB_PARAM_LOAD_DONE_DID_EFUSE_ERROR) + DP_NOTICE(p_hwfn, false, + "warning: device configuration is not supported on this board type. The device may not function as expected.\n"); + + return ECORE_SUCCESS; +} + enum _ecore_status_t ecore_mcp_unload_req(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt) { @@ -1556,10 +1580,9 @@ static void ecore_mcp_handle_critical_error(struct ecore_hwfn *p_hwfn, DP_NOTICE(p_hwfn, false, "Received a critical error notification from the MFW!\n"); - if (p_hwfn->p_dev->mdump_en) { + if (p_hwfn->p_dev->allow_mdump) { DP_NOTICE(p_hwfn, false, "Not acknowledging the notification to allow the MFW crash dump\n"); - p_hwfn->p_dev->mdump_en = false; return; } @@ -2894,6 +2917,27 @@ struct ecore_resc_alloc_out_params { u32 flags; }; +#define ECORE_RECOVERY_PROLOG_SLEEP_MS 100 + +enum _ecore_status_t ecore_recovery_prolog(struct ecore_dev *p_dev) +{ + struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev); + struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt; + enum _ecore_status_t rc; + + /* Allow ongoing PCIe transactions to complete */ + OSAL_MSLEEP(ECORE_RECOVERY_PROLOG_SLEEP_MS); + + /* Clear the PF's internal FID_enable in the PXP */ + rc = ecore_pglueb_set_pfid_enable(p_hwfn, p_ptt, false); + if (rc != ECORE_SUCCESS) + DP_NOTICE(p_hwfn, false, + "ecore_pglueb_set_pfid_enable() failed. rc = %d.\n", + rc); + + return rc; +} + static enum _ecore_status_t ecore_mcp_resc_allocation_msg(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt, diff --git a/drivers/net/qede/base/ecore_mcp.h b/drivers/net/qede/base/ecore_mcp.h index 37d1835f..77fb5a3c 100644 --- a/drivers/net/qede/base/ecore_mcp.h +++ b/drivers/net/qede/base/ecore_mcp.h @@ -171,6 +171,17 @@ enum _ecore_status_t ecore_mcp_load_req(struct ecore_hwfn *p_hwfn, struct ecore_load_req_params *p_params); /** + * @brief Sends a LOAD_DONE message to the MFW + * + * @param p_hwfn + * @param p_ptt + * + * @return enum _ecore_status_t - ECORE_SUCCESS - Operation was successful. + */ +enum _ecore_status_t ecore_mcp_load_done(struct ecore_hwfn *p_hwfn, + struct ecore_ptt *p_ptt); + +/** * @brief Sends a UNLOAD_REQ message to the MFW * * @param p_hwfn diff --git a/drivers/net/qede/base/ecore_mcp_api.h b/drivers/net/qede/base/ecore_mcp_api.h index 190c1352..abc190c9 100644 --- a/drivers/net/qede/base/ecore_mcp_api.h +++ b/drivers/net/qede/base/ecore_mcp_api.h @@ -736,6 +736,17 @@ enum _ecore_status_t ecore_start_recovery_process(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt); /** + * @brief A recovery handler must call this function as its first step. + * It is assumed that the handler is not run from an interrupt context. + * + * @param p_dev + * @param p_ptt + * + * @return enum _ecore_status_t + */ +enum _ecore_status_t ecore_recovery_prolog(struct ecore_dev *p_dev); + +/** * @brief Notify MFW about the change in base device properties * * @param p_hwfn diff --git a/drivers/net/qede/base/ecore_rt_defs.h b/drivers/net/qede/base/ecore_rt_defs.h index 846dc6d1..c9c23096 100644 --- a/drivers/net/qede/base/ecore_rt_defs.h +++ b/drivers/net/qede/base/ecore_rt_defs.h @@ -94,359 +94,358 @@ #define PSWRQ2_REG_CDUC_BLOCKS_FACTOR_RT_OFFSET 6697 #define PSWRQ2_REG_VF_BASE_RT_OFFSET 6698 #define PSWRQ2_REG_VF_LAST_ILT_RT_OFFSET 6699 -#define PSWRQ2_REG_WR_MBS0_RT_OFFSET 6700 -#define PSWRQ2_REG_RD_MBS0_RT_OFFSET 6701 -#define PSWRQ2_REG_DRAM_ALIGN_WR_RT_OFFSET 6702 -#define PSWRQ2_REG_DRAM_ALIGN_RD_RT_OFFSET 6703 -#define PSWRQ2_REG_ILT_MEMORY_RT_OFFSET 6704 +#define PSWRQ2_REG_DRAM_ALIGN_WR_RT_OFFSET 6700 +#define PSWRQ2_REG_DRAM_ALIGN_RD_RT_OFFSET 6701 +#define PSWRQ2_REG_ILT_MEMORY_RT_OFFSET 6702 #define PSWRQ2_REG_ILT_MEMORY_RT_SIZE 22000 -#define PGLUE_REG_B_VF_BASE_RT_OFFSET 28704 -#define PGLUE_REG_B_MSDM_OFFSET_MASK_B_RT_OFFSET 28705 -#define PGLUE_REG_B_MSDM_VF_SHIFT_B_RT_OFFSET 28706 -#define PGLUE_REG_B_CACHE_LINE_SIZE_RT_OFFSET 28707 -#define PGLUE_REG_B_PF_BAR0_SIZE_RT_OFFSET 28708 -#define PGLUE_REG_B_PF_BAR1_SIZE_RT_OFFSET 28709 -#define PGLUE_REG_B_VF_BAR1_SIZE_RT_OFFSET 28710 -#define TM_REG_VF_ENABLE_CONN_RT_OFFSET 28711 -#define TM_REG_PF_ENABLE_CONN_RT_OFFSET 28712 -#define TM_REG_PF_ENABLE_TASK_RT_OFFSET 28713 -#define TM_REG_GROUP_SIZE_RESOLUTION_CONN_RT_OFFSET 28714 -#define TM_REG_GROUP_SIZE_RESOLUTION_TASK_RT_OFFSET 28715 -#define TM_REG_CONFIG_CONN_MEM_RT_OFFSET 28716 +#define PGLUE_REG_B_VF_BASE_RT_OFFSET 28702 +#define PGLUE_REG_B_MSDM_OFFSET_MASK_B_RT_OFFSET 28703 +#define PGLUE_REG_B_MSDM_VF_SHIFT_B_RT_OFFSET 28704 +#define PGLUE_REG_B_CACHE_LINE_SIZE_RT_OFFSET 28705 +#define PGLUE_REG_B_PF_BAR0_SIZE_RT_OFFSET 28706 +#define PGLUE_REG_B_PF_BAR1_SIZE_RT_OFFSET 28707 +#define PGLUE_REG_B_VF_BAR1_SIZE_RT_OFFSET 28708 +#define TM_REG_VF_ENABLE_CONN_RT_OFFSET 28709 +#define TM_REG_PF_ENABLE_CONN_RT_OFFSET 28710 +#define TM_REG_PF_ENABLE_TASK_RT_OFFSET 28711 +#define TM_REG_GROUP_SIZE_RESOLUTION_CONN_RT_OFFSET 28712 +#define TM_REG_GROUP_SIZE_RESOLUTION_TASK_RT_OFFSET 28713 +#define TM_REG_CONFIG_CONN_MEM_RT_OFFSET 28714 #define TM_REG_CONFIG_CONN_MEM_RT_SIZE 416 -#define TM_REG_CONFIG_TASK_MEM_RT_OFFSET 29132 +#define TM_REG_CONFIG_TASK_MEM_RT_OFFSET 29130 #define TM_REG_CONFIG_TASK_MEM_RT_SIZE 608 -#define QM_REG_MAXPQSIZE_0_RT_OFFSET 29740 -#define QM_REG_MAXPQSIZE_1_RT_OFFSET 29741 -#define QM_REG_MAXPQSIZE_2_RT_OFFSET 29742 -#define QM_REG_MAXPQSIZETXSEL_0_RT_OFFSET 29743 -#define QM_REG_MAXPQSIZETXSEL_1_RT_OFFSET 29744 -#define QM_REG_MAXPQSIZETXSEL_2_RT_OFFSET 29745 -#define QM_REG_MAXPQSIZETXSEL_3_RT_OFFSET 29746 -#define QM_REG_MAXPQSIZETXSEL_4_RT_OFFSET 29747 -#define QM_REG_MAXPQSIZETXSEL_5_RT_OFFSET 29748 -#define QM_REG_MAXPQSIZETXSEL_6_RT_OFFSET 29749 -#define QM_REG_MAXPQSIZETXSEL_7_RT_OFFSET 29750 -#define QM_REG_MAXPQSIZETXSEL_8_RT_OFFSET 29751 -#define QM_REG_MAXPQSIZETXSEL_9_RT_OFFSET 29752 -#define QM_REG_MAXPQSIZETXSEL_10_RT_OFFSET 29753 -#define QM_REG_MAXPQSIZETXSEL_11_RT_OFFSET 29754 -#define QM_REG_MAXPQSIZETXSEL_12_RT_OFFSET 29755 -#define QM_REG_MAXPQSIZETXSEL_13_RT_OFFSET 29756 -#define QM_REG_MAXPQSIZETXSEL_14_RT_OFFSET 29757 -#define QM_REG_MAXPQSIZETXSEL_15_RT_OFFSET 29758 -#define QM_REG_MAXPQSIZETXSEL_16_RT_OFFSET 29759 -#define QM_REG_MAXPQSIZETXSEL_17_RT_OFFSET 29760 -#define QM_REG_MAXPQSIZETXSEL_18_RT_OFFSET 29761 -#define QM_REG_MAXPQSIZETXSEL_19_RT_OFFSET 29762 -#define QM_REG_MAXPQSIZETXSEL_20_RT_OFFSET 29763 -#define QM_REG_MAXPQSIZETXSEL_21_RT_OFFSET 29764 -#define QM_REG_MAXPQSIZETXSEL_22_RT_OFFSET 29765 -#define QM_REG_MAXPQSIZETXSEL_23_RT_OFFSET 29766 -#define QM_REG_MAXPQSIZETXSEL_24_RT_OFFSET 29767 -#define QM_REG_MAXPQSIZETXSEL_25_RT_OFFSET 29768 -#define QM_REG_MAXPQSIZETXSEL_26_RT_OFFSET 29769 -#define QM_REG_MAXPQSIZETXSEL_27_RT_OFFSET 29770 -#define QM_REG_MAXPQSIZETXSEL_28_RT_OFFSET 29771 -#define QM_REG_MAXPQSIZETXSEL_29_RT_OFFSET 29772 -#define QM_REG_MAXPQSIZETXSEL_30_RT_OFFSET 29773 -#define QM_REG_MAXPQSIZETXSEL_31_RT_OFFSET 29774 -#define QM_REG_MAXPQSIZETXSEL_32_RT_OFFSET 29775 -#define QM_REG_MAXPQSIZETXSEL_33_RT_OFFSET 29776 -#define QM_REG_MAXPQSIZETXSEL_34_RT_OFFSET 29777 -#define QM_REG_MAXPQSIZETXSEL_35_RT_OFFSET 29778 -#define QM_REG_MAXPQSIZETXSEL_36_RT_OFFSET 29779 -#define QM_REG_MAXPQSIZETXSEL_37_RT_OFFSET 29780 -#define QM_REG_MAXPQSIZETXSEL_38_RT_OFFSET 29781 -#define QM_REG_MAXPQSIZETXSEL_39_RT_OFFSET 29782 -#define QM_REG_MAXPQSIZETXSEL_40_RT_OFFSET 29783 -#define QM_REG_MAXPQSIZETXSEL_41_RT_OFFSET 29784 -#define QM_REG_MAXPQSIZETXSEL_42_RT_OFFSET 29785 -#define QM_REG_MAXPQSIZETXSEL_43_RT_OFFSET 29786 -#define QM_REG_MAXPQSIZETXSEL_44_RT_OFFSET 29787 -#define QM_REG_MAXPQSIZETXSEL_45_RT_OFFSET 29788 -#define QM_REG_MAXPQSIZETXSEL_46_RT_OFFSET 29789 -#define QM_REG_MAXPQSIZETXSEL_47_RT_OFFSET 29790 -#define QM_REG_MAXPQSIZETXSEL_48_RT_OFFSET 29791 -#define QM_REG_MAXPQSIZETXSEL_49_RT_OFFSET 29792 -#define QM_REG_MAXPQSIZETXSEL_50_RT_OFFSET 29793 -#define QM_REG_MAXPQSIZETXSEL_51_RT_OFFSET 29794 -#define QM_REG_MAXPQSIZETXSEL_52_RT_OFFSET 29795 -#define QM_REG_MAXPQSIZETXSEL_53_RT_OFFSET 29796 -#define QM_REG_MAXPQSIZETXSEL_54_RT_OFFSET 29797 -#define QM_REG_MAXPQSIZETXSEL_55_RT_OFFSET 29798 -#define QM_REG_MAXPQSIZETXSEL_56_RT_OFFSET 29799 -#define QM_REG_MAXPQSIZETXSEL_57_RT_OFFSET 29800 -#define QM_REG_MAXPQSIZETXSEL_58_RT_OFFSET 29801 -#define QM_REG_MAXPQSIZETXSEL_59_RT_OFFSET 29802 -#define QM_REG_MAXPQSIZETXSEL_60_RT_OFFSET 29803 -#define QM_REG_MAXPQSIZETXSEL_61_RT_OFFSET 29804 -#define QM_REG_MAXPQSIZETXSEL_62_RT_OFFSET 29805 -#define QM_REG_MAXPQSIZETXSEL_63_RT_OFFSET 29806 -#define QM_REG_BASEADDROTHERPQ_RT_OFFSET 29807 -#define QM_REG_AFULLQMBYPTHRPFWFQ_RT_OFFSET 29935 -#define QM_REG_AFULLQMBYPTHRVPWFQ_RT_OFFSET 29936 -#define QM_REG_AFULLQMBYPTHRPFRL_RT_OFFSET 29937 -#define QM_REG_AFULLQMBYPTHRGLBLRL_RT_OFFSET 29938 -#define QM_REG_AFULLOPRTNSTCCRDMASK_RT_OFFSET 29939 -#define QM_REG_WRROTHERPQGRP_0_RT_OFFSET 29940 -#define QM_REG_WRROTHERPQGRP_1_RT_OFFSET 29941 -#define QM_REG_WRROTHERPQGRP_2_RT_OFFSET 29942 -#define QM_REG_WRROTHERPQGRP_3_RT_OFFSET 29943 -#define QM_REG_WRROTHERPQGRP_4_RT_OFFSET 29944 -#define QM_REG_WRROTHERPQGRP_5_RT_OFFSET 29945 -#define QM_REG_WRROTHERPQGRP_6_RT_OFFSET 29946 -#define QM_REG_WRROTHERPQGRP_7_RT_OFFSET 29947 -#define QM_REG_WRROTHERPQGRP_8_RT_OFFSET 29948 -#define QM_REG_WRROTHERPQGRP_9_RT_OFFSET 29949 -#define QM_REG_WRROTHERPQGRP_10_RT_OFFSET 29950 -#define QM_REG_WRROTHERPQGRP_11_RT_OFFSET 29951 -#define QM_REG_WRROTHERPQGRP_12_RT_OFFSET 29952 -#define QM_REG_WRROTHERPQGRP_13_RT_OFFSET 29953 -#define QM_REG_WRROTHERPQGRP_14_RT_OFFSET 29954 -#define QM_REG_WRROTHERPQGRP_15_RT_OFFSET 29955 -#define QM_REG_WRROTHERGRPWEIGHT_0_RT_OFFSET 29956 -#define QM_REG_WRROTHERGRPWEIGHT_1_RT_OFFSET 29957 -#define QM_REG_WRROTHERGRPWEIGHT_2_RT_OFFSET 29958 -#define QM_REG_WRROTHERGRPWEIGHT_3_RT_OFFSET 29959 -#define QM_REG_WRRTXGRPWEIGHT_0_RT_OFFSET 29960 -#define QM_REG_WRRTXGRPWEIGHT_1_RT_OFFSET 29961 -#define QM_REG_PQTX2PF_0_RT_OFFSET 29962 -#define QM_REG_PQTX2PF_1_RT_OFFSET 29963 -#define QM_REG_PQTX2PF_2_RT_OFFSET 29964 -#define QM_REG_PQTX2PF_3_RT_OFFSET 29965 -#define QM_REG_PQTX2PF_4_RT_OFFSET 29966 -#define QM_REG_PQTX2PF_5_RT_OFFSET 29967 -#define QM_REG_PQTX2PF_6_RT_OFFSET 29968 -#define QM_REG_PQTX2PF_7_RT_OFFSET 29969 -#define QM_REG_PQTX2PF_8_RT_OFFSET 29970 -#define QM_REG_PQTX2PF_9_RT_OFFSET 29971 -#define QM_REG_PQTX2PF_10_RT_OFFSET 29972 -#define QM_REG_PQTX2PF_11_RT_OFFSET 29973 -#define QM_REG_PQTX2PF_12_RT_OFFSET 29974 -#define QM_REG_PQTX2PF_13_RT_OFFSET 29975 -#define QM_REG_PQTX2PF_14_RT_OFFSET 29976 -#define QM_REG_PQTX2PF_15_RT_OFFSET 29977 -#define QM_REG_PQTX2PF_16_RT_OFFSET 29978 -#define QM_REG_PQTX2PF_17_RT_OFFSET 29979 -#define QM_REG_PQTX2PF_18_RT_OFFSET 29980 -#define QM_REG_PQTX2PF_19_RT_OFFSET 29981 -#define QM_REG_PQTX2PF_20_RT_OFFSET 29982 -#define QM_REG_PQTX2PF_21_RT_OFFSET 29983 -#define QM_REG_PQTX2PF_22_RT_OFFSET 29984 -#define QM_REG_PQTX2PF_23_RT_OFFSET 29985 -#define QM_REG_PQTX2PF_24_RT_OFFSET 29986 -#define QM_REG_PQTX2PF_25_RT_OFFSET 29987 -#define QM_REG_PQTX2PF_26_RT_OFFSET 29988 -#define QM_REG_PQTX2PF_27_RT_OFFSET 29989 -#define QM_REG_PQTX2PF_28_RT_OFFSET 29990 -#define QM_REG_PQTX2PF_29_RT_OFFSET 29991 -#define QM_REG_PQTX2PF_30_RT_OFFSET 29992 -#define QM_REG_PQTX2PF_31_RT_OFFSET 29993 -#define QM_REG_PQTX2PF_32_RT_OFFSET 29994 -#define QM_REG_PQTX2PF_33_RT_OFFSET 29995 -#define QM_REG_PQTX2PF_34_RT_OFFSET 29996 -#define QM_REG_PQTX2PF_35_RT_OFFSET 29997 -#define QM_REG_PQTX2PF_36_RT_OFFSET 29998 -#define QM_REG_PQTX2PF_37_RT_OFFSET 29999 -#define QM_REG_PQTX2PF_38_RT_OFFSET 30000 -#define QM_REG_PQTX2PF_39_RT_OFFSET 30001 -#define QM_REG_PQTX2PF_40_RT_OFFSET 30002 -#define QM_REG_PQTX2PF_41_RT_OFFSET 30003 -#define QM_REG_PQTX2PF_42_RT_OFFSET 30004 -#define QM_REG_PQTX2PF_43_RT_OFFSET 30005 -#define QM_REG_PQTX2PF_44_RT_OFFSET 30006 -#define QM_REG_PQTX2PF_45_RT_OFFSET 30007 -#define QM_REG_PQTX2PF_46_RT_OFFSET 30008 -#define QM_REG_PQTX2PF_47_RT_OFFSET 30009 -#define QM_REG_PQTX2PF_48_RT_OFFSET 30010 -#define QM_REG_PQTX2PF_49_RT_OFFSET 30011 -#define QM_REG_PQTX2PF_50_RT_OFFSET 30012 -#define QM_REG_PQTX2PF_51_RT_OFFSET 30013 -#define QM_REG_PQTX2PF_52_RT_OFFSET 30014 -#define QM_REG_PQTX2PF_53_RT_OFFSET 30015 -#define QM_REG_PQTX2PF_54_RT_OFFSET 30016 -#define QM_REG_PQTX2PF_55_RT_OFFSET 30017 -#define QM_REG_PQTX2PF_56_RT_OFFSET 30018 -#define QM_REG_PQTX2PF_57_RT_OFFSET 30019 -#define QM_REG_PQTX2PF_58_RT_OFFSET 30020 -#define QM_REG_PQTX2PF_59_RT_OFFSET 30021 -#define QM_REG_PQTX2PF_60_RT_OFFSET 30022 -#define QM_REG_PQTX2PF_61_RT_OFFSET 30023 -#define QM_REG_PQTX2PF_62_RT_OFFSET 30024 -#define QM_REG_PQTX2PF_63_RT_OFFSET 30025 -#define QM_REG_PQOTHER2PF_0_RT_OFFSET 30026 -#define QM_REG_PQOTHER2PF_1_RT_OFFSET 30027 -#define QM_REG_PQOTHER2PF_2_RT_OFFSET 30028 -#define QM_REG_PQOTHER2PF_3_RT_OFFSET 30029 -#define QM_REG_PQOTHER2PF_4_RT_OFFSET 30030 -#define QM_REG_PQOTHER2PF_5_RT_OFFSET 30031 -#define QM_REG_PQOTHER2PF_6_RT_OFFSET 30032 -#define QM_REG_PQOTHER2PF_7_RT_OFFSET 30033 -#define QM_REG_PQOTHER2PF_8_RT_OFFSET 30034 -#define QM_REG_PQOTHER2PF_9_RT_OFFSET 30035 -#define QM_REG_PQOTHER2PF_10_RT_OFFSET 30036 -#define QM_REG_PQOTHER2PF_11_RT_OFFSET 30037 -#define QM_REG_PQOTHER2PF_12_RT_OFFSET 30038 -#define QM_REG_PQOTHER2PF_13_RT_OFFSET 30039 -#define QM_REG_PQOTHER2PF_14_RT_OFFSET 30040 -#define QM_REG_PQOTHER2PF_15_RT_OFFSET 30041 -#define QM_REG_RLGLBLPERIOD_0_RT_OFFSET 30042 -#define QM_REG_RLGLBLPERIOD_1_RT_OFFSET 30043 -#define QM_REG_RLGLBLPERIODTIMER_0_RT_OFFSET 30044 -#define QM_REG_RLGLBLPERIODTIMER_1_RT_OFFSET 30045 -#define QM_REG_RLGLBLPERIODSEL_0_RT_OFFSET 30046 -#define QM_REG_RLGLBLPERIODSEL_1_RT_OFFSET 30047 -#define QM_REG_RLGLBLPERIODSEL_2_RT_OFFSET 30048 -#define QM_REG_RLGLBLPERIODSEL_3_RT_OFFSET 30049 -#define QM_REG_RLGLBLPERIODSEL_4_RT_OFFSET 30050 -#define QM_REG_RLGLBLPERIODSEL_5_RT_OFFSET 30051 -#define QM_REG_RLGLBLPERIODSEL_6_RT_OFFSET 30052 -#define QM_REG_RLGLBLPERIODSEL_7_RT_OFFSET 30053 -#define QM_REG_RLGLBLINCVAL_RT_OFFSET 30054 +#define QM_REG_MAXPQSIZE_0_RT_OFFSET 29738 +#define QM_REG_MAXPQSIZE_1_RT_OFFSET 29739 +#define QM_REG_MAXPQSIZE_2_RT_OFFSET 29740 +#define QM_REG_MAXPQSIZETXSEL_0_RT_OFFSET 29741 +#define QM_REG_MAXPQSIZETXSEL_1_RT_OFFSET 29742 +#define QM_REG_MAXPQSIZETXSEL_2_RT_OFFSET 29743 +#define QM_REG_MAXPQSIZETXSEL_3_RT_OFFSET 29744 +#define QM_REG_MAXPQSIZETXSEL_4_RT_OFFSET 29745 +#define QM_REG_MAXPQSIZETXSEL_5_RT_OFFSET 29746 +#define QM_REG_MAXPQSIZETXSEL_6_RT_OFFSET 29747 +#define QM_REG_MAXPQSIZETXSEL_7_RT_OFFSET 29748 +#define QM_REG_MAXPQSIZETXSEL_8_RT_OFFSET 29749 +#define QM_REG_MAXPQSIZETXSEL_9_RT_OFFSET 29750 +#define QM_REG_MAXPQSIZETXSEL_10_RT_OFFSET 29751 +#define QM_REG_MAXPQSIZETXSEL_11_RT_OFFSET 29752 +#define QM_REG_MAXPQSIZETXSEL_12_RT_OFFSET 29753 +#define QM_REG_MAXPQSIZETXSEL_13_RT_OFFSET 29754 +#define QM_REG_MAXPQSIZETXSEL_14_RT_OFFSET 29755 +#define QM_REG_MAXPQSIZETXSEL_15_RT_OFFSET 29756 +#define QM_REG_MAXPQSIZETXSEL_16_RT_OFFSET 29757 +#define QM_REG_MAXPQSIZETXSEL_17_RT_OFFSET 29758 +#define QM_REG_MAXPQSIZETXSEL_18_RT_OFFSET 29759 +#define QM_REG_MAXPQSIZETXSEL_19_RT_OFFSET 29760 +#define QM_REG_MAXPQSIZETXSEL_20_RT_OFFSET 29761 +#define QM_REG_MAXPQSIZETXSEL_21_RT_OFFSET 29762 +#define QM_REG_MAXPQSIZETXSEL_22_RT_OFFSET 29763 +#define QM_REG_MAXPQSIZETXSEL_23_RT_OFFSET 29764 +#define QM_REG_MAXPQSIZETXSEL_24_RT_OFFSET 29765 +#define QM_REG_MAXPQSIZETXSEL_25_RT_OFFSET 29766 +#define QM_REG_MAXPQSIZETXSEL_26_RT_OFFSET 29767 +#define QM_REG_MAXPQSIZETXSEL_27_RT_OFFSET 29768 +#define QM_REG_MAXPQSIZETXSEL_28_RT_OFFSET 29769 +#define QM_REG_MAXPQSIZETXSEL_29_RT_OFFSET 29770 +#define QM_REG_MAXPQSIZETXSEL_30_RT_OFFSET 29771 +#define QM_REG_MAXPQSIZETXSEL_31_RT_OFFSET 29772 +#define QM_REG_MAXPQSIZETXSEL_32_RT_OFFSET 29773 +#define QM_REG_MAXPQSIZETXSEL_33_RT_OFFSET 29774 +#define QM_REG_MAXPQSIZETXSEL_34_RT_OFFSET 29775 +#define QM_REG_MAXPQSIZETXSEL_35_RT_OFFSET 29776 +#define QM_REG_MAXPQSIZETXSEL_36_RT_OFFSET 29777 +#define QM_REG_MAXPQSIZETXSEL_37_RT_OFFSET 29778 +#define QM_REG_MAXPQSIZETXSEL_38_RT_OFFSET 29779 +#define QM_REG_MAXPQSIZETXSEL_39_RT_OFFSET 29780 +#define QM_REG_MAXPQSIZETXSEL_40_RT_OFFSET 29781 +#define QM_REG_MAXPQSIZETXSEL_41_RT_OFFSET 29782 +#define QM_REG_MAXPQSIZETXSEL_42_RT_OFFSET 29783 +#define QM_REG_MAXPQSIZETXSEL_43_RT_OFFSET 29784 +#define QM_REG_MAXPQSIZETXSEL_44_RT_OFFSET 29785 +#define QM_REG_MAXPQSIZETXSEL_45_RT_OFFSET 29786 +#define QM_REG_MAXPQSIZETXSEL_46_RT_OFFSET 29787 +#define QM_REG_MAXPQSIZETXSEL_47_RT_OFFSET 29788 +#define QM_REG_MAXPQSIZETXSEL_48_RT_OFFSET 29789 +#define QM_REG_MAXPQSIZETXSEL_49_RT_OFFSET 29790 +#define QM_REG_MAXPQSIZETXSEL_50_RT_OFFSET 29791 +#define QM_REG_MAXPQSIZETXSEL_51_RT_OFFSET 29792 +#define QM_REG_MAXPQSIZETXSEL_52_RT_OFFSET 29793 +#define QM_REG_MAXPQSIZETXSEL_53_RT_OFFSET 29794 +#define QM_REG_MAXPQSIZETXSEL_54_RT_OFFSET 29795 +#define QM_REG_MAXPQSIZETXSEL_55_RT_OFFSET 29796 +#define QM_REG_MAXPQSIZETXSEL_56_RT_OFFSET 29797 +#define QM_REG_MAXPQSIZETXSEL_57_RT_OFFSET 29798 +#define QM_REG_MAXPQSIZETXSEL_58_RT_OFFSET 29799 +#define QM_REG_MAXPQSIZETXSEL_59_RT_OFFSET 29800 +#define QM_REG_MAXPQSIZETXSEL_60_RT_OFFSET 29801 +#define QM_REG_MAXPQSIZETXSEL_61_RT_OFFSET 29802 +#define QM_REG_MAXPQSIZETXSEL_62_RT_OFFSET 29803 +#define QM_REG_MAXPQSIZETXSEL_63_RT_OFFSET 29804 +#define QM_REG_BASEADDROTHERPQ_RT_OFFSET 29805 +#define QM_REG_BASEADDROTHERPQ_RT_SIZE 128 +#define QM_REG_AFULLQMBYPTHRPFWFQ_RT_OFFSET 29933 +#define QM_REG_AFULLQMBYPTHRVPWFQ_RT_OFFSET 29934 +#define QM_REG_AFULLQMBYPTHRPFRL_RT_OFFSET 29935 +#define QM_REG_AFULLQMBYPTHRGLBLRL_RT_OFFSET 29936 +#define QM_REG_AFULLOPRTNSTCCRDMASK_RT_OFFSET 29937 +#define QM_REG_WRROTHERPQGRP_0_RT_OFFSET 29938 +#define QM_REG_WRROTHERPQGRP_1_RT_OFFSET 29939 +#define QM_REG_WRROTHERPQGRP_2_RT_OFFSET 29940 +#define QM_REG_WRROTHERPQGRP_3_RT_OFFSET 29941 +#define QM_REG_WRROTHERPQGRP_4_RT_OFFSET 29942 +#define QM_REG_WRROTHERPQGRP_5_RT_OFFSET 29943 +#define QM_REG_WRROTHERPQGRP_6_RT_OFFSET 29944 +#define QM_REG_WRROTHERPQGRP_7_RT_OFFSET 29945 +#define QM_REG_WRROTHERPQGRP_8_RT_OFFSET 29946 +#define QM_REG_WRROTHERPQGRP_9_RT_OFFSET 29947 +#define QM_REG_WRROTHERPQGRP_10_RT_OFFSET 29948 +#define QM_REG_WRROTHERPQGRP_11_RT_OFFSET 29949 +#define QM_REG_WRROTHERPQGRP_12_RT_OFFSET 29950 +#define QM_REG_WRROTHERPQGRP_13_RT_OFFSET 29951 +#define QM_REG_WRROTHERPQGRP_14_RT_OFFSET 29952 +#define QM_REG_WRROTHERPQGRP_15_RT_OFFSET 29953 +#define QM_REG_WRROTHERGRPWEIGHT_0_RT_OFFSET 29954 +#define QM_REG_WRROTHERGRPWEIGHT_1_RT_OFFSET 29955 +#define QM_REG_WRROTHERGRPWEIGHT_2_RT_OFFSET 29956 +#define QM_REG_WRROTHERGRPWEIGHT_3_RT_OFFSET 29957 +#define QM_REG_WRRTXGRPWEIGHT_0_RT_OFFSET 29958 +#define QM_REG_WRRTXGRPWEIGHT_1_RT_OFFSET 29959 +#define QM_REG_PQTX2PF_0_RT_OFFSET 29960 +#define QM_REG_PQTX2PF_1_RT_OFFSET 29961 +#define QM_REG_PQTX2PF_2_RT_OFFSET 29962 +#define QM_REG_PQTX2PF_3_RT_OFFSET 29963 +#define QM_REG_PQTX2PF_4_RT_OFFSET 29964 +#define QM_REG_PQTX2PF_5_RT_OFFSET 29965 +#define QM_REG_PQTX2PF_6_RT_OFFSET 29966 +#define QM_REG_PQTX2PF_7_RT_OFFSET 29967 +#define QM_REG_PQTX2PF_8_RT_OFFSET 29968 +#define QM_REG_PQTX2PF_9_RT_OFFSET 29969 +#define QM_REG_PQTX2PF_10_RT_OFFSET 29970 +#define QM_REG_PQTX2PF_11_RT_OFFSET 29971 +#define QM_REG_PQTX2PF_12_RT_OFFSET 29972 +#define QM_REG_PQTX2PF_13_RT_OFFSET 29973 +#define QM_REG_PQTX2PF_14_RT_OFFSET 29974 +#define QM_REG_PQTX2PF_15_RT_OFFSET 29975 +#define QM_REG_PQTX2PF_16_RT_OFFSET 29976 +#define QM_REG_PQTX2PF_17_RT_OFFSET 29977 +#define QM_REG_PQTX2PF_18_RT_OFFSET 29978 +#define QM_REG_PQTX2PF_19_RT_OFFSET 29979 +#define QM_REG_PQTX2PF_20_RT_OFFSET 29980 +#define QM_REG_PQTX2PF_21_RT_OFFSET 29981 +#define QM_REG_PQTX2PF_22_RT_OFFSET 29982 +#define QM_REG_PQTX2PF_23_RT_OFFSET 29983 +#define QM_REG_PQTX2PF_24_RT_OFFSET 29984 +#define QM_REG_PQTX2PF_25_RT_OFFSET 29985 +#define QM_REG_PQTX2PF_26_RT_OFFSET 29986 +#define QM_REG_PQTX2PF_27_RT_OFFSET 29987 +#define QM_REG_PQTX2PF_28_RT_OFFSET 29988 +#define QM_REG_PQTX2PF_29_RT_OFFSET 29989 +#define QM_REG_PQTX2PF_30_RT_OFFSET 29990 +#define QM_REG_PQTX2PF_31_RT_OFFSET 29991 +#define QM_REG_PQTX2PF_32_RT_OFFSET 29992 +#define QM_REG_PQTX2PF_33_RT_OFFSET 29993 +#define QM_REG_PQTX2PF_34_RT_OFFSET 29994 +#define QM_REG_PQTX2PF_35_RT_OFFSET 29995 +#define QM_REG_PQTX2PF_36_RT_OFFSET 29996 +#define QM_REG_PQTX2PF_37_RT_OFFSET 29997 +#define QM_REG_PQTX2PF_38_RT_OFFSET 29998 +#define QM_REG_PQTX2PF_39_RT_OFFSET 29999 +#define QM_REG_PQTX2PF_40_RT_OFFSET 30000 +#define QM_REG_PQTX2PF_41_RT_OFFSET 30001 +#define QM_REG_PQTX2PF_42_RT_OFFSET 30002 +#define QM_REG_PQTX2PF_43_RT_OFFSET 30003 +#define QM_REG_PQTX2PF_44_RT_OFFSET 30004 +#define QM_REG_PQTX2PF_45_RT_OFFSET 30005 +#define QM_REG_PQTX2PF_46_RT_OFFSET 30006 +#define QM_REG_PQTX2PF_47_RT_OFFSET 30007 +#define QM_REG_PQTX2PF_48_RT_OFFSET 30008 +#define QM_REG_PQTX2PF_49_RT_OFFSET 30009 +#define QM_REG_PQTX2PF_50_RT_OFFSET 30010 +#define QM_REG_PQTX2PF_51_RT_OFFSET 30011 +#define QM_REG_PQTX2PF_52_RT_OFFSET 30012 +#define QM_REG_PQTX2PF_53_RT_OFFSET 30013 +#define QM_REG_PQTX2PF_54_RT_OFFSET 30014 +#define QM_REG_PQTX2PF_55_RT_OFFSET 30015 +#define QM_REG_PQTX2PF_56_RT_OFFSET 30016 +#define QM_REG_PQTX2PF_57_RT_OFFSET 30017 +#define QM_REG_PQTX2PF_58_RT_OFFSET 30018 +#define QM_REG_PQTX2PF_59_RT_OFFSET 30019 +#define QM_REG_PQTX2PF_60_RT_OFFSET 30020 +#define QM_REG_PQTX2PF_61_RT_OFFSET 30021 +#define QM_REG_PQTX2PF_62_RT_OFFSET 30022 +#define QM_REG_PQTX2PF_63_RT_OFFSET 30023 +#define QM_REG_PQOTHER2PF_0_RT_OFFSET 30024 +#define QM_REG_PQOTHER2PF_1_RT_OFFSET 30025 +#define QM_REG_PQOTHER2PF_2_RT_OFFSET 30026 +#define QM_REG_PQOTHER2PF_3_RT_OFFSET 30027 +#define QM_REG_PQOTHER2PF_4_RT_OFFSET 30028 +#define QM_REG_PQOTHER2PF_5_RT_OFFSET 30029 +#define QM_REG_PQOTHER2PF_6_RT_OFFSET 30030 +#define QM_REG_PQOTHER2PF_7_RT_OFFSET 30031 +#define QM_REG_PQOTHER2PF_8_RT_OFFSET 30032 +#define QM_REG_PQOTHER2PF_9_RT_OFFSET 30033 +#define QM_REG_PQOTHER2PF_10_RT_OFFSET 30034 +#define QM_REG_PQOTHER2PF_11_RT_OFFSET 30035 +#define QM_REG_PQOTHER2PF_12_RT_OFFSET 30036 +#define QM_REG_PQOTHER2PF_13_RT_OFFSET 30037 +#define QM_REG_PQOTHER2PF_14_RT_OFFSET 30038 +#define QM_REG_PQOTHER2PF_15_RT_OFFSET 30039 +#define QM_REG_RLGLBLPERIOD_0_RT_OFFSET 30040 +#define QM_REG_RLGLBLPERIOD_1_RT_OFFSET 30041 +#define QM_REG_RLGLBLPERIODTIMER_0_RT_OFFSET 30042 +#define QM_REG_RLGLBLPERIODTIMER_1_RT_OFFSET 30043 +#define QM_REG_RLGLBLPERIODSEL_0_RT_OFFSET 30044 +#define QM_REG_RLGLBLPERIODSEL_1_RT_OFFSET 30045 +#define QM_REG_RLGLBLPERIODSEL_2_RT_OFFSET 30046 +#define QM_REG_RLGLBLPERIODSEL_3_RT_OFFSET 30047 +#define QM_REG_RLGLBLPERIODSEL_4_RT_OFFSET 30048 +#define QM_REG_RLGLBLPERIODSEL_5_RT_OFFSET 30049 +#define QM_REG_RLGLBLPERIODSEL_6_RT_OFFSET 30050 +#define QM_REG_RLGLBLPERIODSEL_7_RT_OFFSET 30051 +#define QM_REG_RLGLBLINCVAL_RT_OFFSET 30052 #define QM_REG_RLGLBLINCVAL_RT_SIZE 256 -#define QM_REG_RLGLBLUPPERBOUND_RT_OFFSET 30310 +#define QM_REG_RLGLBLUPPERBOUND_RT_OFFSET 30308 #define QM_REG_RLGLBLUPPERBOUND_RT_SIZE 256 -#define QM_REG_RLGLBLCRD_RT_OFFSET 30566 +#define QM_REG_RLGLBLCRD_RT_OFFSET 30564 #define QM_REG_RLGLBLCRD_RT_SIZE 256 -#define QM_REG_RLGLBLENABLE_RT_OFFSET 30822 -#define QM_REG_RLPFPERIOD_RT_OFFSET 30823 -#define QM_REG_RLPFPERIODTIMER_RT_OFFSET 30824 -#define QM_REG_RLPFINCVAL_RT_OFFSET 30825 +#define QM_REG_RLGLBLENABLE_RT_OFFSET 30820 +#define QM_REG_RLPFPERIOD_RT_OFFSET 30821 +#define QM_REG_RLPFPERIODTIMER_RT_OFFSET 30822 +#define QM_REG_RLPFINCVAL_RT_OFFSET 30823 #define QM_REG_RLPFINCVAL_RT_SIZE 16 -#define QM_REG_RLPFUPPERBOUND_RT_OFFSET 30841 +#define QM_REG_RLPFUPPERBOUND_RT_OFFSET 30839 #define QM_REG_RLPFUPPERBOUND_RT_SIZE 16 -#define QM_REG_RLPFCRD_RT_OFFSET 30857 +#define QM_REG_RLPFCRD_RT_OFFSET 30855 #define QM_REG_RLPFCRD_RT_SIZE 16 -#define QM_REG_RLPFENABLE_RT_OFFSET 30873 -#define QM_REG_RLPFVOQENABLE_RT_OFFSET 30874 -#define QM_REG_WFQPFWEIGHT_RT_OFFSET 30875 +#define QM_REG_RLPFENABLE_RT_OFFSET 30871 +#define QM_REG_RLPFVOQENABLE_RT_OFFSET 30872 +#define QM_REG_WFQPFWEIGHT_RT_OFFSET 30873 #define QM_REG_WFQPFWEIGHT_RT_SIZE 16 -#define QM_REG_WFQPFUPPERBOUND_RT_OFFSET 30891 +#define QM_REG_WFQPFUPPERBOUND_RT_OFFSET 30889 #define QM_REG_WFQPFUPPERBOUND_RT_SIZE 16 -#define QM_REG_WFQPFCRD_RT_OFFSET 30907 +#define QM_REG_WFQPFCRD_RT_OFFSET 30905 #define QM_REG_WFQPFCRD_RT_SIZE 256 -#define QM_REG_WFQPFENABLE_RT_OFFSET 31163 -#define QM_REG_WFQVPENABLE_RT_OFFSET 31164 -#define QM_REG_BASEADDRTXPQ_RT_OFFSET 31165 +#define QM_REG_WFQPFENABLE_RT_OFFSET 31161 +#define QM_REG_WFQVPENABLE_RT_OFFSET 31162 +#define QM_REG_BASEADDRTXPQ_RT_OFFSET 31163 #define QM_REG_BASEADDRTXPQ_RT_SIZE 512 -#define QM_REG_TXPQMAP_RT_OFFSET 31677 +#define QM_REG_TXPQMAP_RT_OFFSET 31675 #define QM_REG_TXPQMAP_RT_SIZE 512 -#define QM_REG_WFQVPWEIGHT_RT_OFFSET 32189 +#define QM_REG_WFQVPWEIGHT_RT_OFFSET 32187 #define QM_REG_WFQVPWEIGHT_RT_SIZE 512 -#define QM_REG_WFQVPCRD_RT_OFFSET 32701 +#define QM_REG_WFQVPCRD_RT_OFFSET 32699 #define QM_REG_WFQVPCRD_RT_SIZE 512 -#define QM_REG_WFQVPMAP_RT_OFFSET 33213 +#define QM_REG_WFQVPMAP_RT_OFFSET 33211 #define QM_REG_WFQVPMAP_RT_SIZE 512 -#define QM_REG_WFQPFCRD_MSB_RT_OFFSET 33725 +#define QM_REG_WFQPFCRD_MSB_RT_OFFSET 33723 #define QM_REG_WFQPFCRD_MSB_RT_SIZE 320 -#define QM_REG_VOQCRDLINE_RT_OFFSET 34045 +#define QM_REG_VOQCRDLINE_RT_OFFSET 34043 #define QM_REG_VOQCRDLINE_RT_SIZE 36 -#define QM_REG_VOQINITCRDLINE_RT_OFFSET 34081 +#define QM_REG_VOQINITCRDLINE_RT_OFFSET 34079 #define QM_REG_VOQINITCRDLINE_RT_SIZE 36 -#define NIG_REG_TAG_ETHERTYPE_0_RT_OFFSET 34117 -#define NIG_REG_OUTER_TAG_VALUE_LIST0_RT_OFFSET 34118 -#define NIG_REG_OUTER_TAG_VALUE_LIST1_RT_OFFSET 34119 -#define NIG_REG_OUTER_TAG_VALUE_LIST2_RT_OFFSET 34120 -#define NIG_REG_OUTER_TAG_VALUE_LIST3_RT_OFFSET 34121 -#define NIG_REG_OUTER_TAG_VALUE_MASK_RT_OFFSET 34122 -#define NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET 34123 -#define NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET 34124 +#define NIG_REG_TAG_ETHERTYPE_0_RT_OFFSET 34115 +#define NIG_REG_OUTER_TAG_VALUE_LIST0_RT_OFFSET 34116 +#define NIG_REG_OUTER_TAG_VALUE_LIST1_RT_OFFSET 34117 +#define NIG_REG_OUTER_TAG_VALUE_LIST2_RT_OFFSET 34118 +#define NIG_REG_OUTER_TAG_VALUE_LIST3_RT_OFFSET 34119 +#define NIG_REG_OUTER_TAG_VALUE_MASK_RT_OFFSET 34120 +#define NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET 34121 +#define NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET 34122 #define NIG_REG_LLH_FUNC_TAG_EN_RT_SIZE 4 -#define NIG_REG_LLH_FUNC_TAG_HDR_SEL_RT_OFFSET 34128 +#define NIG_REG_LLH_FUNC_TAG_HDR_SEL_RT_OFFSET 34126 #define NIG_REG_LLH_FUNC_TAG_HDR_SEL_RT_SIZE 4 -#define NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET 34132 +#define NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET 34130 #define NIG_REG_LLH_FUNC_TAG_VALUE_RT_SIZE 4 -#define NIG_REG_LLH_FUNC_NO_TAG_RT_OFFSET 34136 -#define NIG_REG_LLH_FUNC_FILTER_VALUE_RT_OFFSET 34137 +#define NIG_REG_LLH_FUNC_NO_TAG_RT_OFFSET 34134 +#define NIG_REG_LLH_FUNC_FILTER_VALUE_RT_OFFSET 34135 #define NIG_REG_LLH_FUNC_FILTER_VALUE_RT_SIZE 32 -#define NIG_REG_LLH_FUNC_FILTER_EN_RT_OFFSET 34169 +#define NIG_REG_LLH_FUNC_FILTER_EN_RT_OFFSET 34167 #define NIG_REG_LLH_FUNC_FILTER_EN_RT_SIZE 16 -#define NIG_REG_LLH_FUNC_FILTER_MODE_RT_OFFSET 34185 +#define NIG_REG_LLH_FUNC_FILTER_MODE_RT_OFFSET 34183 #define NIG_REG_LLH_FUNC_FILTER_MODE_RT_SIZE 16 -#define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_RT_OFFSET 34201 +#define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_RT_OFFSET 34199 #define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_RT_SIZE 16 -#define NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_OFFSET 34217 +#define NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_OFFSET 34215 #define NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_SIZE 16 -#define NIG_REG_TX_EDPM_CTRL_RT_OFFSET 34233 -#define NIG_REG_ROCE_DUPLICATE_TO_HOST_RT_OFFSET 34234 -#define CDU_REG_CID_ADDR_PARAMS_RT_OFFSET 34235 -#define CDU_REG_SEGMENT0_PARAMS_RT_OFFSET 34236 -#define CDU_REG_SEGMENT1_PARAMS_RT_OFFSET 34237 -#define CDU_REG_PF_SEG0_TYPE_OFFSET_RT_OFFSET 34238 -#define CDU_REG_PF_SEG1_TYPE_OFFSET_RT_OFFSET 34239 -#define CDU_REG_PF_SEG2_TYPE_OFFSET_RT_OFFSET 34240 -#define CDU_REG_PF_SEG3_TYPE_OFFSET_RT_OFFSET 34241 -#define CDU_REG_PF_FL_SEG0_TYPE_OFFSET_RT_OFFSET 34242 -#define CDU_REG_PF_FL_SEG1_TYPE_OFFSET_RT_OFFSET 34243 -#define CDU_REG_PF_FL_SEG2_TYPE_OFFSET_RT_OFFSET 34244 -#define CDU_REG_PF_FL_SEG3_TYPE_OFFSET_RT_OFFSET 34245 -#define CDU_REG_VF_SEG_TYPE_OFFSET_RT_OFFSET 34246 -#define CDU_REG_VF_FL_SEG_TYPE_OFFSET_RT_OFFSET 34247 -#define PBF_REG_TAG_ETHERTYPE_0_RT_OFFSET 34248 -#define PBF_REG_BTB_SHARED_AREA_SIZE_RT_OFFSET 34249 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ0_RT_OFFSET 34250 -#define PBF_REG_BTB_GUARANTEED_VOQ0_RT_OFFSET 34251 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ0_RT_OFFSET 34252 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ1_RT_OFFSET 34253 -#define PBF_REG_BTB_GUARANTEED_VOQ1_RT_OFFSET 34254 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ1_RT_OFFSET 34255 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ2_RT_OFFSET 34256 -#define PBF_REG_BTB_GUARANTEED_VOQ2_RT_OFFSET 34257 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ2_RT_OFFSET 34258 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ3_RT_OFFSET 34259 -#define PBF_REG_BTB_GUARANTEED_VOQ3_RT_OFFSET 34260 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ3_RT_OFFSET 34261 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ4_RT_OFFSET 34262 -#define PBF_REG_BTB_GUARANTEED_VOQ4_RT_OFFSET 34263 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ4_RT_OFFSET 34264 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ5_RT_OFFSET 34265 -#define PBF_REG_BTB_GUARANTEED_VOQ5_RT_OFFSET 34266 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ5_RT_OFFSET 34267 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ6_RT_OFFSET 34268 -#define PBF_REG_BTB_GUARANTEED_VOQ6_RT_OFFSET 34269 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ6_RT_OFFSET 34270 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ7_RT_OFFSET 34271 -#define PBF_REG_BTB_GUARANTEED_VOQ7_RT_OFFSET 34272 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ7_RT_OFFSET 34273 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ8_RT_OFFSET 34274 -#define PBF_REG_BTB_GUARANTEED_VOQ8_RT_OFFSET 34275 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ8_RT_OFFSET 34276 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ9_RT_OFFSET 34277 -#define PBF_REG_BTB_GUARANTEED_VOQ9_RT_OFFSET 34278 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ9_RT_OFFSET 34279 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ10_RT_OFFSET 34280 -#define PBF_REG_BTB_GUARANTEED_VOQ10_RT_OFFSET 34281 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ10_RT_OFFSET 34282 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ11_RT_OFFSET 34283 -#define PBF_REG_BTB_GUARANTEED_VOQ11_RT_OFFSET 34284 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ11_RT_OFFSET 34285 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ12_RT_OFFSET 34286 -#define PBF_REG_BTB_GUARANTEED_VOQ12_RT_OFFSET 34287 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ12_RT_OFFSET 34288 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ13_RT_OFFSET 34289 -#define PBF_REG_BTB_GUARANTEED_VOQ13_RT_OFFSET 34290 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ13_RT_OFFSET 34291 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ14_RT_OFFSET 34292 -#define PBF_REG_BTB_GUARANTEED_VOQ14_RT_OFFSET 34293 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ14_RT_OFFSET 34294 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ15_RT_OFFSET 34295 -#define PBF_REG_BTB_GUARANTEED_VOQ15_RT_OFFSET 34296 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ15_RT_OFFSET 34297 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ16_RT_OFFSET 34298 -#define PBF_REG_BTB_GUARANTEED_VOQ16_RT_OFFSET 34299 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ16_RT_OFFSET 34300 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ17_RT_OFFSET 34301 -#define PBF_REG_BTB_GUARANTEED_VOQ17_RT_OFFSET 34302 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ17_RT_OFFSET 34303 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ18_RT_OFFSET 34304 -#define PBF_REG_BTB_GUARANTEED_VOQ18_RT_OFFSET 34305 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ18_RT_OFFSET 34306 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ19_RT_OFFSET 34307 -#define PBF_REG_BTB_GUARANTEED_VOQ19_RT_OFFSET 34308 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ19_RT_OFFSET 34309 -#define XCM_REG_CON_PHY_Q3_RT_OFFSET 34310 +#define NIG_REG_TX_EDPM_CTRL_RT_OFFSET 34231 +#define NIG_REG_ROCE_DUPLICATE_TO_HOST_RT_OFFSET 34232 +#define CDU_REG_CID_ADDR_PARAMS_RT_OFFSET 34233 +#define CDU_REG_SEGMENT0_PARAMS_RT_OFFSET 34234 +#define CDU_REG_SEGMENT1_PARAMS_RT_OFFSET 34235 +#define CDU_REG_PF_SEG0_TYPE_OFFSET_RT_OFFSET 34236 +#define CDU_REG_PF_SEG1_TYPE_OFFSET_RT_OFFSET 34237 +#define CDU_REG_PF_SEG2_TYPE_OFFSET_RT_OFFSET 34238 +#define CDU_REG_PF_SEG3_TYPE_OFFSET_RT_OFFSET 34239 +#define CDU_REG_PF_FL_SEG0_TYPE_OFFSET_RT_OFFSET 34240 +#define CDU_REG_PF_FL_SEG1_TYPE_OFFSET_RT_OFFSET 34241 +#define CDU_REG_PF_FL_SEG2_TYPE_OFFSET_RT_OFFSET 34242 +#define CDU_REG_PF_FL_SEG3_TYPE_OFFSET_RT_OFFSET 34243 +#define CDU_REG_VF_SEG_TYPE_OFFSET_RT_OFFSET 34244 +#define CDU_REG_VF_FL_SEG_TYPE_OFFSET_RT_OFFSET 34245 +#define PBF_REG_TAG_ETHERTYPE_0_RT_OFFSET 34246 +#define PBF_REG_BTB_SHARED_AREA_SIZE_RT_OFFSET 34247 +#define PBF_REG_YCMD_QS_NUM_LINES_VOQ0_RT_OFFSET 34248 +#define PBF_REG_BTB_GUARANTEED_VOQ0_RT_OFFSET 34249 +#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ0_RT_OFFSET 34250 +#define PBF_REG_YCMD_QS_NUM_LINES_VOQ1_RT_OFFSET 34251 +#define PBF_REG_BTB_GUARANTEED_VOQ1_RT_OFFSET 34252 +#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ1_RT_OFFSET 34253 +#define PBF_REG_YCMD_QS_NUM_LINES_VOQ2_RT_OFFSET 34254 +#define PBF_REG_BTB_GUARANTEED_VOQ2_RT_OFFSET 34255 +#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ2_RT_OFFSET 34256 +#define PBF_REG_YCMD_QS_NUM_LINES_VOQ3_RT_OFFSET 34257 +#define PBF_REG_BTB_GUARANTEED_VOQ3_RT_OFFSET 34258 +#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ3_RT_OFFSET 34259 +#define PBF_REG_YCMD_QS_NUM_LINES_VOQ4_RT_OFFSET 34260 +#define PBF_REG_BTB_GUARANTEED_VOQ4_RT_OFFSET 34261 +#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ4_RT_OFFSET 34262 +#define PBF_REG_YCMD_QS_NUM_LINES_VOQ5_RT_OFFSET 34263 +#define PBF_REG_BTB_GUARANTEED_VOQ5_RT_OFFSET 34264 +#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ5_RT_OFFSET 34265 +#define PBF_REG_YCMD_QS_NUM_LINES_VOQ6_RT_OFFSET 34266 +#define PBF_REG_BTB_GUARANTEED_VOQ6_RT_OFFSET 34267 +#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ6_RT_OFFSET 34268 +#define PBF_REG_YCMD_QS_NUM_LINES_VOQ7_RT_OFFSET 34269 +#define PBF_REG_BTB_GUARANTEED_VOQ7_RT_OFFSET 34270 +#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ7_RT_OFFSET 34271 +#define PBF_REG_YCMD_QS_NUM_LINES_VOQ8_RT_OFFSET 34272 +#define PBF_REG_BTB_GUARANTEED_VOQ8_RT_OFFSET 34273 +#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ8_RT_OFFSET 34274 +#define PBF_REG_YCMD_QS_NUM_LINES_VOQ9_RT_OFFSET 34275 +#define PBF_REG_BTB_GUARANTEED_VOQ9_RT_OFFSET 34276 +#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ9_RT_OFFSET 34277 +#define PBF_REG_YCMD_QS_NUM_LINES_VOQ10_RT_OFFSET 34278 +#define PBF_REG_BTB_GUARANTEED_VOQ10_RT_OFFSET 34279 +#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ10_RT_OFFSET 34280 +#define PBF_REG_YCMD_QS_NUM_LINES_VOQ11_RT_OFFSET 34281 +#define PBF_REG_BTB_GUARANTEED_VOQ11_RT_OFFSET 34282 +#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ11_RT_OFFSET 34283 +#define PBF_REG_YCMD_QS_NUM_LINES_VOQ12_RT_OFFSET 34284 +#define PBF_REG_BTB_GUARANTEED_VOQ12_RT_OFFSET 34285 +#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ12_RT_OFFSET 34286 +#define PBF_REG_YCMD_QS_NUM_LINES_VOQ13_RT_OFFSET 34287 +#define PBF_REG_BTB_GUARANTEED_VOQ13_RT_OFFSET 34288 +#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ13_RT_OFFSET 34289 +#define PBF_REG_YCMD_QS_NUM_LINES_VOQ14_RT_OFFSET 34290 +#define PBF_REG_BTB_GUARANTEED_VOQ14_RT_OFFSET 34291 +#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ14_RT_OFFSET 34292 +#define PBF_REG_YCMD_QS_NUM_LINES_VOQ15_RT_OFFSET 34293 +#define PBF_REG_BTB_GUARANTEED_VOQ15_RT_OFFSET 34294 +#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ15_RT_OFFSET 34295 +#define PBF_REG_YCMD_QS_NUM_LINES_VOQ16_RT_OFFSET 34296 +#define PBF_REG_BTB_GUARANTEED_VOQ16_RT_OFFSET 34297 +#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ16_RT_OFFSET 34298 +#define PBF_REG_YCMD_QS_NUM_LINES_VOQ17_RT_OFFSET 34299 +#define PBF_REG_BTB_GUARANTEED_VOQ17_RT_OFFSET 34300 +#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ17_RT_OFFSET 34301 +#define PBF_REG_YCMD_QS_NUM_LINES_VOQ18_RT_OFFSET 34302 +#define PBF_REG_BTB_GUARANTEED_VOQ18_RT_OFFSET 34303 +#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ18_RT_OFFSET 34304 +#define PBF_REG_YCMD_QS_NUM_LINES_VOQ19_RT_OFFSET 34305 +#define PBF_REG_BTB_GUARANTEED_VOQ19_RT_OFFSET 34306 +#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ19_RT_OFFSET 34307 +#define XCM_REG_CON_PHY_Q3_RT_OFFSET 34308 -#define RUNTIME_ARRAY_SIZE 34311 +#define RUNTIME_ARRAY_SIZE 34309 #endif /* __RT_DEFS_H__ */ diff --git a/drivers/net/qede/base/ecore_sp_commands.c b/drivers/net/qede/base/ecore_sp_commands.c index 8fd64d7a..d6e4b9e0 100644 --- a/drivers/net/qede/base/ecore_sp_commands.c +++ b/drivers/net/qede/base/ecore_sp_commands.c @@ -165,23 +165,19 @@ static void ecore_set_tunn_ports(struct ecore_tunnel_info *p_tun, } static void -__ecore_set_ramrod_tunnel_param(u8 *p_tunn_cls, u8 *p_enable_tx_clas, +__ecore_set_ramrod_tunnel_param(u8 *p_tunn_cls, struct ecore_tunn_update_type *tun_type) { *p_tunn_cls = tun_type->tun_cls; - - if (tun_type->b_mode_enabled) - *p_enable_tx_clas = 1; } static void -ecore_set_ramrod_tunnel_param(u8 *p_tunn_cls, u8 *p_enable_tx_clas, +ecore_set_ramrod_tunnel_param(u8 *p_tunn_cls, struct ecore_tunn_update_type *tun_type, u8 *p_update_port, __le16 *p_port, struct ecore_tunn_update_udp_port *p_udp_port) { - __ecore_set_ramrod_tunnel_param(p_tunn_cls, p_enable_tx_clas, - tun_type); + __ecore_set_ramrod_tunnel_param(p_tunn_cls, tun_type); if (p_udp_port->b_update_port) { *p_update_port = 1; *p_port = OSAL_CPU_TO_LE16(p_udp_port->port); @@ -200,33 +196,27 @@ ecore_tunn_set_pf_update_params(struct ecore_hwfn *p_hwfn, ecore_set_tunn_ports(p_tun, p_src); ecore_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_vxlan, - &p_tunn_cfg->tx_enable_vxlan, &p_tun->vxlan, &p_tunn_cfg->set_vxlan_udp_port_flg, &p_tunn_cfg->vxlan_udp_port, &p_tun->vxlan_port); ecore_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_l2geneve, - &p_tunn_cfg->tx_enable_l2geneve, &p_tun->l2_geneve, &p_tunn_cfg->set_geneve_udp_port_flg, &p_tunn_cfg->geneve_udp_port, &p_tun->geneve_port); __ecore_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_ipgeneve, - &p_tunn_cfg->tx_enable_ipgeneve, &p_tun->ip_geneve); __ecore_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_l2gre, - &p_tunn_cfg->tx_enable_l2gre, &p_tun->l2_gre); __ecore_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_ipgre, - &p_tunn_cfg->tx_enable_ipgre, &p_tun->ip_gre); p_tunn_cfg->update_rx_pf_clss = p_tun->b_update_rx_cls; - p_tunn_cfg->update_tx_pf_clss = p_tun->b_update_tx_cls; } static void ecore_set_hw_tunn_mode(struct ecore_hwfn *p_hwfn, @@ -282,29 +272,24 @@ ecore_tunn_set_pf_start_params(struct ecore_hwfn *p_hwfn, ecore_set_tunn_ports(p_tun, p_src); ecore_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_vxlan, - &p_tunn_cfg->tx_enable_vxlan, &p_tun->vxlan, &p_tunn_cfg->set_vxlan_udp_port_flg, &p_tunn_cfg->vxlan_udp_port, &p_tun->vxlan_port); ecore_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_l2geneve, - &p_tunn_cfg->tx_enable_l2geneve, &p_tun->l2_geneve, &p_tunn_cfg->set_geneve_udp_port_flg, &p_tunn_cfg->geneve_udp_port, &p_tun->geneve_port); __ecore_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_ipgeneve, - &p_tunn_cfg->tx_enable_ipgeneve, &p_tun->ip_geneve); __ecore_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_l2gre, - &p_tunn_cfg->tx_enable_l2gre, &p_tun->l2_gre); __ecore_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_ipgre, - &p_tunn_cfg->tx_enable_ipgre, &p_tun->ip_gre); } @@ -345,7 +330,7 @@ enum _ecore_status_t ecore_sp_pf_start(struct ecore_hwfn *p_hwfn, /* For easier debugging */ p_ramrod->dont_log_ramrods = 0; - p_ramrod->log_type_mask = OSAL_CPU_TO_LE16(0xf); + p_ramrod->log_type_mask = OSAL_CPU_TO_LE16(0x8f); switch (mode) { case ECORE_MF_DEFAULT: diff --git a/drivers/net/qede/base/eth_common.h b/drivers/net/qede/base/eth_common.h index 6dc969b0..45a0356d 100644 --- a/drivers/net/qede/base/eth_common.h +++ b/drivers/net/qede/base/eth_common.h @@ -79,6 +79,10 @@ /* Maximum number of buffers, used for RX packet placement */ #define ETH_RX_MAX_BUFF_PER_PKT 5 +/* Minimum number of free BDs in RX ring, that guarantee receiving of at least + * one RX packet. + */ +#define ETH_RX_BD_THRESHOLD 12 /* num of MAC/VLAN filters */ #define ETH_NUM_MAC_FILTERS 512 diff --git a/drivers/net/qede/base/mcp_public.h b/drivers/net/qede/base/mcp_public.h index fcf98477..1ad8a962 100644 --- a/drivers/net/qede/base/mcp_public.h +++ b/drivers/net/qede/base/mcp_public.h @@ -132,13 +132,28 @@ struct eth_stats { u64 r1023; /* 0x04 (Offset 0x20 ) RX 512 to 1023 byte frame counter*/ /* 0x05 (Offset 0x28 ) RX 1024 to 1518 byte frame counter */ u64 r1518; + union { + struct { /* bb */ /* 0x06 (Offset 0x30 ) RX 1519 to 1522 byte VLAN-tagged frame counter */ - u64 r1522; - u64 r2047; /* 0x07 (Offset 0x38 ) RX 1519 to 2047 byte frame counter*/ - u64 r4095; /* 0x08 (Offset 0x40 ) RX 2048 to 4095 byte frame counter*/ - u64 r9216; /* 0x09 (Offset 0x48 ) RX 4096 to 9216 byte frame counter*/ + u64 r1522; +/* 0x07 (Offset 0x38 ) RX 1519 to 2047 byte frame counter*/ + u64 r2047; +/* 0x08 (Offset 0x40 ) RX 2048 to 4095 byte frame counter*/ + u64 r4095; +/* 0x09 (Offset 0x48 ) RX 4096 to 9216 byte frame counter*/ + u64 r9216; /* 0x0A (Offset 0x50 ) RX 9217 to 16383 byte frame counter */ - u64 r16383; + u64 r16383; + } bb0; + struct { /* ah */ + u64 unused1; +/* 0x07 (Offset 0x38 ) RX 1519 to max byte frame counter*/ + u64 r1519_to_max; + u64 unused2; + u64 unused3; + u64 unused4; + } ah0; + } u0; u64 rfcs; /* 0x0F (Offset 0x58 ) RX FCS error frame counter*/ u64 rxcf; /* 0x10 (Offset 0x60 ) RX control frame counter*/ u64 rxpf; /* 0x11 (Offset 0x68 ) RX pause frame counter*/ @@ -156,19 +171,40 @@ struct eth_stats { u64 t1023; /* 0x44 (Offset 0xc8 ) TX 512 to 1023 byte frame counter*/ /* 0x45 (Offset 0xd0 ) TX 1024 to 1518 byte frame counter */ u64 t1518; + union { + struct { /* bb */ /* 0x47 (Offset 0xd8 ) TX 1519 to 2047 byte frame counter */ - u64 t2047; + u64 t2047; /* 0x48 (Offset 0xe0 ) TX 2048 to 4095 byte frame counter */ - u64 t4095; + u64 t4095; /* 0x49 (Offset 0xe8 ) TX 4096 to 9216 byte frame counter */ - u64 t9216; + u64 t9216; /* 0x4A (Offset 0xf0 ) TX 9217 to 16383 byte frame counter */ - u64 t16383; + u64 t16383; + } bb1; + struct { /* ah */ +/* 0x47 (Offset 0xd8 ) TX 1519 to max byte frame counter */ + u64 t1519_to_max; + u64 unused6; + u64 unused7; + u64 unused8; + } ah1; + } u1; u64 txpf; /* 0x50 (Offset 0xf8 ) TX pause frame counter */ u64 txpp; /* 0x51 (Offset 0x100) TX PFC frame counter */ /* 0x6C (Offset 0x108) Transmit Logical Type LLFC message counter */ - u64 tlpiec; - u64 tncl; /* 0x6E (Offset 0x110) Transmit Total Collision Counter */ + union { + struct { /* bb */ +/* 0x6C (Offset 0x108) Transmit Logical Type LLFC message counter */ + u64 tlpiec; +/* 0x6E (Offset 0x110) Transmit Total Collision Counter */ + u64 tncl; + } bb2; + struct { /* ah */ + u64 unused9; + u64 unused10; + } ah2; + } u2; u64 rbyte; /* 0x3d (Offset 0x118) RX byte counter */ u64 rxuca; /* 0x0c (Offset 0x120) RX UC frame counter */ u64 rxmca; /* 0x0d (Offset 0x128) RX MC frame counter */ diff --git a/drivers/net/qede/base/reg_addr.h b/drivers/net/qede/base/reg_addr.h index f9920f37..60286545 100644 --- a/drivers/net/qede/base/reg_addr.h +++ b/drivers/net/qede/base/reg_addr.h @@ -1200,3 +1200,8 @@ #define PGLUE_B_REG_VF_BAR0_SIZE_K2_E5 0x2aaeb4UL #define PRS_REG_OUTPUT_FORMAT_4_0_BB_K2 0x1f099cUL + +#define NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 0x501a00UL +#define NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 0x501a80UL +#define NIG_REG_LLH_FUNC_FILTER_MODE_BB_K2 0x501ac0UL +#define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_BB_K2 0x501b00UL |