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-rw-r--r--drivers/crypto/aesni_gcm/aesni_gcm_pmd.c9
-rw-r--r--drivers/crypto/aesni_gcm/aesni_gcm_pmd_private.h6
-rw-r--r--drivers/crypto/aesni_mb/rte_aesni_mb_pmd.c9
-rw-r--r--drivers/crypto/aesni_mb/rte_aesni_mb_pmd_private.h2
-rw-r--r--drivers/crypto/kasumi/rte_kasumi_pmd.c18
-rw-r--r--drivers/crypto/kasumi/rte_kasumi_pmd_ops.c4
-rw-r--r--drivers/crypto/kasumi/rte_kasumi_pmd_private.h6
-rw-r--r--drivers/crypto/null/null_crypto_pmd.c9
-rw-r--r--drivers/crypto/null/null_crypto_pmd_private.h6
-rw-r--r--drivers/crypto/qat/qat_adf/qat_algs.h3
-rw-r--r--drivers/crypto/qat/qat_adf/qat_algs_build_desc.c10
-rw-r--r--drivers/crypto/qat/qat_crypto.c6
-rw-r--r--drivers/crypto/qat/rte_qat_cryptodev.c5
-rw-r--r--drivers/crypto/snow3g/rte_snow3g_pmd.c9
-rw-r--r--drivers/crypto/snow3g/rte_snow3g_pmd_private.h6
-rw-r--r--drivers/net/af_packet/rte_eth_af_packet.c9
-rw-r--r--drivers/net/bnx2x/Makefile2
-rw-r--r--drivers/net/bnx2x/bnx2x.c9
-rw-r--r--drivers/net/bnx2x/bnx2x.h8
-rw-r--r--drivers/net/bnx2x/bnx2x_ethdev.c113
-rw-r--r--drivers/net/bnx2x/bnx2x_vfpf.c9
-rw-r--r--drivers/net/bnx2x/bnx2x_vfpf.h2
-rw-r--r--drivers/net/bnxt/bnxt_ethdev.c31
-rw-r--r--drivers/net/bnxt/bnxt_hwrm.c3
-rw-r--r--drivers/net/bonding/rte_eth_bond_8023ad.c12
-rw-r--r--drivers/net/bonding/rte_eth_bond_8023ad.h4
-rw-r--r--drivers/net/bonding/rte_eth_bond_pmd.c14
-rw-r--r--drivers/net/cxgbe/cxgbe_ethdev.c19
-rw-r--r--drivers/net/e1000/e1000_ethdev.h2
-rw-r--r--drivers/net/e1000/em_ethdev.c40
-rw-r--r--drivers/net/e1000/igb_ethdev.c20
-rw-r--r--drivers/net/ena/base/ena_com.c254
-rw-r--r--drivers/net/ena/base/ena_com.h82
-rw-r--r--drivers/net/ena/base/ena_defs/ena_admin_defs.h107
-rw-r--r--drivers/net/ena/base/ena_defs/ena_eth_io_defs.h436
-rw-r--r--drivers/net/ena/base/ena_defs/ena_gen_info.h4
-rw-r--r--drivers/net/ena/base/ena_eth_com.c32
-rw-r--r--drivers/net/ena/base/ena_eth_com.h14
-rw-r--r--drivers/net/ena/base/ena_plat_dpdk.h42
-rw-r--r--drivers/net/ena/ena_ethdev.c316
-rw-r--r--drivers/net/ena/ena_ethdev.h39
-rw-r--r--drivers/net/enic/base/vnic_wq.c2
-rw-r--r--drivers/net/enic/enic.h18
-rw-r--r--drivers/net/enic/enic_ethdev.c20
-rw-r--r--drivers/net/enic/enic_main.c21
-rw-r--r--drivers/net/enic/enic_res.c12
-rw-r--r--drivers/net/enic/enic_rxtx.c2
-rw-r--r--drivers/net/fm10k/fm10k_ethdev.c9
-rw-r--r--drivers/net/fm10k/fm10k_rxtx.c8
-rw-r--r--drivers/net/i40e/i40e_ethdev.c101
-rw-r--r--drivers/net/i40e/i40e_ethdev_vf.c19
-rw-r--r--drivers/net/ixgbe/ixgbe_ethdev.c20
-rw-r--r--drivers/net/ixgbe/ixgbe_rxtx_vec_sse.c4
-rw-r--r--drivers/net/mlx4/mlx4.c92
-rw-r--r--drivers/net/mlx5/mlx5.c4
-rw-r--r--drivers/net/mlx5/mlx5_ethdev.c4
-rw-r--r--drivers/net/mlx5/mlx5_rxtx.c5
-rw-r--r--drivers/net/mpipe/mpipe_tilegx.c6
-rw-r--r--drivers/net/nfp/nfp_net.c3
-rw-r--r--drivers/net/null/rte_eth_null.c6
-rw-r--r--drivers/net/pcap/rte_eth_pcap.c9
-rw-r--r--drivers/net/qede/qede_ethdev.c210
-rw-r--r--drivers/net/ring/rte_eth_ring.c5
-rw-r--r--drivers/net/szedata2/rte_eth_szedata2.c6
-rw-r--r--drivers/net/thunderx/base/nicvf_hw_defs.h3
-rw-r--r--drivers/net/thunderx/nicvf_ethdev.c24
-rw-r--r--drivers/net/thunderx/nicvf_ethdev.h1
-rw-r--r--drivers/net/vhost/rte_eth_vhost.c16
-rw-r--r--drivers/net/virtio/virtio_ethdev.c12
-rw-r--r--drivers/net/virtio/virtio_rxtx_simple.c9
-rw-r--r--drivers/net/virtio/virtio_user/vhost_user.c5
-rw-r--r--drivers/net/virtio/virtio_user/virtio_user_dev.c6
-rw-r--r--drivers/net/virtio/virtio_user_ethdev.c72
-rw-r--r--drivers/net/vmxnet3/vmxnet3_ethdev.c12
-rw-r--r--drivers/net/xenvirt/rte_eth_xenvirt.c5
75 files changed, 1577 insertions, 905 deletions
diff --git a/drivers/crypto/aesni_gcm/aesni_gcm_pmd.c b/drivers/crypto/aesni_gcm/aesni_gcm_pmd.c
index 2987ef6b..dc0b0337 100644
--- a/drivers/crypto/aesni_gcm/aesni_gcm_pmd.c
+++ b/drivers/crypto/aesni_gcm/aesni_gcm_pmd.c
@@ -57,7 +57,7 @@ create_unique_device_name(char *name, size_t size)
if (name == NULL)
return -EINVAL;
- ret = snprintf(name, size, "%s_%u", CRYPTODEV_NAME_AESNI_GCM_PMD,
+ ret = snprintf(name, size, "%s_%u", RTE_STR(CRYPTODEV_NAME_AESNI_GCM_PMD),
unique_name_id++);
if (ret < 0)
return ret;
@@ -515,10 +515,13 @@ aesni_gcm_uninit(const char *name)
}
static struct rte_driver aesni_gcm_pmd_drv = {
- .name = CRYPTODEV_NAME_AESNI_GCM_PMD,
.type = PMD_VDEV,
.init = aesni_gcm_init,
.uninit = aesni_gcm_uninit
};
-PMD_REGISTER_DRIVER(aesni_gcm_pmd_drv);
+PMD_REGISTER_DRIVER(aesni_gcm_pmd_drv, CRYPTODEV_NAME_AESNI_GCM_PMD);
+DRIVER_REGISTER_PARAM_STRING(CRYPTODEV_NAME_AESNI_GCM_PMD,
+ "max_nb_queue_pairs=<int> "
+ "max_nb_sessions=<int> "
+ "socket_id=<int>");
diff --git a/drivers/crypto/aesni_gcm/aesni_gcm_pmd_private.h b/drivers/crypto/aesni_gcm/aesni_gcm_pmd_private.h
index a42f9414..9878d6e4 100644
--- a/drivers/crypto/aesni_gcm/aesni_gcm_pmd_private.h
+++ b/drivers/crypto/aesni_gcm/aesni_gcm_pmd_private.h
@@ -37,18 +37,18 @@
#define GCM_LOG_ERR(fmt, args...) \
RTE_LOG(ERR, CRYPTODEV, "[%s] %s() line %u: " fmt "\n", \
- CRYPTODEV_NAME_AESNI_GCM_PMD, \
+ RTE_STR(CRYPTODEV_NAME_AESNI_GCM_PMD), \
__func__, __LINE__, ## args)
#ifdef RTE_LIBRTE_AESNI_MB_DEBUG
#define GCM_LOG_INFO(fmt, args...) \
RTE_LOG(INFO, CRYPTODEV, "[%s] %s() line %u: " fmt "\n", \
- CRYPTODEV_NAME_AESNI_GCM_PMD, \
+ RTE_STR(CRYPTODEV_NAME_AESNI_GCM_PMD), \
__func__, __LINE__, ## args)
#define GCM_LOG_DBG(fmt, args...) \
RTE_LOG(DEBUG, CRYPTODEV, "[%s] %s() line %u: " fmt "\n", \
- CRYPTODEV_NAME_AESNI_GCM_PMD, \
+ RTE_STR(CRYPTODEV_NAME_AESNI_GCM_PMD), \
__func__, __LINE__, ## args)
#else
#define GCM_LOG_INFO(fmt, args...)
diff --git a/drivers/crypto/aesni_mb/rte_aesni_mb_pmd.c b/drivers/crypto/aesni_mb/rte_aesni_mb_pmd.c
index 6554fc4e..b2d0c8ca 100644
--- a/drivers/crypto/aesni_mb/rte_aesni_mb_pmd.c
+++ b/drivers/crypto/aesni_mb/rte_aesni_mb_pmd.c
@@ -54,7 +54,7 @@ create_unique_device_name(char *name, size_t size)
if (name == NULL)
return -EINVAL;
- ret = snprintf(name, size, "%s_%u", CRYPTODEV_NAME_AESNI_MB_PMD,
+ ret = snprintf(name, size, "%s_%u", RTE_STR(CRYPTODEV_NAME_AESNI_MB_PMD),
unique_name_id++);
if (ret < 0)
return ret;
@@ -715,10 +715,13 @@ cryptodev_aesni_mb_uninit(const char *name)
}
static struct rte_driver cryptodev_aesni_mb_pmd_drv = {
- .name = CRYPTODEV_NAME_AESNI_MB_PMD,
.type = PMD_VDEV,
.init = cryptodev_aesni_mb_init,
.uninit = cryptodev_aesni_mb_uninit
};
-PMD_REGISTER_DRIVER(cryptodev_aesni_mb_pmd_drv);
+PMD_REGISTER_DRIVER(cryptodev_aesni_mb_pmd_drv, CRYPTODEV_NAME_AESNI_MB_PMD);
+DRIVER_REGISTER_PARAM_STRING(CRYPTODEV_NAME_AESNI_MB_PMD,
+ "max_nb_queue_pairs=<int> "
+ "max_nb_sessions=<int> "
+ "socket_id=<int>");
diff --git a/drivers/crypto/aesni_mb/rte_aesni_mb_pmd_private.h b/drivers/crypto/aesni_mb/rte_aesni_mb_pmd_private.h
index 949d9a60..17f367f4 100644
--- a/drivers/crypto/aesni_mb/rte_aesni_mb_pmd_private.h
+++ b/drivers/crypto/aesni_mb/rte_aesni_mb_pmd_private.h
@@ -37,7 +37,7 @@
#define MB_LOG_ERR(fmt, args...) \
RTE_LOG(ERR, CRYPTODEV, "[%s] %s() line %u: " fmt "\n", \
- CRYPTODEV_NAME_AESNI_MB_PMD, \
+ RTE_STR(CRYPTODEV_NAME_AESNI_MB_PMD), \
__func__, __LINE__, ## args)
#ifdef RTE_LIBRTE_AESNI_MB_DEBUG
diff --git a/drivers/crypto/kasumi/rte_kasumi_pmd.c b/drivers/crypto/kasumi/rte_kasumi_pmd.c
index 5f8c7a2e..4e217434 100644
--- a/drivers/crypto/kasumi/rte_kasumi_pmd.c
+++ b/drivers/crypto/kasumi/rte_kasumi_pmd.c
@@ -61,7 +61,7 @@ create_unique_device_name(char *name, size_t size)
if (name == NULL)
return -EINVAL;
- ret = snprintf(name, size, "%s_%u", CRYPTODEV_NAME_KASUMI_PMD,
+ ret = snprintf(name, size, "%s_%u", RTE_STR(CRYPTODEV_NAME_KASUMI_PMD),
unique_name_id++);
if (ret < 0)
return ret;
@@ -243,9 +243,12 @@ process_kasumi_cipher_op_bit(struct rte_crypto_op *op,
offset_in_bits = op->sym->cipher.data.offset;
src = rte_pktmbuf_mtod(op->sym->m_src, uint8_t *);
- dst = op->sym->m_dst ?
- rte_pktmbuf_mtod(op->sym->m_dst, uint8_t *) :
- rte_pktmbuf_mtod(op->sym->m_src, uint8_t *);
+ if (op->sym->m_dst == NULL) {
+ op->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;
+ KASUMI_LOG_ERR("bit-level in-place not supported\n");
+ return 0;
+ }
+ dst = rte_pktmbuf_mtod(op->sym->m_dst, uint8_t *);
IV = *((uint64_t *)(op->sym->cipher.iv.data));
length_in_bits = op->sym->cipher.data.length;
@@ -648,10 +651,13 @@ cryptodev_kasumi_uninit(const char *name)
}
static struct rte_driver cryptodev_kasumi_pmd_drv = {
- .name = CRYPTODEV_NAME_KASUMI_PMD,
.type = PMD_VDEV,
.init = cryptodev_kasumi_init,
.uninit = cryptodev_kasumi_uninit
};
-PMD_REGISTER_DRIVER(cryptodev_kasumi_pmd_drv);
+PMD_REGISTER_DRIVER(cryptodev_kasumi_pmd_drv, CRYPTODEV_NAME_KASUMI_PMD);
+DRIVER_REGISTER_PARAM_STRING(CRYPTODEV_NAME_KASUMI_PMD,
+ "max_nb_queue_pairs=<int> "
+ "max_nb_sessions=<int> "
+ "socket_id=<int>");
diff --git a/drivers/crypto/kasumi/rte_kasumi_pmd_ops.c b/drivers/crypto/kasumi/rte_kasumi_pmd_ops.c
index da5854eb..b9285a43 100644
--- a/drivers/crypto/kasumi/rte_kasumi_pmd_ops.c
+++ b/drivers/crypto/kasumi/rte_kasumi_pmd_ops.c
@@ -57,8 +57,8 @@ static const struct rte_cryptodev_capabilities kasumi_pmd_capabilities[] = {
.increment = 0
},
.aad_size = {
- .min = 9,
- .max = 9,
+ .min = 8,
+ .max = 8,
.increment = 0
}
}, }
diff --git a/drivers/crypto/kasumi/rte_kasumi_pmd_private.h b/drivers/crypto/kasumi/rte_kasumi_pmd_private.h
index 04e1c437..fb586caa 100644
--- a/drivers/crypto/kasumi/rte_kasumi_pmd_private.h
+++ b/drivers/crypto/kasumi/rte_kasumi_pmd_private.h
@@ -37,18 +37,18 @@
#define KASUMI_LOG_ERR(fmt, args...) \
RTE_LOG(ERR, CRYPTODEV, "[%s] %s() line %u: " fmt "\n", \
- CRYPTODEV_NAME_KASUMI_PMD, \
+ RTE_STR(CRYPTODEV_NAME_KASUMI_PMD), \
__func__, __LINE__, ## args)
#ifdef RTE_LIBRTE_KASUMI_DEBUG
#define KASUMI_LOG_INFO(fmt, args...) \
RTE_LOG(INFO, CRYPTODEV, "[%s] %s() line %u: " fmt "\n", \
- CRYPTODEV_NAME_KASUMI_PMD, \
+ RTE_STR(CRYPTODEV_NAME_KASUMI_PMD), \
__func__, __LINE__, ## args)
#define KASUMI_LOG_DBG(fmt, args...) \
RTE_LOG(DEBUG, CRYPTODEV, "[%s] %s() line %u: " fmt "\n", \
- CRYPTODEV_NAME_KASUMI_PMD, \
+ RTE_STR(CRYPTODEV_NAME_KASUMI_PMD), \
__func__, __LINE__, ## args)
#else
#define KASUMI_LOG_INFO(fmt, args...)
diff --git a/drivers/crypto/null/null_crypto_pmd.c b/drivers/crypto/null/null_crypto_pmd.c
index bdaf13ca..909b04f9 100644
--- a/drivers/crypto/null/null_crypto_pmd.c
+++ b/drivers/crypto/null/null_crypto_pmd.c
@@ -51,7 +51,7 @@ create_unique_device_name(char *name, size_t size)
if (name == NULL)
return -EINVAL;
- ret = snprintf(name, size, "%s_%u", CRYPTODEV_NAME_NULL_PMD,
+ ret = snprintf(name, size, "%s_%u", RTE_STR(CRYPTODEV_NAME_NULL_PMD),
unique_name_id++);
if (ret < 0)
return ret;
@@ -269,10 +269,13 @@ cryptodev_null_uninit(const char *name)
}
static struct rte_driver cryptodev_null_pmd_drv = {
- .name = CRYPTODEV_NAME_NULL_PMD,
.type = PMD_VDEV,
.init = cryptodev_null_init,
.uninit = cryptodev_null_uninit
};
-PMD_REGISTER_DRIVER(cryptodev_null_pmd_drv);
+PMD_REGISTER_DRIVER(cryptodev_null_pmd_drv, CRYPTODEV_NAME_NULL_PMD);
+DRIVER_REGISTER_PARAM_STRING(CRYPTODEV_NAME_NULL_PMD,
+ "max_nb_queue_pairs=<int> "
+ "max_nb_sessions=<int> "
+ "socket_id=<int>");
diff --git a/drivers/crypto/null/null_crypto_pmd_private.h b/drivers/crypto/null/null_crypto_pmd_private.h
index 2a4c739c..acebc973 100644
--- a/drivers/crypto/null/null_crypto_pmd_private.h
+++ b/drivers/crypto/null/null_crypto_pmd_private.h
@@ -37,18 +37,18 @@
#define NULL_CRYPTO_LOG_ERR(fmt, args...) \
RTE_LOG(ERR, CRYPTODEV, "[%s] %s() line %u: " fmt "\n", \
- CRYPTODEV_NAME_NULL_PMD, \
+ RTE_STR(CRYPTODEV_NAME_NULL_PMD), \
__func__, __LINE__, ## args)
#ifdef RTE_LIBRTE_NULL_CRYPTO_DEBUG
#define NULL_CRYPTO_LOG_INFO(fmt, args...) \
RTE_LOG(INFO, CRYPTODEV, "[%s] %s() line %u: " fmt "\n", \
- CRYPTODEV_NAME_NULL_PMD, \
+ RTE_STR(CRYPTODEV_NAME_NULL_PMD), \
__func__, __LINE__, ## args)
#define NULL_CRYPTO_LOG_DBG(fmt, args...) \
RTE_LOG(DEBUG, CRYPTODEV, "[%s] %s() line %u: " fmt "\n", \
- CRYPTODEV_NAME_NULL_PMD, \
+ RTE_STR(CRYPTODEV_NAME_NULL_PMD), \
__func__, __LINE__, ## args)
#else
#define NULL_CRYPTO_LOG_INFO(fmt, args...)
diff --git a/drivers/crypto/qat/qat_adf/qat_algs.h b/drivers/crypto/qat/qat_adf/qat_algs.h
index b47dbc23..243c1b40 100644
--- a/drivers/crypto/qat/qat_adf/qat_algs.h
+++ b/drivers/crypto/qat/qat_adf/qat_algs.h
@@ -112,7 +112,8 @@ int qat_alg_aead_session_create_content_desc_auth(struct qat_session *cdesc,
uint8_t *authkey,
uint32_t authkeylen,
uint32_t add_auth_data_length,
- uint32_t digestsize);
+ uint32_t digestsize,
+ unsigned int operation);
void qat_alg_init_common_hdr(struct icp_qat_fw_comn_req_hdr *header);
diff --git a/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c b/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c
index aa108d47..185bb334 100644
--- a/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c
+++ b/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c
@@ -51,6 +51,7 @@
#include <rte_byteorder.h>
#include <rte_log.h>
#include <rte_malloc.h>
+#include <rte_crypto_sym.h>
#include "../qat_logs.h"
#include "qat_algs.h"
@@ -502,7 +503,8 @@ int qat_alg_aead_session_create_content_desc_auth(struct qat_session *cdesc,
uint8_t *authkey,
uint32_t authkeylen,
uint32_t add_auth_data_length,
- uint32_t digestsize)
+ uint32_t digestsize,
+ unsigned int operation)
{
struct icp_qat_hw_cipher_algo_blk *cipher;
struct icp_qat_hw_auth_algo_blk *hash;
@@ -654,6 +656,12 @@ int qat_alg_aead_session_create_content_desc_auth(struct qat_session *cdesc,
ICP_QAT_FW_LA_CMP_AUTH_SET(header->serv_specif_flags,
ICP_QAT_FW_LA_NO_CMP_AUTH_RES);
}
+ if (operation == RTE_CRYPTO_AUTH_OP_VERIFY) {
+ ICP_QAT_FW_LA_RET_AUTH_SET(header->serv_specif_flags,
+ ICP_QAT_FW_LA_NO_RET_AUTH_RES);
+ ICP_QAT_FW_LA_CMP_AUTH_SET(header->serv_specif_flags,
+ ICP_QAT_FW_LA_CMP_AUTH_RES);
+ }
/* Cipher CD config setup */
cipher_cd_ctrl->cipher_state_sz = ICP_QAT_HW_AES_BLK_SZ >> 3;
diff --git a/drivers/crypto/qat/qat_crypto.c b/drivers/crypto/qat/qat_crypto.c
index 940b2b63..d51ca968 100644
--- a/drivers/crypto/qat/qat_crypto.c
+++ b/drivers/crypto/qat/qat_crypto.c
@@ -560,14 +560,16 @@ qat_crypto_sym_configure_session_auth(struct rte_cryptodev *dev,
cipher_xform->key.data,
cipher_xform->key.length,
auth_xform->add_auth_data_length,
- auth_xform->digest_length))
+ auth_xform->digest_length,
+ auth_xform->op))
goto error_out;
} else {
if (qat_alg_aead_session_create_content_desc_auth(session,
auth_xform->key.data,
auth_xform->key.length,
auth_xform->add_auth_data_length,
- auth_xform->digest_length))
+ auth_xform->digest_length,
+ auth_xform->op))
goto error_out;
}
return session;
diff --git a/drivers/crypto/qat/rte_qat_cryptodev.c b/drivers/crypto/qat/rte_qat_cryptodev.c
index f46ec857..82ab047f 100644
--- a/drivers/crypto/qat/rte_qat_cryptodev.c
+++ b/drivers/crypto/qat/rte_qat_cryptodev.c
@@ -114,7 +114,6 @@ crypto_qat_dev_init(__attribute__((unused)) struct rte_cryptodev_driver *crypto_
static struct rte_cryptodev_driver rte_qat_pmd = {
{
- .name = "rte_qat_pmd",
.id_table = pci_id_qat_map,
.drv_flags = RTE_PCI_DRV_NEED_MAPPING,
},
@@ -134,4 +133,6 @@ static struct rte_driver pmd_qat_drv = {
.init = rte_qat_pmd_init,
};
-PMD_REGISTER_DRIVER(pmd_qat_drv);
+PMD_REGISTER_DRIVER(pmd_qat_drv, CRYPTODEV_NAME_QAT_SYM_PMD);
+DRIVER_REGISTER_PCI_TABLE(CRYPTODEV_NAME_QAT_SYM_PMD, pci_id_qat_map);
+
diff --git a/drivers/crypto/snow3g/rte_snow3g_pmd.c b/drivers/crypto/snow3g/rte_snow3g_pmd.c
index dc8de6bd..87cd070a 100644
--- a/drivers/crypto/snow3g/rte_snow3g_pmd.c
+++ b/drivers/crypto/snow3g/rte_snow3g_pmd.c
@@ -60,7 +60,7 @@ create_unique_device_name(char *name, size_t size)
if (name == NULL)
return -EINVAL;
- ret = snprintf(name, size, "%s_%u", CRYPTODEV_NAME_SNOW3G_PMD,
+ ret = snprintf(name, size, "%s_%u", RTE_STR(CRYPTODEV_NAME_SNOW3G_PMD),
unique_name_id++);
if (ret < 0)
return ret;
@@ -639,10 +639,13 @@ cryptodev_snow3g_uninit(const char *name)
}
static struct rte_driver cryptodev_snow3g_pmd_drv = {
- .name = CRYPTODEV_NAME_SNOW3G_PMD,
.type = PMD_VDEV,
.init = cryptodev_snow3g_init,
.uninit = cryptodev_snow3g_uninit
};
-PMD_REGISTER_DRIVER(cryptodev_snow3g_pmd_drv);
+PMD_REGISTER_DRIVER(cryptodev_snow3g_pmd_drv, CRYPTODEV_NAME_SNOW3G_PMD);
+DRIVER_REGISTER_PARAM_STRING(CRYPTODEV_NAME_SNOW3G_PMD,
+ "max_nb_queue_pairs=<int> "
+ "max_nb_sessions=<int> "
+ "socket_id=<int>");
diff --git a/drivers/crypto/snow3g/rte_snow3g_pmd_private.h b/drivers/crypto/snow3g/rte_snow3g_pmd_private.h
index b383cbcb..03973b97 100644
--- a/drivers/crypto/snow3g/rte_snow3g_pmd_private.h
+++ b/drivers/crypto/snow3g/rte_snow3g_pmd_private.h
@@ -37,18 +37,18 @@
#define SNOW3G_LOG_ERR(fmt, args...) \
RTE_LOG(ERR, CRYPTODEV, "[%s] %s() line %u: " fmt "\n", \
- CRYPTODEV_NAME_SNOW3G_PMD, \
+ RTE_STR(CRYPTODEV_NAME_SNOW3G_PMD), \
__func__, __LINE__, ## args)
#ifdef RTE_LIBRTE_SNOW3G_DEBUG
#define SNOW3G_LOG_INFO(fmt, args...) \
RTE_LOG(INFO, CRYPTODEV, "[%s] %s() line %u: " fmt "\n", \
- CRYPTODEV_NAME_SNOW3G_PMD, \
+ RTE_STR(CRYPTODEV_NAME_SNOW3G_PMD), \
__func__, __LINE__, ## args)
#define SNOW3G_LOG_DBG(fmt, args...) \
RTE_LOG(DEBUG, CRYPTODEV, "[%s] %s() line %u: " fmt "\n", \
- CRYPTODEV_NAME_SNOW3G_PMD, \
+ RTE_STR(CRYPTODEV_NAME_SNOW3G_PMD), \
__func__, __LINE__, ## args)
#else
#define SNOW3G_LOG_INFO(fmt, args...)
diff --git a/drivers/net/af_packet/rte_eth_af_packet.c b/drivers/net/af_packet/rte_eth_af_packet.c
index 2d7f3448..f7955662 100644
--- a/drivers/net/af_packet/rte_eth_af_packet.c
+++ b/drivers/net/af_packet/rte_eth_af_packet.c
@@ -890,10 +890,15 @@ rte_pmd_af_packet_devuninit(const char *name)
}
static struct rte_driver pmd_af_packet_drv = {
- .name = "eth_af_packet",
.type = PMD_VDEV,
.init = rte_pmd_af_packet_devinit,
.uninit = rte_pmd_af_packet_devuninit,
};
-PMD_REGISTER_DRIVER(pmd_af_packet_drv);
+PMD_REGISTER_DRIVER(pmd_af_packet_drv, eth_af_packet);
+DRIVER_REGISTER_PARAM_STRING(eth_af_packet,
+ "iface=<string> "
+ "qpairs=<int> "
+ "blocksz=<int> "
+ "framesz=<int> "
+ "framecnt=<int>");
diff --git a/drivers/net/bnx2x/Makefile b/drivers/net/bnx2x/Makefile
index c2ddd8d7..ab696801 100644
--- a/drivers/net/bnx2x/Makefile
+++ b/drivers/net/bnx2x/Makefile
@@ -31,7 +31,7 @@ SRCS-$(CONFIG_RTE_LIBRTE_BNX2X_PMD) += bnx2x_vfpf.c
SRCS-$(CONFIG_RTE_LIBRTE_BNX2X_DEBUG_PERIODIC) += debug.c
# this lib depends upon:
-DEPDIRS-$(CONFIG_RTE_LIBRTE_BNX2X_PMD) += lib/librte_eal lib/librte_ether lib/librte_hash
+DEPDIRS-$(CONFIG_RTE_LIBRTE_BNX2X_PMD) += lib/librte_eal lib/librte_ether
DEPDIRS-$(CONFIG_RTE_LIBRTE_BNX2X_PMD) += lib/librte_mempool lib/librte_mbuf
include $(RTE_SDK)/mk/rte.lib.mk
diff --git a/drivers/net/bnx2x/bnx2x.c b/drivers/net/bnx2x/bnx2x.c
index 3095d2bb..95fbad8d 100644
--- a/drivers/net/bnx2x/bnx2x.c
+++ b/drivers/net/bnx2x/bnx2x.c
@@ -22,7 +22,6 @@
#include "ecore_init_ops.h"
#include "rte_version.h"
-#include "rte_pci_dev_ids.h"
#include <sys/types.h>
#include <sys/stat.h>
@@ -9572,7 +9571,7 @@ void bnx2x_load_firmware(struct bnx2x_softc *sc)
int f;
struct stat st;
- fwname = sc->devinfo.device_id == BNX2X_DEV_ID_57711
+ fwname = sc->devinfo.device_id == CHIP_NUM_57711
? FW_NAME_57711 : FW_NAME_57810;
f = open(fwname, O_RDONLY);
if (f < 0) {
@@ -9682,9 +9681,6 @@ int bnx2x_attach(struct bnx2x_softc *sc)
sc->state = BNX2X_STATE_CLOSED;
- /* Init RTE stuff */
- bnx2x_init_rte(sc);
-
pci_write_long(sc, PCICFG_GRC_ADDRESS, PCICFG_VENDOR_ID_OFFSET);
sc->igu_base_addr = IS_VF(sc) ? PXP_VF_ADDR_IGU_START : BAR_IGU_INTMEM;
@@ -9702,6 +9698,9 @@ int bnx2x_attach(struct bnx2x_softc *sc)
sc->igu_sb_cnt = 1;
}
+ /* Init RTE stuff */
+ bnx2x_init_rte(sc);
+
if (IS_PF(sc)) {
/* get device info and set params */
if (bnx2x_get_device_info(sc) != 0) {
diff --git a/drivers/net/bnx2x/bnx2x.h b/drivers/net/bnx2x/bnx2x.h
index c24a5308..78757a8d 100644
--- a/drivers/net/bnx2x/bnx2x.h
+++ b/drivers/net/bnx2x/bnx2x.h
@@ -1906,14 +1906,6 @@ pci_find_cap(struct bnx2x_softc *sc, uint8_t id, uint8_t type)
return NULL;
}
-static inline int is_valid_ether_addr(uint8_t *addr)
-{
- if (!(addr[0] | addr[1] | addr[2] | addr[3] | addr[4] | addr[5]))
- return 0;
- else
- return 1;
-}
-
static inline void
bnx2x_set_rx_mode(struct bnx2x_softc *sc)
{
diff --git a/drivers/net/bnx2x/bnx2x_ethdev.c b/drivers/net/bnx2x/bnx2x_ethdev.c
index 3ff57c42..c8d2bf2e 100644
--- a/drivers/net/bnx2x/bnx2x_ethdev.c
+++ b/drivers/net/bnx2x/bnx2x_ethdev.c
@@ -16,18 +16,67 @@
/*
* The set of PCI devices this driver supports
*/
+#define BROADCOM_PCI_VENDOR_ID 0x14E4
static struct rte_pci_id pci_id_bnx2x_map[] = {
-#define RTE_PCI_DEV_ID_DECL_BNX2X(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
-#include "rte_pci_dev_ids.h"
+ { RTE_PCI_DEVICE(BROADCOM_PCI_VENDOR_ID, CHIP_NUM_57800) },
+ { RTE_PCI_DEVICE(BROADCOM_PCI_VENDOR_ID, CHIP_NUM_57711) },
+ { RTE_PCI_DEVICE(BROADCOM_PCI_VENDOR_ID, CHIP_NUM_57810) },
+ { RTE_PCI_DEVICE(BROADCOM_PCI_VENDOR_ID, CHIP_NUM_57811) },
+ { RTE_PCI_DEVICE(BROADCOM_PCI_VENDOR_ID, CHIP_NUM_57840_OBS) },
+ { RTE_PCI_DEVICE(BROADCOM_PCI_VENDOR_ID, CHIP_NUM_57840_4_10) },
+ { RTE_PCI_DEVICE(BROADCOM_PCI_VENDOR_ID, CHIP_NUM_57840_2_20) },
+#ifdef RTE_LIBRTE_BNX2X_MF_SUPPORT
+ { RTE_PCI_DEVICE(BROADCOM_PCI_VENDOR_ID, CHIP_NUM_57810_MF) },
+ { RTE_PCI_DEVICE(BROADCOM_PCI_VENDOR_ID, CHIP_NUM_57811_MF) },
+ { RTE_PCI_DEVICE(BROADCOM_PCI_VENDOR_ID, CHIP_NUM_57840_MF) },
+#endif
{ .vendor_id = 0, }
};
static struct rte_pci_id pci_id_bnx2xvf_map[] = {
-#define RTE_PCI_DEV_ID_DECL_BNX2XVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
-#include "rte_pci_dev_ids.h"
+ { RTE_PCI_DEVICE(BROADCOM_PCI_VENDOR_ID, CHIP_NUM_57800_VF) },
+ { RTE_PCI_DEVICE(BROADCOM_PCI_VENDOR_ID, CHIP_NUM_57810_VF) },
+ { RTE_PCI_DEVICE(BROADCOM_PCI_VENDOR_ID, CHIP_NUM_57811_VF) },
+ { RTE_PCI_DEVICE(BROADCOM_PCI_VENDOR_ID, CHIP_NUM_57840_VF) },
{ .vendor_id = 0, }
};
+struct rte_bnx2x_xstats_name_off {
+ char name[RTE_ETH_XSTATS_NAME_SIZE];
+ uint32_t offset_hi;
+ uint32_t offset_lo;
+};
+
+static const struct rte_bnx2x_xstats_name_off bnx2x_xstats_strings[] = {
+ {"rx_buffer_drops",
+ offsetof(struct bnx2x_eth_stats, brb_drop_hi),
+ offsetof(struct bnx2x_eth_stats, brb_drop_lo)},
+ {"rx_buffer_truncates",
+ offsetof(struct bnx2x_eth_stats, brb_truncate_hi),
+ offsetof(struct bnx2x_eth_stats, brb_truncate_lo)},
+ {"rx_buffer_truncate_discard",
+ offsetof(struct bnx2x_eth_stats, brb_truncate_discard),
+ offsetof(struct bnx2x_eth_stats, brb_truncate_discard)},
+ {"mac_filter_discard",
+ offsetof(struct bnx2x_eth_stats, mac_filter_discard),
+ offsetof(struct bnx2x_eth_stats, mac_filter_discard)},
+ {"no_match_vlan_tag_discard",
+ offsetof(struct bnx2x_eth_stats, mf_tag_discard),
+ offsetof(struct bnx2x_eth_stats, mf_tag_discard)},
+ {"tx_pause",
+ offsetof(struct bnx2x_eth_stats, pause_frames_sent_hi),
+ offsetof(struct bnx2x_eth_stats, pause_frames_sent_lo)},
+ {"rx_pause",
+ offsetof(struct bnx2x_eth_stats, pause_frames_received_hi),
+ offsetof(struct bnx2x_eth_stats, pause_frames_received_lo)},
+ {"tx_priority_flow_control",
+ offsetof(struct bnx2x_eth_stats, pfc_frames_sent_hi),
+ offsetof(struct bnx2x_eth_stats, pfc_frames_sent_lo)},
+ {"rx_priority_flow_control",
+ offsetof(struct bnx2x_eth_stats, pfc_frames_received_hi),
+ offsetof(struct bnx2x_eth_stats, pfc_frames_received_lo)}
+};
+
static void
bnx2x_link_update(struct rte_eth_dev *dev)
{
@@ -334,6 +383,52 @@ bnx2x_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
brb_truncate_discard + stats->rx_nombuf;
}
+static int
+bnx2x_get_xstats_names(__rte_unused struct rte_eth_dev *dev,
+ struct rte_eth_xstat_name *xstats_names,
+ __rte_unused unsigned limit)
+{
+ unsigned int i, stat_cnt = RTE_DIM(bnx2x_xstats_strings);
+
+ if (xstats_names != NULL)
+ for (i = 0; i < stat_cnt; i++)
+ snprintf(xstats_names[i].name,
+ sizeof(xstats_names[i].name),
+ "%s",
+ bnx2x_xstats_strings[i].name);
+
+ return stat_cnt;
+}
+
+static int
+bnx2x_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
+ unsigned int n)
+{
+ struct bnx2x_softc *sc = dev->data->dev_private;
+ unsigned int num = RTE_DIM(bnx2x_xstats_strings);
+
+ if (n < num)
+ return num;
+
+ bnx2x_stats_handle(sc, STATS_EVENT_UPDATE);
+
+ for (num = 0; num < n; num++) {
+ if (bnx2x_xstats_strings[num].offset_hi !=
+ bnx2x_xstats_strings[num].offset_lo)
+ xstats[num].value = HILO_U64(
+ *(uint32_t *)((char *)&sc->eth_stats +
+ bnx2x_xstats_strings[num].offset_hi),
+ *(uint32_t *)((char *)&sc->eth_stats +
+ bnx2x_xstats_strings[num].offset_lo));
+ else
+ xstats[num].value =
+ *(uint64_t *)((char *)&sc->eth_stats +
+ bnx2x_xstats_strings[num].offset_lo);
+ }
+
+ return num;
+}
+
static void
bnx2x_dev_infos_get(struct rte_eth_dev *dev, __rte_unused struct rte_eth_dev_info *dev_info)
{
@@ -376,6 +471,8 @@ static const struct eth_dev_ops bnx2x_eth_dev_ops = {
.allmulticast_disable = bnx2x_dev_allmulticast_disable,
.link_update = bnx2x_dev_link_update,
.stats_get = bnx2x_dev_stats_get,
+ .xstats_get = bnx2x_dev_xstats_get,
+ .xstats_get_names = bnx2x_get_xstats_names,
.dev_infos_get = bnx2x_dev_infos_get,
.rx_queue_setup = bnx2x_dev_rx_queue_setup,
.rx_queue_release = bnx2x_dev_rx_queue_release,
@@ -399,6 +496,8 @@ static const struct eth_dev_ops bnx2xvf_eth_dev_ops = {
.allmulticast_disable = bnx2x_dev_allmulticast_disable,
.link_update = bnx2xvf_dev_link_update,
.stats_get = bnx2x_dev_stats_get,
+ .xstats_get = bnx2x_dev_xstats_get,
+ .xstats_get_names = bnx2x_get_xstats_names,
.dev_infos_get = bnx2x_dev_infos_get,
.rx_queue_setup = bnx2x_dev_rx_queue_setup,
.rx_queue_release = bnx2x_dev_rx_queue_release,
@@ -566,5 +665,7 @@ static struct rte_driver rte_bnx2xvf_driver = {
.init = rte_bnx2xvf_pmd_init,
};
-PMD_REGISTER_DRIVER(rte_bnx2x_driver);
-PMD_REGISTER_DRIVER(rte_bnx2xvf_driver);
+PMD_REGISTER_DRIVER(rte_bnx2x_driver, bnx2x);
+DRIVER_REGISTER_PCI_TABLE(bnx2x, pci_id_bnx2x_map);
+PMD_REGISTER_DRIVER(rte_bnx2xvf_driver, bnx2xvf);
+DRIVER_REGISTER_PCI_TABLE(bnx2xvf, pci_id_bnx2xvf_map);
diff --git a/drivers/net/bnx2x/bnx2x_vfpf.c b/drivers/net/bnx2x/bnx2x_vfpf.c
index 14b1d10a..1c895f88 100644
--- a/drivers/net/bnx2x/bnx2x_vfpf.c
+++ b/drivers/net/bnx2x/bnx2x_vfpf.c
@@ -293,10 +293,11 @@ int bnx2x_vf_get_resources(struct bnx2x_softc *sc, uint8_t tx_count, uint8_t rx_
sc->igu_sb_cnt, sc->igu_base_sb);
strncpy(sc->fw_ver, sc_resp.fw_ver, sizeof(sc->fw_ver));
- if (is_valid_ether_addr(sc_resp.resc.current_mac_addr))
- (void)rte_memcpy(sc->link_params.mac_addr,
- sc_resp.resc.current_mac_addr,
- ETH_ALEN);
+ if (is_valid_assigned_ether_addr(&sc_resp.resc.current_mac_addr))
+ ether_addr_copy(&sc_resp.resc.current_mac_addr,
+ (struct ether_addr *)sc->link_params.mac_addr);
+ else
+ eth_random_addr(sc->link_params.mac_addr);
return 0;
}
diff --git a/drivers/net/bnx2x/bnx2x_vfpf.h b/drivers/net/bnx2x/bnx2x_vfpf.h
index 966240cc..f854d81b 100644
--- a/drivers/net/bnx2x/bnx2x_vfpf.h
+++ b/drivers/net/bnx2x/bnx2x_vfpf.h
@@ -114,7 +114,7 @@ struct vf_resc {
uint8_t num_vlan_filters;
uint8_t num_mc_filters;
uint8_t permanent_mac_addr[ETH_ALEN];
- uint8_t current_mac_addr[ETH_ALEN];
+ struct ether_addr current_mac_addr;
uint16_t pf_link_speed;
uint32_t pf_link_supported;
};
diff --git a/drivers/net/bnxt/bnxt_ethdev.c b/drivers/net/bnxt/bnxt_ethdev.c
index 406e38a6..3795facd 100644
--- a/drivers/net/bnxt/bnxt_ethdev.c
+++ b/drivers/net/bnxt/bnxt_ethdev.c
@@ -56,10 +56,31 @@
static const char bnxt_version[] =
"Broadcom Cumulus driver " DRV_MODULE_NAME "\n";
+#define PCI_VENDOR_ID_BROADCOM 0x14E4
+
+#define BROADCOM_DEV_ID_57301 0x16c8
+#define BROADCOM_DEV_ID_57302 0x16c9
+#define BROADCOM_DEV_ID_57304_PF 0x16ca
+#define BROADCOM_DEV_ID_57304_VF 0x16cb
+#define BROADCOM_DEV_ID_57402 0x16d0
+#define BROADCOM_DEV_ID_57404 0x16d1
+#define BROADCOM_DEV_ID_57406_PF 0x16d2
+#define BROADCOM_DEV_ID_57406_VF 0x16d3
+#define BROADCOM_DEV_ID_57406_MF 0x16d4
+#define BROADCOM_DEV_ID_57314 0x16df
+
static struct rte_pci_id bnxt_pci_id_map[] = {
-#define RTE_PCI_DEV_ID_DECL_BNXT(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
-#include "rte_pci_dev_ids.h"
- {.device_id = 0},
+ { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
+ { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
+ { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
+ { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
+ { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
+ { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
+ { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
+ { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
+ { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
+ { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
+ { .vendor_id = 0, /* sentinel */ },
};
#define BNXT_ETH_RSS_SUPPORT ( \
@@ -1041,9 +1062,9 @@ static int bnxt_rte_pmd_init(const char *name, const char *params __rte_unused)
}
static struct rte_driver bnxt_pmd_drv = {
- .name = "eth_bnxt",
.type = PMD_PDEV,
.init = bnxt_rte_pmd_init,
};
-PMD_REGISTER_DRIVER(bnxt_pmd_drv);
+PMD_REGISTER_DRIVER(bnxt_pmd_drv, bnxt);
+DRIVER_REGISTER_PCI_TABLE(bnxt, bnxt_pci_id_map);
diff --git a/drivers/net/bnxt/bnxt_hwrm.c b/drivers/net/bnxt/bnxt_hwrm.c
index 5d81a60d..2ed4c2f1 100644
--- a/drivers/net/bnxt/bnxt_hwrm.c
+++ b/drivers/net/bnxt/bnxt_hwrm.c
@@ -177,8 +177,7 @@ int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
mask = HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS;
if (vnic->flags & BNXT_VNIC_INFO_ALLMULTI)
mask = HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST;
- req.mask = rte_cpu_to_le_32(HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST |
- HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST |
+ req.mask = rte_cpu_to_le_32(HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST |
mask);
rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
diff --git a/drivers/net/bonding/rte_eth_bond_8023ad.c b/drivers/net/bonding/rte_eth_bond_8023ad.c
index 48a50e4e..2f7ae70c 100644
--- a/drivers/net/bonding/rte_eth_bond_8023ad.c
+++ b/drivers/net/bonding/rte_eth_bond_8023ad.c
@@ -1068,7 +1068,7 @@ bond_mode_8023ad_conf_assign(struct mode8023ad_private *mode4,
}
static void
-bond_mode_8023ad_setup_v1604(struct rte_eth_dev *dev,
+bond_mode_8023ad_setup_v20(struct rte_eth_dev *dev,
struct rte_eth_bond_8023ad_conf *conf)
{
struct rte_eth_bond_8023ad_conf def_conf;
@@ -1214,7 +1214,7 @@ free_out:
}
int
-rte_eth_bond_8023ad_conf_get_v1604(uint8_t port_id,
+rte_eth_bond_8023ad_conf_get_v20(uint8_t port_id,
struct rte_eth_bond_8023ad_conf *conf)
{
struct rte_eth_dev *bond_dev;
@@ -1229,7 +1229,7 @@ rte_eth_bond_8023ad_conf_get_v1604(uint8_t port_id,
bond_mode_8023ad_conf_get(bond_dev, conf);
return 0;
}
-VERSION_SYMBOL(rte_eth_bond_8023ad_conf_get, _v1604, 16.04);
+VERSION_SYMBOL(rte_eth_bond_8023ad_conf_get, _v20, 2.0);
int
rte_eth_bond_8023ad_conf_get_v1607(uint8_t port_id,
@@ -1278,7 +1278,7 @@ bond_8023ad_setup_validate(uint8_t port_id,
}
int
-rte_eth_bond_8023ad_setup_v1604(uint8_t port_id,
+rte_eth_bond_8023ad_setup_v20(uint8_t port_id,
struct rte_eth_bond_8023ad_conf *conf)
{
struct rte_eth_dev *bond_dev;
@@ -1289,11 +1289,11 @@ rte_eth_bond_8023ad_setup_v1604(uint8_t port_id,
return err;
bond_dev = &rte_eth_devices[port_id];
- bond_mode_8023ad_setup_v1604(bond_dev, conf);
+ bond_mode_8023ad_setup_v20(bond_dev, conf);
return 0;
}
-VERSION_SYMBOL(rte_eth_bond_8023ad_setup, _v1604, 16.04);
+VERSION_SYMBOL(rte_eth_bond_8023ad_setup, _v20, 2.0);
int
rte_eth_bond_8023ad_setup_v1607(uint8_t port_id,
diff --git a/drivers/net/bonding/rte_eth_bond_8023ad.h b/drivers/net/bonding/rte_eth_bond_8023ad.h
index 1de34bc8..6b8ff575 100644
--- a/drivers/net/bonding/rte_eth_bond_8023ad.h
+++ b/drivers/net/bonding/rte_eth_bond_8023ad.h
@@ -188,7 +188,7 @@ int
rte_eth_bond_8023ad_conf_get(uint8_t port_id,
struct rte_eth_bond_8023ad_conf *conf);
int
-rte_eth_bond_8023ad_conf_get_v1604(uint8_t port_id,
+rte_eth_bond_8023ad_conf_get_v20(uint8_t port_id,
struct rte_eth_bond_8023ad_conf *conf);
int
rte_eth_bond_8023ad_conf_get_v1607(uint8_t port_id,
@@ -209,7 +209,7 @@ int
rte_eth_bond_8023ad_setup(uint8_t port_id,
struct rte_eth_bond_8023ad_conf *conf);
int
-rte_eth_bond_8023ad_setup_v1604(uint8_t port_id,
+rte_eth_bond_8023ad_setup_v20(uint8_t port_id,
struct rte_eth_bond_8023ad_conf *conf);
int
rte_eth_bond_8023ad_setup_v1607(uint8_t port_id,
diff --git a/drivers/net/bonding/rte_eth_bond_pmd.c b/drivers/net/bonding/rte_eth_bond_pmd.c
index 9a2518fb..b20a2729 100644
--- a/drivers/net/bonding/rte_eth_bond_pmd.c
+++ b/drivers/net/bonding/rte_eth_bond_pmd.c
@@ -2509,10 +2509,20 @@ bond_ethdev_configure(struct rte_eth_dev *dev)
}
static struct rte_driver bond_drv = {
- .name = "eth_bond",
.type = PMD_VDEV,
.init = bond_init,
.uninit = bond_uninit,
};
-PMD_REGISTER_DRIVER(bond_drv);
+PMD_REGISTER_DRIVER(bond_drv, eth_bond);
+
+DRIVER_REGISTER_PARAM_STRING(eth_bond,
+ "slave=<ifc> "
+ "primary=<ifc> "
+ "mode=[0-6] "
+ "xmit_policy=[l2 | l23 | l34] "
+ "socket_id=<int> "
+ "mac=<mac addr> "
+ "lsc_poll_period_ms=<int> "
+ "up_delay=<int> "
+ "down_delay=<int>");
diff --git a/drivers/net/cxgbe/cxgbe_ethdev.c b/drivers/net/cxgbe/cxgbe_ethdev.c
index 6c130ed2..9208a615 100644
--- a/drivers/net/cxgbe/cxgbe_ethdev.c
+++ b/drivers/net/cxgbe/cxgbe_ethdev.c
@@ -934,10 +934,17 @@ static int cxgbe_get_regs(struct rte_eth_dev *eth_dev,
struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
struct adapter *adapter = pi->adapter;
- regs->length = cxgbe_get_regs_len(eth_dev);
regs->version = CHELSIO_CHIP_VERSION(adapter->params.chip) |
- (CHELSIO_CHIP_RELEASE(adapter->params.chip) << 10) |
- (1 << 16);
+ (CHELSIO_CHIP_RELEASE(adapter->params.chip) << 10) |
+ (1 << 16);
+
+ if (regs->data == NULL) {
+ regs->length = cxgbe_get_regs_len(eth_dev);
+ regs->width = sizeof(uint32_t);
+
+ return 0;
+ }
+
t4_get_regs(adapter, regs->data, (regs->length * sizeof(uint32_t)));
return 0;
@@ -971,7 +978,6 @@ static const struct eth_dev_ops cxgbe_eth_dev_ops = {
.get_eeprom_length = cxgbe_get_eeprom_length,
.get_eeprom = cxgbe_get_eeprom,
.set_eeprom = cxgbe_set_eeprom,
- .get_reg_length = cxgbe_get_regs_len,
.get_reg = cxgbe_get_regs,
};
@@ -1056,9 +1062,10 @@ static int rte_cxgbe_pmd_init(const char *name __rte_unused,
}
static struct rte_driver rte_cxgbe_driver = {
- .name = "cxgbe_driver",
.type = PMD_PDEV,
.init = rte_cxgbe_pmd_init,
};
-PMD_REGISTER_DRIVER(rte_cxgbe_driver);
+PMD_REGISTER_DRIVER(rte_cxgbe_driver, cxgb4);
+DRIVER_REGISTER_PCI_TABLE(cxgb4, cxgb4_pci_tbl);
+
diff --git a/drivers/net/e1000/e1000_ethdev.h b/drivers/net/e1000/e1000_ethdev.h
index e8bf8dad..6c25c8da 100644
--- a/drivers/net/e1000/e1000_ethdev.h
+++ b/drivers/net/e1000/e1000_ethdev.h
@@ -35,6 +35,8 @@
#define _E1000_ETHDEV_H_
#include <rte_time.h>
+#define E1000_INTEL_VENDOR_ID 0x8086
+
/* need update link, bit flag */
#define E1000_FLAG_NEED_LINK_UPDATE (uint32_t)(1 << 0)
#define E1000_FLAG_MAILBOX (uint32_t)(1 << 1)
diff --git a/drivers/net/e1000/em_ethdev.c b/drivers/net/e1000/em_ethdev.c
index 653be092..ad104ed7 100644
--- a/drivers/net/e1000/em_ethdev.c
+++ b/drivers/net/e1000/em_ethdev.c
@@ -137,11 +137,38 @@ static enum e1000_fc_mode em_fc_setting = e1000_fc_full;
* The set of PCI devices this driver supports
*/
static const struct rte_pci_id pci_id_em_map[] = {
-
-#define RTE_PCI_DEV_ID_DECL_EM(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
-#include "rte_pci_dev_ids.h"
-
-{0},
+ { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82540EM) },
+ { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82545EM_COPPER) },
+ { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82545EM_FIBER) },
+ { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82546EB_COPPER) },
+ { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82546EB_FIBER) },
+ { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82546EB_QUAD_COPPER) },
+ { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_COPPER) },
+ { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_FIBER) },
+ { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_SERDES) },
+ { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_SERDES_DUAL) },
+ { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_SERDES_QUAD) },
+ { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_QUAD_COPPER) },
+ { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571PT_QUAD_COPPER) },
+ { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_QUAD_FIBER) },
+ { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_QUAD_COPPER_LP) },
+ { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82572EI_COPPER) },
+ { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82572EI_FIBER) },
+ { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82572EI_SERDES) },
+ { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82572EI) },
+ { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82573L) },
+ { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82574L) },
+ { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82574LA) },
+ { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82583V) },
+ { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LPT_I217_LM) },
+ { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LPT_I217_V) },
+ { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LPTLP_I218_LM) },
+ { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LPTLP_I218_V) },
+ { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_I218_LM2) },
+ { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_I218_V2) },
+ { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_I218_LM3) },
+ { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_I218_V3) },
+ { .vendor_id = 0, /* sentinel */ },
};
static const struct eth_dev_ops eth_em_ops = {
@@ -1777,4 +1804,5 @@ struct rte_driver em_pmd_drv = {
.init = rte_em_pmd_init,
};
-PMD_REGISTER_DRIVER(em_pmd_drv);
+PMD_REGISTER_DRIVER(em_pmd_drv, em);
+DRIVER_REGISTER_PCI_TABLE(em, pci_id_em_map);
diff --git a/drivers/net/e1000/igb_ethdev.c b/drivers/net/e1000/igb_ethdev.c
index 5067d208..fbf4d090 100644
--- a/drivers/net/e1000/igb_ethdev.c
+++ b/drivers/net/e1000/igb_ethdev.c
@@ -386,7 +386,6 @@ static const struct eth_dev_ops eth_igb_ops = {
.timesync_disable = igb_timesync_disable,
.timesync_read_rx_timestamp = igb_timesync_read_rx_timestamp,
.timesync_read_tx_timestamp = igb_timesync_read_tx_timestamp,
- .get_reg_length = eth_igb_get_reg_length,
.get_reg = eth_igb_get_regs,
.get_eeprom_length = eth_igb_get_eeprom_length,
.get_eeprom = eth_igb_get_eeprom,
@@ -426,7 +425,6 @@ static const struct eth_dev_ops igbvf_eth_dev_ops = {
.rxq_info_get = igb_rxq_info_get,
.txq_info_get = igb_txq_info_get,
.mac_addr_set = igbvf_default_mac_addr_set,
- .get_reg_length = igbvf_get_reg_length,
.get_reg = igbvf_get_regs,
};
@@ -4945,6 +4943,12 @@ eth_igb_get_regs(struct rte_eth_dev *dev,
int count = 0;
const struct reg_info *reg_group;
+ if (data == NULL) {
+ regs->length = eth_igb_get_reg_length(dev);
+ regs->width = sizeof(uint32_t);
+ return 0;
+ }
+
/* Support only full register dump */
if ((regs->length == 0) ||
(regs->length == (uint32_t)eth_igb_get_reg_length(dev))) {
@@ -4969,6 +4973,12 @@ igbvf_get_regs(struct rte_eth_dev *dev,
int count = 0;
const struct reg_info *reg_group;
+ if (data == NULL) {
+ regs->length = igbvf_get_reg_length(dev);
+ regs->width = sizeof(uint32_t);
+ return 0;
+ }
+
/* Support only full register dump */
if ((regs->length == 0) ||
(regs->length == (uint32_t)igbvf_get_reg_length(dev))) {
@@ -5210,5 +5220,7 @@ eth_igb_configure_msix_intr(struct rte_eth_dev *dev)
E1000_WRITE_FLUSH(hw);
}
-PMD_REGISTER_DRIVER(pmd_igb_drv);
-PMD_REGISTER_DRIVER(pmd_igbvf_drv);
+PMD_REGISTER_DRIVER(pmd_igb_drv, igb);
+DRIVER_REGISTER_PCI_TABLE(igb, pci_id_igb_map);
+PMD_REGISTER_DRIVER(pmd_igbvf_drv, igbvf);
+DRIVER_REGISTER_PCI_TABLE(igbvf, pci_id_igbvf_map);
diff --git a/drivers/net/ena/base/ena_com.c b/drivers/net/ena/base/ena_com.c
index a21a9513..a3649d8b 100644
--- a/drivers/net/ena/base/ena_com.c
+++ b/drivers/net/ena/base/ena_com.c
@@ -42,9 +42,6 @@
#define ENA_ASYNC_QUEUE_DEPTH 4
#define ENA_ADMIN_QUEUE_DEPTH 32
-#define ENA_EXTENDED_STAT_GET_FUNCT(_funct_queue) (_funct_queue & 0xFFFF)
-#define ENA_EXTENDED_STAT_GET_QUEUE(_funct_queue) (_funct_queue >> 16)
-
#define MIN_ENA_VER (((ENA_COMMON_SPEC_VERSION_MAJOR) << \
ENA_REGS_VERSION_MAJOR_VERSION_SHIFT) \
| (ENA_COMMON_SPEC_VERSION_MINOR))
@@ -201,12 +198,16 @@ static inline void comp_ctxt_release(struct ena_com_admin_queue *queue,
static struct ena_comp_ctx *get_comp_ctxt(struct ena_com_admin_queue *queue,
u16 command_id, bool capture)
{
- ENA_ASSERT(command_id < queue->q_depth,
- "command id is larger than the queue size. cmd_id: %u queue size %d\n",
- command_id, queue->q_depth);
+ if (unlikely(command_id >= queue->q_depth)) {
+ ena_trc_err("command id is larger than the queue size. cmd_id: %u queue size %d\n",
+ command_id, queue->q_depth);
+ return NULL;
+ }
- ENA_ASSERT(!(queue->comp_ctx[command_id].occupied && capture),
- "Completion context is occupied");
+ if (unlikely(queue->comp_ctx[command_id].occupied && capture)) {
+ ena_trc_err("Completion context is occupied\n");
+ return NULL;
+ }
if (capture) {
ATOMIC32_INC(&queue->outstanding_cmds);
@@ -290,7 +291,8 @@ static inline int ena_com_init_comp_ctxt(struct ena_com_admin_queue *queue)
for (i = 0; i < queue->q_depth; i++) {
comp_ctx = get_comp_ctxt(queue, i, false);
- ENA_WAIT_EVENT_INIT(comp_ctx->wait_event);
+ if (comp_ctx)
+ ENA_WAIT_EVENT_INIT(comp_ctx->wait_event);
}
return 0;
@@ -315,15 +317,21 @@ ena_com_submit_admin_cmd(struct ena_com_admin_queue *admin_queue,
cmd_size_in_bytes,
comp,
comp_size_in_bytes);
+ if (unlikely(IS_ERR(comp_ctx)))
+ admin_queue->running_state = false;
ENA_SPINLOCK_UNLOCK(admin_queue->q_lock, flags);
return comp_ctx;
}
static int ena_com_init_io_sq(struct ena_com_dev *ena_dev,
+ struct ena_com_create_io_ctx *ctx,
struct ena_com_io_sq *io_sq)
{
size_t size;
+ int dev_node;
+
+ ENA_TOUCH(ctx);
memset(&io_sq->desc_addr, 0x0, sizeof(struct ena_com_io_desc_addr));
@@ -334,15 +342,29 @@ static int ena_com_init_io_sq(struct ena_com_dev *ena_dev,
size = io_sq->desc_entry_size * io_sq->q_depth;
- if (io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST)
- ENA_MEM_ALLOC_COHERENT(ena_dev->dmadev,
- size,
- io_sq->desc_addr.virt_addr,
- io_sq->desc_addr.phys_addr,
- io_sq->desc_addr.mem_handle);
- else
- io_sq->desc_addr.virt_addr =
- ENA_MEM_ALLOC(ena_dev->dmadev, size);
+ if (io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST) {
+ ENA_MEM_ALLOC_COHERENT_NODE(ena_dev->dmadev,
+ size,
+ io_sq->desc_addr.virt_addr,
+ io_sq->desc_addr.phys_addr,
+ ctx->numa_node,
+ dev_node);
+ if (!io_sq->desc_addr.virt_addr)
+ ENA_MEM_ALLOC_COHERENT(ena_dev->dmadev,
+ size,
+ io_sq->desc_addr.virt_addr,
+ io_sq->desc_addr.phys_addr,
+ io_sq->desc_addr.mem_handle);
+ } else {
+ ENA_MEM_ALLOC_NODE(ena_dev->dmadev,
+ size,
+ io_sq->desc_addr.virt_addr,
+ ctx->numa_node,
+ dev_node);
+ if (!io_sq->desc_addr.virt_addr)
+ io_sq->desc_addr.virt_addr =
+ ENA_MEM_ALLOC(ena_dev->dmadev, size);
+ }
if (!io_sq->desc_addr.virt_addr) {
ena_trc_err("memory allocation failed");
@@ -357,10 +379,13 @@ static int ena_com_init_io_sq(struct ena_com_dev *ena_dev,
}
static int ena_com_init_io_cq(struct ena_com_dev *ena_dev,
+ struct ena_com_create_io_ctx *ctx,
struct ena_com_io_cq *io_cq)
{
size_t size;
+ int prev_node;
+ ENA_TOUCH(ctx);
memset(&io_cq->cdesc_addr, 0x0, sizeof(struct ena_com_io_desc_addr));
/* Use the basic completion descriptor for Rx */
@@ -371,11 +396,18 @@ static int ena_com_init_io_cq(struct ena_com_dev *ena_dev,
size = io_cq->cdesc_entry_size_in_bytes * io_cq->q_depth;
- ENA_MEM_ALLOC_COHERENT(ena_dev->dmadev,
- size,
- io_cq->cdesc_addr.virt_addr,
- io_cq->cdesc_addr.phys_addr,
- io_cq->cdesc_addr.mem_handle);
+ ENA_MEM_ALLOC_COHERENT_NODE(ena_dev->dmadev,
+ size,
+ io_cq->cdesc_addr.virt_addr,
+ io_cq->cdesc_addr.phys_addr,
+ ctx->numa_node,
+ prev_node);
+ if (!io_cq->cdesc_addr.virt_addr)
+ ENA_MEM_ALLOC_COHERENT(ena_dev->dmadev,
+ size,
+ io_cq->cdesc_addr.virt_addr,
+ io_cq->cdesc_addr.phys_addr,
+ io_cq->cdesc_addr.mem_handle);
if (!io_cq->cdesc_addr.virt_addr) {
ena_trc_err("memory allocation failed");
@@ -399,6 +431,11 @@ ena_com_handle_single_admin_completion(struct ena_com_admin_queue *admin_queue,
ENA_ADMIN_ACQ_COMMON_DESC_COMMAND_ID_MASK;
comp_ctx = get_comp_ctxt(admin_queue, cmd_id, false);
+ if (unlikely(!comp_ctx)) {
+ ena_trc_err("comp_ctx is NULL. Changing the admin queue running state\n");
+ admin_queue->running_state = false;
+ return;
+ }
comp_ctx->status = ENA_CMD_COMPLETED;
comp_ctx->comp_status = cqe->acq_common_descriptor.status;
@@ -615,10 +652,12 @@ static u32 ena_com_reg_bar_read32(struct ena_com_dev *ena_dev, u16 offset)
goto err;
}
- ENA_ASSERT(read_resp->reg_off == offset,
- "Invalid MMIO read return value");
-
- ret = read_resp->reg_val;
+ if (read_resp->reg_off != offset) {
+ ena_trc_err("reading failed for wrong offset value");
+ ret = ENA_MMIO_READ_TIMEOUT;
+ } else {
+ ret = read_resp->reg_val;
+ }
err:
ENA_SPINLOCK_UNLOCK(mmio_read->lock, flags);
@@ -838,7 +877,7 @@ static int ena_com_hash_key_allocate(struct ena_com_dev *ena_dev)
return 0;
}
-static int ena_com_hash_key_destroy(struct ena_com_dev *ena_dev)
+static void ena_com_hash_key_destroy(struct ena_com_dev *ena_dev)
{
struct ena_rss *rss = &ena_dev->rss;
@@ -849,7 +888,6 @@ static int ena_com_hash_key_destroy(struct ena_com_dev *ena_dev)
rss->hash_key_dma_addr,
rss->hash_key_mem_handle);
rss->hash_key = NULL;
- return 0;
}
static int ena_com_hash_ctrl_init(struct ena_com_dev *ena_dev)
@@ -862,10 +900,13 @@ static int ena_com_hash_ctrl_init(struct ena_com_dev *ena_dev)
rss->hash_ctrl_dma_addr,
rss->hash_ctrl_mem_handle);
+ if (unlikely(!rss->hash_ctrl))
+ return ENA_COM_NO_MEM;
+
return 0;
}
-static int ena_com_hash_ctrl_destroy(struct ena_com_dev *ena_dev)
+static void ena_com_hash_ctrl_destroy(struct ena_com_dev *ena_dev)
{
struct ena_rss *rss = &ena_dev->rss;
@@ -876,8 +917,6 @@ static int ena_com_hash_ctrl_destroy(struct ena_com_dev *ena_dev)
rss->hash_ctrl_dma_addr,
rss->hash_ctrl_mem_handle);
rss->hash_ctrl = NULL;
-
- return 0;
}
static int ena_com_indirect_table_allocate(struct ena_com_dev *ena_dev,
@@ -902,7 +941,7 @@ static int ena_com_indirect_table_allocate(struct ena_com_dev *ena_dev,
return ENA_COM_INVAL;
}
- tbl_size = (1 << log_size) *
+ tbl_size = (1ULL << log_size) *
sizeof(struct ena_admin_rss_ind_table_entry);
ENA_MEM_ALLOC_COHERENT(ena_dev->dmadev,
@@ -913,7 +952,7 @@ static int ena_com_indirect_table_allocate(struct ena_com_dev *ena_dev,
if (unlikely(!rss->rss_ind_tbl))
goto mem_err1;
- tbl_size = (1 << log_size) * sizeof(u16);
+ tbl_size = (1ULL << log_size) * sizeof(u16);
rss->host_rss_ind_tbl =
ENA_MEM_ALLOC(ena_dev->dmadev, tbl_size);
if (unlikely(!rss->host_rss_ind_tbl))
@@ -924,7 +963,7 @@ static int ena_com_indirect_table_allocate(struct ena_com_dev *ena_dev,
return 0;
mem_err2:
- tbl_size = (1 << log_size) *
+ tbl_size = (1ULL << log_size) *
sizeof(struct ena_admin_rss_ind_table_entry);
ENA_MEM_FREE_COHERENT(ena_dev->dmadev,
@@ -938,10 +977,10 @@ mem_err1:
return ENA_COM_NO_MEM;
}
-static int ena_com_indirect_table_destroy(struct ena_com_dev *ena_dev)
+static void ena_com_indirect_table_destroy(struct ena_com_dev *ena_dev)
{
struct ena_rss *rss = &ena_dev->rss;
- size_t tbl_size = (1 << rss->tbl_log_size) *
+ size_t tbl_size = (1ULL << rss->tbl_log_size) *
sizeof(struct ena_admin_rss_ind_table_entry);
if (rss->rss_ind_tbl)
@@ -955,8 +994,6 @@ static int ena_com_indirect_table_destroy(struct ena_com_dev *ena_dev)
if (rss->host_rss_ind_tbl)
ENA_MEM_FREE(ena_dev->dmadev, rss->host_rss_ind_tbl);
rss->host_rss_ind_tbl = NULL;
-
- return 0;
}
static int ena_com_create_io_sq(struct ena_com_dev *ena_dev,
@@ -1059,17 +1096,18 @@ static int ena_com_ind_tbl_convert_to_device(struct ena_com_dev *ena_dev)
static int ena_com_ind_tbl_convert_from_device(struct ena_com_dev *ena_dev)
{
- u16 dev_idx_to_host_tbl[ENA_TOTAL_NUM_QUEUES] = { -1 };
+ u16 dev_idx_to_host_tbl[ENA_TOTAL_NUM_QUEUES] = { (u16)-1 };
struct ena_rss *rss = &ena_dev->rss;
- u16 idx, i;
+ u8 idx;
+ u16 i;
for (i = 0; i < ENA_TOTAL_NUM_QUEUES; i++)
dev_idx_to_host_tbl[ena_dev->io_sq_queues[i].idx] = i;
for (i = 0; i < 1 << rss->tbl_log_size; i++) {
- idx = rss->rss_ind_tbl[i].cq_idx;
- if (idx > ENA_TOTAL_NUM_QUEUES)
+ if (rss->rss_ind_tbl[i].cq_idx > ENA_TOTAL_NUM_QUEUES)
return ENA_COM_INVAL;
+ idx = (u8)rss->rss_ind_tbl[i].cq_idx;
if (dev_idx_to_host_tbl[idx] > ENA_TOTAL_NUM_QUEUES)
return ENA_COM_INVAL;
@@ -1097,7 +1135,7 @@ static int ena_com_init_interrupt_moderation_table(struct ena_com_dev *ena_dev)
static void
ena_com_update_intr_delay_resolution(struct ena_com_dev *ena_dev,
- unsigned int intr_delay_resolution)
+ u16 intr_delay_resolution)
{
struct ena_intr_moder_entry *intr_moder_tbl = ena_dev->intr_moder_tbl;
unsigned int i;
@@ -1189,23 +1227,19 @@ int ena_com_create_io_cq(struct ena_com_dev *ena_dev,
}
io_cq->idx = cmd_completion.cq_idx;
- io_cq->db_addr = (u32 __iomem *)((uintptr_t)ena_dev->reg_bar +
- cmd_completion.cq_doorbell_offset);
-
- if (io_cq->q_depth != cmd_completion.cq_actual_depth) {
- ena_trc_err("completion actual queue size (%d) is differ from requested size (%d)\n",
- cmd_completion.cq_actual_depth, io_cq->q_depth);
- ena_com_destroy_io_cq(ena_dev, io_cq);
- return ENA_COM_NO_SPACE;
- }
io_cq->unmask_reg = (u32 __iomem *)((uintptr_t)ena_dev->reg_bar +
- cmd_completion.cq_interrupt_unmask_register);
+ cmd_completion.cq_interrupt_unmask_register_offset);
- if (cmd_completion.cq_head_db_offset)
+ if (cmd_completion.cq_head_db_register_offset)
io_cq->cq_head_db_reg =
(u32 __iomem *)((uintptr_t)ena_dev->reg_bar +
- cmd_completion.cq_head_db_offset);
+ cmd_completion.cq_head_db_register_offset);
+
+ if (cmd_completion.numa_node_register_offset)
+ io_cq->numa_node_cfg_reg =
+ (u32 __iomem *)((uintptr_t)ena_dev->reg_bar +
+ cmd_completion.numa_node_register_offset);
ena_trc_dbg("created cq[%u], depth[%u]\n", io_cq->idx, io_cq->q_depth);
@@ -1239,6 +1273,9 @@ void ena_com_abort_admin_commands(struct ena_com_dev *ena_dev)
for (i = 0; i < admin_queue->q_depth; i++) {
comp_ctx = get_comp_ctxt(admin_queue, i, false);
+ if (unlikely(!comp_ctx))
+ break;
+
comp_ctx->status = ENA_CMD_ABORTED;
ENA_WAIT_EVENT_SIGNAL(comp_ctx->wait_event);
@@ -1304,7 +1341,7 @@ void ena_com_admin_aenq_enable(struct ena_com_dev *ena_dev)
{
u16 depth = ena_dev->aenq.q_depth;
- ENA_ASSERT(ena_dev->aenq.head == depth, "Invliad AENQ state\n");
+ ENA_ASSERT(ena_dev->aenq.head == depth, "Invalid AENQ state\n");
/* Init head_db to mark that all entries in the queue
* are initially available
@@ -1556,7 +1593,7 @@ int ena_com_admin_init(struct ena_com_dev *ena_dev,
if (!(dev_sts & ENA_REGS_DEV_STS_READY_MASK)) {
ena_trc_err("Device isn't ready, abort com init\n");
- return -1;
+ return ENA_COM_NO_DEVICE;
}
admin_queue->q_depth = ENA_ADMIN_QUEUE_DEPTH;
@@ -1631,50 +1668,46 @@ error:
}
int ena_com_create_io_queue(struct ena_com_dev *ena_dev,
- u16 qid,
- enum queue_direction direction,
- enum ena_admin_placement_policy_type mem_queue_type,
- u32 msix_vector,
- u16 queue_size)
+ struct ena_com_create_io_ctx *ctx)
{
struct ena_com_io_sq *io_sq;
struct ena_com_io_cq *io_cq;
int ret = 0;
- if (qid >= ENA_TOTAL_NUM_QUEUES) {
+ if (ctx->qid >= ENA_TOTAL_NUM_QUEUES) {
ena_trc_err("Qid (%d) is bigger than max num of queues (%d)\n",
- qid, ENA_TOTAL_NUM_QUEUES);
+ ctx->qid, ENA_TOTAL_NUM_QUEUES);
return ENA_COM_INVAL;
}
- io_sq = &ena_dev->io_sq_queues[qid];
- io_cq = &ena_dev->io_cq_queues[qid];
+ io_sq = &ena_dev->io_sq_queues[ctx->qid];
+ io_cq = &ena_dev->io_cq_queues[ctx->qid];
memset(io_sq, 0x0, sizeof(struct ena_com_io_sq));
memset(io_cq, 0x0, sizeof(struct ena_com_io_cq));
/* Init CQ */
- io_cq->q_depth = queue_size;
- io_cq->direction = direction;
- io_cq->qid = qid;
+ io_cq->q_depth = ctx->queue_size;
+ io_cq->direction = ctx->direction;
+ io_cq->qid = ctx->qid;
- io_cq->msix_vector = msix_vector;
+ io_cq->msix_vector = ctx->msix_vector;
- io_sq->q_depth = queue_size;
- io_sq->direction = direction;
- io_sq->qid = qid;
+ io_sq->q_depth = ctx->queue_size;
+ io_sq->direction = ctx->direction;
+ io_sq->qid = ctx->qid;
- io_sq->mem_queue_type = mem_queue_type;
+ io_sq->mem_queue_type = ctx->mem_queue_type;
- if (direction == ENA_COM_IO_QUEUE_DIRECTION_TX)
+ if (ctx->direction == ENA_COM_IO_QUEUE_DIRECTION_TX)
/* header length is limited to 8 bits */
io_sq->tx_max_header_size =
- ENA_MIN16(ena_dev->tx_max_header_size, SZ_256);
+ ENA_MIN32(ena_dev->tx_max_header_size, SZ_256);
- ret = ena_com_init_io_sq(ena_dev, io_sq);
+ ret = ena_com_init_io_sq(ena_dev, ctx, io_sq);
if (ret)
goto error;
- ret = ena_com_init_io_cq(ena_dev, io_cq);
+ ret = ena_com_init_io_cq(ena_dev, ctx, io_cq);
if (ret)
goto error;
@@ -1840,22 +1873,6 @@ void ena_com_aenq_intr_handler(struct ena_com_dev *dev, void *data)
+ ENA_REGS_AENQ_HEAD_DB_OFF);
}
-/* Sets the function Idx and Queue Idx to be used for
- * get full statistics feature
- */
-int ena_com_extended_stats_set_func_queue(struct ena_com_dev *ena_dev,
- u32 func_queue)
-{
- /* Function & Queue is acquired from user in the following format :
- * Bottom Half word: funct
- * Top Half Word: queue
- */
- ena_dev->stats_func = ENA_EXTENDED_STAT_GET_FUNCT(func_queue);
- ena_dev->stats_queue = ENA_EXTENDED_STAT_GET_QUEUE(func_queue);
-
- return 0;
-}
-
int ena_com_dev_reset(struct ena_com_dev *ena_dev)
{
u32 stat, timeout, cap, reset_val;
@@ -2195,7 +2212,7 @@ int ena_com_get_hash_function(struct ena_com_dev *ena_dev,
*func = rss->hash_func;
if (key)
- memcpy(key, hash_key->key, hash_key->keys_num << 2);
+ memcpy(key, hash_key->key, (size_t)(hash_key->keys_num) << 2);
return 0;
}
@@ -2337,7 +2354,7 @@ int ena_com_fill_hash_ctrl(struct ena_com_dev *ena_dev,
u16 supported_fields;
int rc;
- if (proto > ENA_ADMIN_RSS_PROTO_NUM) {
+ if (proto >= ENA_ADMIN_RSS_PROTO_NUM) {
ena_trc_err("Invalid proto num (%u)\n", proto);
return ENA_COM_INVAL;
}
@@ -2420,7 +2437,7 @@ int ena_com_indirect_table_set(struct ena_com_dev *ena_dev)
return ret;
}
- cmd.control_buffer.length = (1 << rss->tbl_log_size) *
+ cmd.control_buffer.length = (1ULL << rss->tbl_log_size) *
sizeof(struct ena_admin_rss_ind_table_entry);
ret = ena_com_execute_admin_command(admin_queue,
@@ -2444,7 +2461,7 @@ int ena_com_indirect_table_get(struct ena_com_dev *ena_dev, u32 *ind_tbl)
u32 tbl_size;
int i, rc;
- tbl_size = (1 << rss->tbl_log_size) *
+ tbl_size = (1ULL << rss->tbl_log_size) *
sizeof(struct ena_admin_rss_ind_table_entry);
rc = ena_com_get_feature_ex(ena_dev, &get_resp,
@@ -2496,22 +2513,18 @@ err_indr_tbl:
return rc;
}
-int ena_com_rss_destroy(struct ena_com_dev *ena_dev)
+void ena_com_rss_destroy(struct ena_com_dev *ena_dev)
{
ena_com_indirect_table_destroy(ena_dev);
ena_com_hash_key_destroy(ena_dev);
ena_com_hash_ctrl_destroy(ena_dev);
memset(&ena_dev->rss, 0x0, sizeof(ena_dev->rss));
-
- return 0;
}
-int ena_com_allocate_host_attribute(struct ena_com_dev *ena_dev,
- u32 debug_area_size)
+int ena_com_allocate_host_info(struct ena_com_dev *ena_dev)
{
struct ena_host_attribute *host_attr = &ena_dev->host_attr;
- int rc;
ENA_MEM_ALLOC_COHERENT(ena_dev->dmadev,
SZ_4K,
@@ -2521,33 +2534,29 @@ int ena_com_allocate_host_attribute(struct ena_com_dev *ena_dev,
if (unlikely(!host_attr->host_info))
return ENA_COM_NO_MEM;
- if (debug_area_size) {
+ return 0;
+}
+
+int ena_com_allocate_debug_area(struct ena_com_dev *ena_dev,
+ u32 debug_area_size) {
+ struct ena_host_attribute *host_attr = &ena_dev->host_attr;
+
ENA_MEM_ALLOC_COHERENT(ena_dev->dmadev,
debug_area_size,
host_attr->debug_area_virt_addr,
host_attr->debug_area_dma_addr,
host_attr->debug_area_dma_handle);
if (unlikely(!host_attr->debug_area_virt_addr)) {
- rc = ENA_COM_NO_MEM;
- goto err;
- }
+ host_attr->debug_area_size = 0;
+ return ENA_COM_NO_MEM;
}
host_attr->debug_area_size = debug_area_size;
return 0;
-err:
-
- ENA_MEM_FREE_COHERENT(ena_dev->dmadev,
- SZ_4K,
- host_attr->host_info,
- host_attr->host_info_dma_addr,
- host_attr->host_info_dma_handle);
- host_attr->host_info = NULL;
- return rc;
}
-void ena_com_delete_host_attribute(struct ena_com_dev *ena_dev)
+void ena_com_delete_host_info(struct ena_com_dev *ena_dev)
{
struct ena_host_attribute *host_attr = &ena_dev->host_attr;
@@ -2559,6 +2568,11 @@ void ena_com_delete_host_attribute(struct ena_com_dev *ena_dev)
host_attr->host_info_dma_handle);
host_attr->host_info = NULL;
}
+}
+
+void ena_com_delete_debug_area(struct ena_com_dev *ena_dev)
+{
+ struct ena_host_attribute *host_attr = &ena_dev->host_attr;
if (host_attr->debug_area_virt_addr) {
ENA_MEM_FREE_COHERENT(ena_dev->dmadev,
@@ -2677,7 +2691,7 @@ void ena_com_destroy_interrupt_moderation(struct ena_com_dev *ena_dev)
int ena_com_init_interrupt_moderation(struct ena_com_dev *ena_dev)
{
struct ena_admin_get_feat_resp get_resp;
- u32 delay_resolution;
+ u16 delay_resolution;
int rc;
rc = ena_com_get_feature(ena_dev, &get_resp,
diff --git a/drivers/net/ena/base/ena_com.h b/drivers/net/ena/base/ena_com.h
index 19e53ffb..e5345926 100644
--- a/drivers/net/ena/base/ena_com.h
+++ b/drivers/net/ena/base/ena_com.h
@@ -120,8 +120,8 @@ struct ena_com_rx_buf_info {
};
struct ena_com_io_desc_addr {
- void __iomem *pbuf_dev_addr; /* LLQ address */
- void *virt_addr;
+ u8 __iomem *pbuf_dev_addr; /* LLQ address */
+ u8 *virt_addr;
dma_addr_t phys_addr;
ena_mem_handle_t mem_handle;
};
@@ -138,13 +138,14 @@ struct ena_com_tx_meta {
struct ena_com_io_cq {
struct ena_com_io_desc_addr cdesc_addr;
- u32 __iomem *db_addr;
-
/* Interrupt unmask register */
u32 __iomem *unmask_reg;
/* The completion queue head doorbell register */
- uint32_t __iomem *cq_head_db_reg;
+ u32 __iomem *cq_head_db_reg;
+
+ /* numa configuration register (for TPH) */
+ u32 __iomem *numa_node_cfg_reg;
/* The value to write to the above register to unmask
* the interrupt of this queue
@@ -189,7 +190,7 @@ struct ena_com_io_sq {
u16 idx;
u16 tail;
u16 next_to_comp;
- u16 tx_max_header_size;
+ u32 tx_max_header_size;
u8 phase;
u8 desc_entry_size;
u8 dma_addr_bits;
@@ -312,17 +313,15 @@ struct ena_com_dev {
struct ena_com_aenq aenq;
struct ena_com_io_cq io_cq_queues[ENA_TOTAL_NUM_QUEUES];
struct ena_com_io_sq io_sq_queues[ENA_TOTAL_NUM_QUEUES];
- void __iomem *reg_bar;
+ u8 __iomem *reg_bar;
void __iomem *mem_bar;
void *dmadev;
enum ena_admin_placement_policy_type tx_mem_queue_type;
-
+ u32 tx_max_header_size;
u16 stats_func; /* Selected function for extended statistic dump */
u16 stats_queue; /* Selected queue for extended statistic dump */
- u16 tx_max_header_size;
-
struct ena_com_mmio_read mmio_read;
struct ena_rss rss;
@@ -343,6 +342,15 @@ struct ena_com_dev_get_features_ctx {
struct ena_admin_feature_offload_desc offload;
};
+struct ena_com_create_io_ctx {
+ enum ena_admin_placement_policy_type mem_queue_type;
+ enum queue_direction direction;
+ int numa_node;
+ u32 msix_vector;
+ u16 queue_size;
+ u16 qid;
+};
+
typedef void (*ena_aenq_handler)(void *data,
struct ena_admin_aenq_entry *aenq_e);
@@ -420,22 +428,14 @@ int ena_com_dev_reset(struct ena_com_dev *ena_dev);
/* ena_com_create_io_queue - Create io queue.
* @ena_dev: ENA communication layer struct
- * @qid - the caller virtual queue id.
- * @direction - the queue direction (Rx/Tx)
- * @mem_queue_type - Indicate if this queue is LLQ or regular queue
- * (relevant only for Tx queue)
- * @msix_vector - MSI-X vector
- * @queue_size - queue size
+ * ena_com_create_io_ctx - create context structure
*
- * Create the submission and the completion queues for queue id - qid.
+ * Create the submission and the completion queues.
*
* @return - 0 on success, negative value on failure.
*/
-int ena_com_create_io_queue(struct ena_com_dev *ena_dev, u16 qid,
- enum queue_direction direction,
- enum ena_admin_placement_policy_type mem_queue_type,
- u32 msix_vector,
- u16 queue_size);
+int ena_com_create_io_queue(struct ena_com_dev *ena_dev,
+ struct ena_com_create_io_ctx *ctx);
/* ena_com_admin_destroy - Destroy IO queue with the queue id - qid.
* @ena_dev: ENA communication layer struct
@@ -519,7 +519,7 @@ void ena_com_aenq_intr_handler(struct ena_com_dev *dev, void *data);
* @ena_dev: ENA communication layer struct
*
* This method aborts all the outstanding admin commands.
- * The called should then call ena_com_wait_for_abort_completion to make sure
+ * The caller should then call ena_com_wait_for_abort_completion to make sure
* all the commands were completed.
*/
void ena_com_abort_admin_commands(struct ena_com_dev *ena_dev);
@@ -628,10 +628,8 @@ int ena_com_rss_init(struct ena_com_dev *ena_dev, u16 log_size);
* @ena_dev: ENA communication layer struct
*
* Free all the RSS/RFS resources.
- *
- * @return: 0 on Success and negative value otherwise.
*/
-int ena_com_rss_destroy(struct ena_com_dev *ena_dev);
+void ena_com_rss_destroy(struct ena_com_dev *ena_dev);
/* ena_com_fill_hash_function - Fill RSS hash function
* @ena_dev: ENA communication layer struct
@@ -774,26 +772,38 @@ int ena_com_indirect_table_set(struct ena_com_dev *ena_dev);
*/
int ena_com_indirect_table_get(struct ena_com_dev *ena_dev, u32 *ind_tbl);
-/* ena_com_allocate_host_attribute - Allocate host attributes resources.
+/* ena_com_allocate_host_info - Allocate host info resources.
* @ena_dev: ENA communication layer struct
- * @debug_area_size: Debug aread size
*
- * Allocate host info and debug area.
+ * @return: 0 on Success and negative value otherwise.
+ */
+int ena_com_allocate_host_info(struct ena_com_dev *ena_dev);
+
+/* ena_com_allocate_debug_area - Allocate debug area.
+ * @ena_dev: ENA communication layer struct
+ * @debug_area_size - debug area size.
*
* @return: 0 on Success and negative value otherwise.
*/
-int ena_com_allocate_host_attribute(struct ena_com_dev *ena_dev,
- u32 debug_area_size);
+int ena_com_allocate_debug_area(struct ena_com_dev *ena_dev,
+ u32 debug_area_size);
+
+/* ena_com_delete_debug_area - Free the debug area resources.
+ * @ena_dev: ENA communication layer struct
+ *
+ * Free the allocate debug area.
+ */
+void ena_com_delete_debug_area(struct ena_com_dev *ena_dev);
-/* ena_com_allocate_host_attribute - Free the host attributes resources.
+/* ena_com_delete_host_info - Free the host info resources.
* @ena_dev: ENA communication layer struct
*
- * Free the allocate host info and debug area.
+ * Free the allocate host info.
*/
-void ena_com_delete_host_attribute(struct ena_com_dev *ena_dev);
+void ena_com_delete_host_info(struct ena_com_dev *ena_dev);
/* ena_com_set_host_attributes - Update the device with the host
- * attributes base address.
+ * attributes (debug area and host info) base address.
* @ena_dev: ENA communication layer struct
*
* @return: 0 on Success and negative value otherwise.
@@ -979,7 +989,7 @@ ena_com_calculate_interrupt_delay(struct ena_com_dev *ena_dev,
*/
return;
- curr_moder_idx = (enum ena_intr_moder_level)*moder_tbl_idx;
+ curr_moder_idx = (enum ena_intr_moder_level)(*moder_tbl_idx);
if (unlikely(curr_moder_idx >= ENA_INTR_MAX_NUM_OF_LEVELS)) {
ena_trc_err("Wrong moderation index %u\n", curr_moder_idx);
return;
diff --git a/drivers/net/ena/base/ena_defs/ena_admin_defs.h b/drivers/net/ena/base/ena_defs/ena_admin_defs.h
index fe412469..7a031d90 100644
--- a/drivers/net/ena/base/ena_defs/ena_admin_defs.h
+++ b/drivers/net/ena/base/ena_defs/ena_admin_defs.h
@@ -58,30 +58,6 @@ enum ena_admin_aq_opcode {
ENA_ADMIN_GET_STATS = 11,
};
-/* privileged amdin commands opcodes */
-enum ena_admin_aq_opcode_privileged {
- /* get device capabilities */
- ENA_ADMIN_IDENTIFY = 48,
-
- /* configure device */
- ENA_ADMIN_CONFIGURE_PF_DEVICE = 49,
-
- /* setup SRIOV PCIe Virtual Function capabilities */
- ENA_ADMIN_SETUP_VF = 50,
-
- /* load firmware to the controller */
- ENA_ADMIN_LOAD_FIRMWARE = 52,
-
- /* commit previously loaded firmare */
- ENA_ADMIN_COMMIT_FIRMWARE = 53,
-
- /* quiesce virtual function */
- ENA_ADMIN_QUIESCE_VF = 54,
-
- /* load virtual function from migrates context */
- ENA_ADMIN_MIGRATE_VF = 55,
-};
-
/* admin command completion status codes */
enum ena_admin_aq_completion_status {
/* Request completed successfully */
@@ -116,25 +92,6 @@ enum ena_admin_aq_feature_id {
/* max number of supported queues per for every queues type */
ENA_ADMIN_MAX_QUEUES_NUM = 2,
- /* low latency queues capabilities (max entry size, depth) */
- ENA_ADMIN_LLQ_CONFIG = 3,
-
- /* power management capabilities */
- ENA_ADMIN_POWER_MANAGEMENT_CONFIG = 4,
-
- /* MAC address filters support, multicast, broadcast, and
- * promiscuous
- */
- ENA_ADMIN_MAC_FILTERS_CONFIG = 5,
-
- /* VLAN membership, frame format, etc. */
- ENA_ADMIN_VLAN_CONFIG = 6,
-
- /* Available size for various on-chip memory resources, accessible
- * by the driver
- */
- ENA_ADMIN_ON_DEVICE_MEMORY_CONFIG = 7,
-
/* Receive Side Scaling (RSS) function */
ENA_ADMIN_RSS_HASH_FUNCTION = 10,
@@ -150,20 +107,9 @@ enum ena_admin_aq_feature_id {
/* Receive Side Scaling (RSS) hash input */
ENA_ADMIN_RSS_HASH_INPUT = 18,
- /* overlay tunnels configuration */
- ENA_ADMIN_TUNNEL_CONFIG = 19,
-
/* interrupt moderation parameters */
ENA_ADMIN_INTERRUPT_MODERATION = 20,
- /* 1588v2 and Timing configuration */
- ENA_ADMIN_1588_CONFIG = 21,
-
- /* Packet Header format templates configuration for input and
- * output parsers
- */
- ENA_ADMIN_PKT_HEADER_TEMPLATES_CONFIG = 23,
-
/* AENQ configuration */
ENA_ADMIN_AENQ_CONFIG = 26,
@@ -440,9 +386,7 @@ struct ena_admin_acq_create_sq_resp_desc {
uint16_t reserved;
- /* word 3 : queue doorbell address as and offset to PCIe MMIO REG
- * BAR
- */
+ /* word 3 : queue doorbell address as an offset to PCIe MMIO REG BAR */
uint32_t sq_doorbell_offset;
/* word 4 : low latency queue ring base address as an offset to
@@ -520,18 +464,18 @@ struct ena_admin_acq_create_cq_resp_desc {
/* actual cq depth in # of entries */
uint16_t cq_actual_depth;
- /* word 3 : doorbell address as an offset to PCIe MMIO REG BAR */
- uint32_t cq_doorbell_offset;
+ /* word 3 : cpu numa node address as an offset to PCIe MMIO REG BAR */
+ uint32_t numa_node_register_offset;
/* word 4 : completion head doorbell address as an offset to PCIe
* MMIO REG BAR
*/
- uint32_t cq_head_db_offset;
+ uint32_t cq_head_db_register_offset;
/* word 5 : interrupt unmask register address as an offset into
* PCIe MMIO REG BAR
*/
- uint32_t cq_interrupt_unmask_register;
+ uint32_t cq_interrupt_unmask_register_offset;
};
/* ENA AQ Destroy Completion Queue command. Placed in control buffer
@@ -724,7 +668,7 @@ struct ena_admin_queue_feature_desc {
/* ENA MTU Set Feature descriptor. */
struct ena_admin_set_feature_mtu_desc {
- /* word 0 : mtu size including L2 */
+ /* word 0 : mtu payload size (exclude L2) */
uint32_t mtu;
};
@@ -913,10 +857,7 @@ struct ena_admin_proto_input {
/* flow hash fields (bitwise according to ena_admin_flow_hash_fields) */
uint16_t fields;
- /* 0 : inner - for tunneled packet, select the fields
- * from inner header
- */
- uint16_t flags;
+ uint16_t reserved2;
};
/* ENA RSS hash control buffer structure */
@@ -927,11 +868,9 @@ struct ena_admin_feature_rss_hash_control {
/* selected input fields */
struct ena_admin_proto_input selected_fields[ENA_ADMIN_RSS_PROTO_NUM];
- /* supported input fields for inner header */
- struct ena_admin_proto_input supported_inner_fields[ENA_ADMIN_RSS_PROTO_NUM];
+ struct ena_admin_proto_input reserved2[ENA_ADMIN_RSS_PROTO_NUM];
- /* selected input fields */
- struct ena_admin_proto_input selected_inner_fields[ENA_ADMIN_RSS_PROTO_NUM];
+ struct ena_admin_proto_input reserved3[ENA_ADMIN_RSS_PROTO_NUM];
};
/* ENA RSS flow hash input */
@@ -966,10 +905,10 @@ enum ena_admin_os_type {
ENA_ADMIN_OS_DPDK = 3,
/* FreeBSD OS */
- ENA_ADMIN_OS_FREE_BSD = 4,
+ ENA_ADMIN_OS_FREEBSD = 4,
/* PXE OS */
- ENA_ADMIN_OS_PXE = 5,
+ ENA_ADMIN_OS_IPXE = 5,
};
/* host info */
@@ -1284,9 +1223,6 @@ struct ena_admin_ena_mmio_req_read_less_resp {
#define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_SELECTED_FUNC_MASK \
GENMASK(7, 0)
-/* proto_input */
-#define ENA_ADMIN_PROTO_INPUT_INNER_MASK BIT(0)
-
/* feature_rss_flow_hash_input */
#define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_SHIFT 1
#define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_MASK BIT(1)
@@ -1816,34 +1752,21 @@ set_ena_admin_feature_rss_flow_hash_function_selected_func(
}
static inline uint16_t
-get_ena_admin_proto_input_inner(const struct ena_admin_proto_input *p)
-{
- return p->flags & ENA_ADMIN_PROTO_INPUT_INNER_MASK;
-}
-
-static inline void
-set_ena_admin_proto_input_inner(struct ena_admin_proto_input *p, uint16_t val)
-{
- p->flags |= val & ENA_ADMIN_PROTO_INPUT_INNER_MASK;
-}
-
-static inline uint16_t
get_ena_admin_feature_rss_flow_hash_input_L3_sort(
const struct ena_admin_feature_rss_flow_hash_input *p)
{
return (p->supported_input_sort &
- ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_MASK)
+ ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_MASK)
>> ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_SHIFT;
}
static inline void
set_ena_admin_feature_rss_flow_hash_input_L3_sort(
- struct ena_admin_feature_rss_flow_hash_input *p,
- uint16_t val)
+ struct ena_admin_feature_rss_flow_hash_input *p, uint16_t val)
{
p->supported_input_sort |=
(val << ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_SHIFT)
- & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_MASK;
+ & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_MASK;
}
static inline uint16_t
@@ -1862,7 +1785,7 @@ set_ena_admin_feature_rss_flow_hash_input_L4_sort(
{
p->supported_input_sort |=
(val << ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_SHIFT)
- & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_MASK;
+ & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_MASK;
}
static inline uint16_t
diff --git a/drivers/net/ena/base/ena_defs/ena_eth_io_defs.h b/drivers/net/ena/base/ena_defs/ena_eth_io_defs.h
index a547033d..6bc3d6a7 100644
--- a/drivers/net/ena/base/ena_defs/ena_eth_io_defs.h
+++ b/drivers/net/ena/base/ena_defs/ena_eth_io_defs.h
@@ -87,28 +87,17 @@ struct ena_eth_io_tx_desc {
/* word 1 : */
/* ethernet control
- * 3:0 : l3_proto_idx - L3 protocol, if
- * tunnel_ctrl[0] is set, then this is the inner
- * packet L3. This field required when
- * l3_csum_en,l3_csum or tso_en are set.
+ * 3:0 : l3_proto_idx - L3 protocol. This field
+ * required when l3_csum_en,l3_csum or tso_en are set.
* 4 : DF - IPv4 DF, must be 0 if packet is IPv4 and
* DF flags of the IPv4 header is 0. Otherwise must
* be set to 1
* 6:5 : reserved5
- * 7 : tso_en - Enable TSO, For TCP only. For packets
- * with tunnel (tunnel_ctrl[0]=1), then the inner
- * packet will be segmented while the outer tunnel is
- * duplicated
- * 12:8 : l4_proto_idx - L4 protocol, if
- * tunnel_ctrl[0] is set, then this is the inner
- * packet L4. This field need to be set when
- * l4_csum_en or tso_en are set.
- * 13 : l3_csum_en - enable IPv4 header checksum. if
- * tunnel_ctrl[0] is set, then this will enable
- * checksum for the inner packet IPv4
- * 14 : l4_csum_en - enable TCP/UDP checksum. if
- * tunnel_ctrl[0] is set, then this will enable
- * checksum on the inner packet TCP/UDP checksum
+ * 7 : tso_en - Enable TSO, For TCP only.
+ * 12:8 : l4_proto_idx - L4 protocol. This field need
+ * to be set when l4_csum_en or tso_en are set.
+ * 13 : l3_csum_en - enable IPv4 header checksum.
+ * 14 : l4_csum_en - enable TCP/UDP checksum.
* 15 : ethernet_fcs_dis - when set, the controller
* will not append the 802.3 Ethernet Frame Check
* Sequence to the packet
@@ -124,11 +113,8 @@ struct ena_eth_io_tx_desc {
* must not include the tcp length field. L4 partial
* checksum should be used for IPv6 packet that
* contains Routing Headers.
- * 20:18 : tunnel_ctrl - Bit 0: tunneling exists, Bit
- * 1: tunnel packet actually uses UDP as L4, Bit 2:
- * tunnel packet L3 protocol: 0: IPv4 1: IPv6
- * 21 : ts_req - Indicates that the packet is IEEE
- * 1588v2 packet requiring the timestamp
+ * 20:18 : reserved18 - MBZ
+ * 21 : reserved21 - MBZ
* 31:22 : req_id_lo - Request ID[9:0]
*/
uint32_t meta_ctrl;
@@ -160,9 +146,7 @@ struct ena_eth_io_tx_meta_desc {
/* word 0 : */
/* length, request id and control flags
* 9:0 : req_id_lo - Request ID[9:0]
- * 11:10 : outr_l3_off_hi - valid if
- * tunnel_ctrl[0]=1. bits[4:3] of outer packet L3
- * offset
+ * 11:10 : reserved10 - MBZ
* 12 : reserved12 - MBZ
* 13 : reserved13 - MBZ
* 14 : ext_valid - if set, offset fields in Word2
@@ -201,35 +185,19 @@ struct ena_eth_io_tx_meta_desc {
/* word 2 : */
/* word 2
* 7:0 : l3_hdr_len - the header length L3 IP header.
- * if tunnel_ctrl[0]=1, this is the IP header length
- * of the inner packet. FIXME - check if includes IP
- * options hdr_len
* 15:8 : l3_hdr_off - the offset of the first byte
* in the L3 header from the beginning of the to-be
- * transmitted packet. if tunnel_ctrl[0]=1, this is
- * the offset the L3 header of the inner packet
+ * transmitted packet.
* 21:16 : l4_hdr_len_in_words - counts the L4 header
* length in words. there is an explicit assumption
* that L4 header appears right after L3 header and
- * L4 offset is based on l3_hdr_off+l3_hdr_len FIXME
- * - pls confirm
+ * L4 offset is based on l3_hdr_off+l3_hdr_len
* 31:22 : mss_lo
*/
uint32_t word2;
/* word 3 : */
- /* word 3
- * 23:0 : crypto_info
- * 28:24 : outr_l3_hdr_len_words - valid if
- * tunnel_ctrl[0]=1. Counts in words
- * 31:29 : outr_l3_off_lo - valid if
- * tunnel_ctrl[0]=1. bits[2:0] of outer packet L3
- * offset. Counts the offset of the tunnel IP header
- * from beginning of the packet. NOTE: if the tunnel
- * header requires CRC or checksum, it is expected to
- * be done by the driver as it is not done by the HW
- */
- uint32_t word3;
+ uint32_t reserved;
};
/* ENA IO Queue Tx completions descriptor */
@@ -298,36 +266,26 @@ struct ena_eth_io_rx_cdesc_base {
/* word 0 : */
/* 4:0 : l3_proto_idx - L3 protocol index
* 6:5 : src_vlan_cnt - Source VLAN count
- * 7 : tunnel - Tunnel exists
+ * 7 : reserved7 - MBZ
* 12:8 : l4_proto_idx - L4 protocol index
* 13 : l3_csum_err - when set, either the L3
* checksum error detected, or, the controller didn't
- * validate the checksum, If tunnel exists, this
- * result is for the inner packet. This bit is valid
- * only when l3_proto_idx indicates IPv4 packet
+ * validate the checksum. This bit is valid only when
+ * l3_proto_idx indicates IPv4 packet
* 14 : l4_csum_err - when set, either the L4
* checksum error detected, or, the controller didn't
- * validate the checksum. If tunnel exists, this
- * result is for the inner packet. This bit is valid
- * only when l4_proto_idx indicates TCP/UDP packet,
- * and, ipv4_frag is not set
+ * validate the checksum. This bit is valid only when
+ * l4_proto_idx indicates TCP/UDP packet, and,
+ * ipv4_frag is not set
* 15 : ipv4_frag - Indicates IPv4 fragmented packet
- * 17:16 : reserved16
- * 19:18 : reserved18
- * 20 : secured_pkt - Set if packet was handled by
- * inline crypto engine
- * 22:21 : crypto_status - bit 0 secured direction:
- * 0: decryption, 1: encryption. bit 1 reserved
- * 23 : reserved23
+ * 23:16 : reserved16
* 24 : phase
* 25 : l3_csum2 - second checksum engine result
* 26 : first - Indicates first descriptor in
* transaction
* 27 : last - Indicates last descriptor in
* transaction
- * 28 : inr_l4_csum - TCP/UDP checksum results for
- * inner packet
- * 29 : reserved29
+ * 29:28 : reserved28
* 30 : buffer - 0: Metadata descriptor. 1: Buffer
* Descriptor was used
* 31 : reserved31
@@ -381,6 +339,16 @@ struct ena_eth_io_intr_reg {
uint32_t intr_control;
};
+/* ENA NUMA Node configuration register */
+struct ena_eth_io_numa_node_cfg_reg {
+ /* word 0 : */
+ /* 7:0 : numa
+ * 30:8 : reserved
+ * 31 : enabled
+ */
+ uint32_t numa_cfg;
+};
+
/* tx_desc */
#define ENA_ETH_IO_TX_DESC_LENGTH_MASK GENMASK(15, 0)
#define ENA_ETH_IO_TX_DESC_REQ_ID_HI_SHIFT 16
@@ -410,10 +378,6 @@ struct ena_eth_io_intr_reg {
#define ENA_ETH_IO_TX_DESC_ETHERNET_FCS_DIS_MASK BIT(15)
#define ENA_ETH_IO_TX_DESC_L4_CSUM_PARTIAL_SHIFT 17
#define ENA_ETH_IO_TX_DESC_L4_CSUM_PARTIAL_MASK BIT(17)
-#define ENA_ETH_IO_TX_DESC_TUNNEL_CTRL_SHIFT 18
-#define ENA_ETH_IO_TX_DESC_TUNNEL_CTRL_MASK GENMASK(20, 18)
-#define ENA_ETH_IO_TX_DESC_TS_REQ_SHIFT 21
-#define ENA_ETH_IO_TX_DESC_TS_REQ_MASK BIT(21)
#define ENA_ETH_IO_TX_DESC_REQ_ID_LO_SHIFT 22
#define ENA_ETH_IO_TX_DESC_REQ_ID_LO_MASK GENMASK(31, 22)
#define ENA_ETH_IO_TX_DESC_ADDR_HI_MASK GENMASK(15, 0)
@@ -422,8 +386,6 @@ struct ena_eth_io_intr_reg {
/* tx_meta_desc */
#define ENA_ETH_IO_TX_META_DESC_REQ_ID_LO_MASK GENMASK(9, 0)
-#define ENA_ETH_IO_TX_META_DESC_OUTR_L3_OFF_HI_SHIFT 10
-#define ENA_ETH_IO_TX_META_DESC_OUTR_L3_OFF_HI_MASK GENMASK(11, 10)
#define ENA_ETH_IO_TX_META_DESC_EXT_VALID_SHIFT 14
#define ENA_ETH_IO_TX_META_DESC_EXT_VALID_MASK BIT(14)
#define ENA_ETH_IO_TX_META_DESC_WORD3_VALID_SHIFT 15
@@ -452,11 +414,6 @@ struct ena_eth_io_intr_reg {
#define ENA_ETH_IO_TX_META_DESC_L4_HDR_LEN_IN_WORDS_MASK GENMASK(21, 16)
#define ENA_ETH_IO_TX_META_DESC_MSS_LO_SHIFT 22
#define ENA_ETH_IO_TX_META_DESC_MSS_LO_MASK GENMASK(31, 22)
-#define ENA_ETH_IO_TX_META_DESC_CRYPTO_INFO_MASK GENMASK(23, 0)
-#define ENA_ETH_IO_TX_META_DESC_OUTR_L3_HDR_LEN_WORDS_SHIFT 24
-#define ENA_ETH_IO_TX_META_DESC_OUTR_L3_HDR_LEN_WORDS_MASK GENMASK(28, 24)
-#define ENA_ETH_IO_TX_META_DESC_OUTR_L3_OFF_LO_SHIFT 29
-#define ENA_ETH_IO_TX_META_DESC_OUTR_L3_OFF_LO_MASK GENMASK(31, 29)
/* tx_cdesc */
#define ENA_ETH_IO_TX_CDESC_PHASE_MASK BIT(0)
@@ -474,8 +431,6 @@ struct ena_eth_io_intr_reg {
#define ENA_ETH_IO_RX_CDESC_BASE_L3_PROTO_IDX_MASK GENMASK(4, 0)
#define ENA_ETH_IO_RX_CDESC_BASE_SRC_VLAN_CNT_SHIFT 5
#define ENA_ETH_IO_RX_CDESC_BASE_SRC_VLAN_CNT_MASK GENMASK(6, 5)
-#define ENA_ETH_IO_RX_CDESC_BASE_TUNNEL_SHIFT 7
-#define ENA_ETH_IO_RX_CDESC_BASE_TUNNEL_MASK BIT(7)
#define ENA_ETH_IO_RX_CDESC_BASE_L4_PROTO_IDX_SHIFT 8
#define ENA_ETH_IO_RX_CDESC_BASE_L4_PROTO_IDX_MASK GENMASK(12, 8)
#define ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM_ERR_SHIFT 13
@@ -484,10 +439,6 @@ struct ena_eth_io_intr_reg {
#define ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_ERR_MASK BIT(14)
#define ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_SHIFT 15
#define ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_MASK BIT(15)
-#define ENA_ETH_IO_RX_CDESC_BASE_SECURED_PKT_SHIFT 20
-#define ENA_ETH_IO_RX_CDESC_BASE_SECURED_PKT_MASK BIT(20)
-#define ENA_ETH_IO_RX_CDESC_BASE_CRYPTO_STATUS_SHIFT 21
-#define ENA_ETH_IO_RX_CDESC_BASE_CRYPTO_STATUS_MASK GENMASK(22, 21)
#define ENA_ETH_IO_RX_CDESC_BASE_PHASE_SHIFT 24
#define ENA_ETH_IO_RX_CDESC_BASE_PHASE_MASK BIT(24)
#define ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM2_SHIFT 25
@@ -496,8 +447,6 @@ struct ena_eth_io_intr_reg {
#define ENA_ETH_IO_RX_CDESC_BASE_FIRST_MASK BIT(26)
#define ENA_ETH_IO_RX_CDESC_BASE_LAST_SHIFT 27
#define ENA_ETH_IO_RX_CDESC_BASE_LAST_MASK BIT(27)
-#define ENA_ETH_IO_RX_CDESC_BASE_INR_L4_CSUM_SHIFT 28
-#define ENA_ETH_IO_RX_CDESC_BASE_INR_L4_CSUM_MASK BIT(28)
#define ENA_ETH_IO_RX_CDESC_BASE_BUFFER_SHIFT 30
#define ENA_ETH_IO_RX_CDESC_BASE_BUFFER_MASK BIT(30)
@@ -508,6 +457,11 @@ struct ena_eth_io_intr_reg {
#define ENA_ETH_IO_INTR_REG_INTR_UNMASK_SHIFT 30
#define ENA_ETH_IO_INTR_REG_INTR_UNMASK_MASK BIT(30)
+/* numa_node_cfg_reg */
+#define ENA_ETH_IO_NUMA_NODE_CFG_REG_NUMA_MASK GENMASK(7, 0)
+#define ENA_ETH_IO_NUMA_NODE_CFG_REG_ENABLED_SHIFT 31
+#define ENA_ETH_IO_NUMA_NODE_CFG_REG_ENABLED_MASK BIT(31)
+
#if !defined(ENA_DEFS_LINUX_MAINLINE)
static inline uint32_t get_ena_eth_io_tx_desc_length(
const struct ena_eth_io_tx_desc *p)
@@ -743,38 +697,6 @@ static inline void set_ena_eth_io_tx_desc_l4_csum_partial(
& ENA_ETH_IO_TX_DESC_L4_CSUM_PARTIAL_MASK;
}
-static inline uint32_t get_ena_eth_io_tx_desc_tunnel_ctrl(
- const struct ena_eth_io_tx_desc *p)
-{
- return (p->meta_ctrl & ENA_ETH_IO_TX_DESC_TUNNEL_CTRL_MASK)
- >> ENA_ETH_IO_TX_DESC_TUNNEL_CTRL_SHIFT;
-}
-
-static inline void set_ena_eth_io_tx_desc_tunnel_ctrl(
- struct ena_eth_io_tx_desc *p,
- uint32_t val)
-{
- p->meta_ctrl |=
- (val << ENA_ETH_IO_TX_DESC_TUNNEL_CTRL_SHIFT)
- & ENA_ETH_IO_TX_DESC_TUNNEL_CTRL_MASK;
-}
-
-static inline uint32_t get_ena_eth_io_tx_desc_ts_req(
- const struct ena_eth_io_tx_desc *p)
-{
- return (p->meta_ctrl & ENA_ETH_IO_TX_DESC_TS_REQ_MASK)
- >> ENA_ETH_IO_TX_DESC_TS_REQ_SHIFT;
-}
-
-static inline void set_ena_eth_io_tx_desc_ts_req(
- struct ena_eth_io_tx_desc *p,
- uint32_t val)
-{
- p->meta_ctrl |=
- (val << ENA_ETH_IO_TX_DESC_TS_REQ_SHIFT)
- & ENA_ETH_IO_TX_DESC_TS_REQ_MASK;
-}
-
static inline uint32_t get_ena_eth_io_tx_desc_req_id_lo(
const struct ena_eth_io_tx_desc *p)
{
@@ -783,11 +705,9 @@ static inline uint32_t get_ena_eth_io_tx_desc_req_id_lo(
}
static inline void set_ena_eth_io_tx_desc_req_id_lo(
- struct ena_eth_io_tx_desc *p,
- uint32_t val)
+ struct ena_eth_io_tx_desc *p, uint32_t val)
{
- p->meta_ctrl |=
- (val << ENA_ETH_IO_TX_DESC_REQ_ID_LO_SHIFT)
+ p->meta_ctrl |= (val << ENA_ETH_IO_TX_DESC_REQ_ID_LO_SHIFT)
& ENA_ETH_IO_TX_DESC_REQ_ID_LO_MASK;
}
@@ -833,22 +753,6 @@ static inline void set_ena_eth_io_tx_meta_desc_req_id_lo(
p->len_ctrl |= val & ENA_ETH_IO_TX_META_DESC_REQ_ID_LO_MASK;
}
-static inline uint32_t get_ena_eth_io_tx_meta_desc_outr_l3_off_hi(
- const struct ena_eth_io_tx_meta_desc *p)
-{
- return (p->len_ctrl & ENA_ETH_IO_TX_META_DESC_OUTR_L3_OFF_HI_MASK)
- >> ENA_ETH_IO_TX_META_DESC_OUTR_L3_OFF_HI_SHIFT;
-}
-
-static inline void set_ena_eth_io_tx_meta_desc_outr_l3_off_hi(
- struct ena_eth_io_tx_meta_desc *p,
- uint32_t val)
-{
- p->len_ctrl |=
- (val << ENA_ETH_IO_TX_META_DESC_OUTR_L3_OFF_HI_SHIFT)
- & ENA_ETH_IO_TX_META_DESC_OUTR_L3_OFF_HI_MASK;
-}
-
static inline uint32_t get_ena_eth_io_tx_meta_desc_ext_valid(
const struct ena_eth_io_tx_meta_desc *p)
{
@@ -857,11 +761,9 @@ static inline uint32_t get_ena_eth_io_tx_meta_desc_ext_valid(
}
static inline void set_ena_eth_io_tx_meta_desc_ext_valid(
- struct ena_eth_io_tx_meta_desc *p,
- uint32_t val)
+ struct ena_eth_io_tx_meta_desc *p, uint32_t val)
{
- p->len_ctrl |=
- (val << ENA_ETH_IO_TX_META_DESC_EXT_VALID_SHIFT)
+ p->len_ctrl |= (val << ENA_ETH_IO_TX_META_DESC_EXT_VALID_SHIFT)
& ENA_ETH_IO_TX_META_DESC_EXT_VALID_MASK;
}
@@ -873,11 +775,9 @@ static inline uint32_t get_ena_eth_io_tx_meta_desc_word3_valid(
}
static inline void set_ena_eth_io_tx_meta_desc_word3_valid(
- struct ena_eth_io_tx_meta_desc *p,
- uint32_t val)
+ struct ena_eth_io_tx_meta_desc *p, uint32_t val)
{
- p->len_ctrl |=
- (val << ENA_ETH_IO_TX_META_DESC_WORD3_VALID_SHIFT)
+ p->len_ctrl |= (val << ENA_ETH_IO_TX_META_DESC_WORD3_VALID_SHIFT)
& ENA_ETH_IO_TX_META_DESC_WORD3_VALID_MASK;
}
@@ -889,11 +789,9 @@ static inline uint32_t get_ena_eth_io_tx_meta_desc_mss_hi_ptp(
}
static inline void set_ena_eth_io_tx_meta_desc_mss_hi_ptp(
- struct ena_eth_io_tx_meta_desc *p,
- uint32_t val)
+ struct ena_eth_io_tx_meta_desc *p, uint32_t val)
{
- p->len_ctrl |=
- (val << ENA_ETH_IO_TX_META_DESC_MSS_HI_PTP_SHIFT)
+ p->len_ctrl |= (val << ENA_ETH_IO_TX_META_DESC_MSS_HI_PTP_SHIFT)
& ENA_ETH_IO_TX_META_DESC_MSS_HI_PTP_MASK;
}
@@ -905,11 +803,9 @@ static inline uint32_t get_ena_eth_io_tx_meta_desc_eth_meta_type(
}
static inline void set_ena_eth_io_tx_meta_desc_eth_meta_type(
- struct ena_eth_io_tx_meta_desc *p,
- uint32_t val)
+ struct ena_eth_io_tx_meta_desc *p, uint32_t val)
{
- p->len_ctrl |=
- (val << ENA_ETH_IO_TX_META_DESC_ETH_META_TYPE_SHIFT)
+ p->len_ctrl |= (val << ENA_ETH_IO_TX_META_DESC_ETH_META_TYPE_SHIFT)
& ENA_ETH_IO_TX_META_DESC_ETH_META_TYPE_MASK;
}
@@ -921,11 +817,9 @@ static inline uint32_t get_ena_eth_io_tx_meta_desc_meta_store(
}
static inline void set_ena_eth_io_tx_meta_desc_meta_store(
- struct ena_eth_io_tx_meta_desc *p,
- uint32_t val)
+ struct ena_eth_io_tx_meta_desc *p, uint32_t val)
{
- p->len_ctrl |=
- (val << ENA_ETH_IO_TX_META_DESC_META_STORE_SHIFT)
+ p->len_ctrl |= (val << ENA_ETH_IO_TX_META_DESC_META_STORE_SHIFT)
& ENA_ETH_IO_TX_META_DESC_META_STORE_MASK;
}
@@ -937,11 +831,9 @@ static inline uint32_t get_ena_eth_io_tx_meta_desc_meta_desc(
}
static inline void set_ena_eth_io_tx_meta_desc_meta_desc(
- struct ena_eth_io_tx_meta_desc *p,
- uint32_t val)
+ struct ena_eth_io_tx_meta_desc *p, uint32_t val)
{
- p->len_ctrl |=
- (val << ENA_ETH_IO_TX_META_DESC_META_DESC_SHIFT)
+ p->len_ctrl |= (val << ENA_ETH_IO_TX_META_DESC_META_DESC_SHIFT)
& ENA_ETH_IO_TX_META_DESC_META_DESC_MASK;
}
@@ -953,11 +845,9 @@ static inline uint32_t get_ena_eth_io_tx_meta_desc_phase(
}
static inline void set_ena_eth_io_tx_meta_desc_phase(
- struct ena_eth_io_tx_meta_desc *p,
- uint32_t val)
+ struct ena_eth_io_tx_meta_desc *p, uint32_t val)
{
- p->len_ctrl |=
- (val << ENA_ETH_IO_TX_META_DESC_PHASE_SHIFT)
+ p->len_ctrl |= (val << ENA_ETH_IO_TX_META_DESC_PHASE_SHIFT)
& ENA_ETH_IO_TX_META_DESC_PHASE_MASK;
}
@@ -969,11 +859,9 @@ static inline uint32_t get_ena_eth_io_tx_meta_desc_first(
}
static inline void set_ena_eth_io_tx_meta_desc_first(
- struct ena_eth_io_tx_meta_desc *p,
- uint32_t val)
+ struct ena_eth_io_tx_meta_desc *p, uint32_t val)
{
- p->len_ctrl |=
- (val << ENA_ETH_IO_TX_META_DESC_FIRST_SHIFT)
+ p->len_ctrl |= (val << ENA_ETH_IO_TX_META_DESC_FIRST_SHIFT)
& ENA_ETH_IO_TX_META_DESC_FIRST_MASK;
}
@@ -985,11 +873,9 @@ static inline uint32_t get_ena_eth_io_tx_meta_desc_last(
}
static inline void set_ena_eth_io_tx_meta_desc_last(
- struct ena_eth_io_tx_meta_desc *p,
- uint32_t val)
+ struct ena_eth_io_tx_meta_desc *p, uint32_t val)
{
- p->len_ctrl |=
- (val << ENA_ETH_IO_TX_META_DESC_LAST_SHIFT)
+ p->len_ctrl |= (val << ENA_ETH_IO_TX_META_DESC_LAST_SHIFT)
& ENA_ETH_IO_TX_META_DESC_LAST_MASK;
}
@@ -1001,11 +887,9 @@ static inline uint32_t get_ena_eth_io_tx_meta_desc_comp_req(
}
static inline void set_ena_eth_io_tx_meta_desc_comp_req(
- struct ena_eth_io_tx_meta_desc *p,
- uint32_t val)
+ struct ena_eth_io_tx_meta_desc *p, uint32_t val)
{
- p->len_ctrl |=
- (val << ENA_ETH_IO_TX_META_DESC_COMP_REQ_SHIFT)
+ p->len_ctrl |= (val << ENA_ETH_IO_TX_META_DESC_COMP_REQ_SHIFT)
& ENA_ETH_IO_TX_META_DESC_COMP_REQ_MASK;
}
@@ -1083,51 +967,6 @@ static inline void set_ena_eth_io_tx_meta_desc_mss_lo(
& ENA_ETH_IO_TX_META_DESC_MSS_LO_MASK;
}
-static inline uint32_t get_ena_eth_io_tx_meta_desc_crypto_info(
- const struct ena_eth_io_tx_meta_desc *p)
-{
- return p->word3 & ENA_ETH_IO_TX_META_DESC_CRYPTO_INFO_MASK;
-}
-
-static inline void set_ena_eth_io_tx_meta_desc_crypto_info(
- struct ena_eth_io_tx_meta_desc *p,
- uint32_t val)
-{
- p->word3 |= val & ENA_ETH_IO_TX_META_DESC_CRYPTO_INFO_MASK;
-}
-
-static inline uint32_t get_ena_eth_io_tx_meta_desc_outr_l3_hdr_len_words(
- const struct ena_eth_io_tx_meta_desc *p)
-{
- return (p->word3 & ENA_ETH_IO_TX_META_DESC_OUTR_L3_HDR_LEN_WORDS_MASK)
- >> ENA_ETH_IO_TX_META_DESC_OUTR_L3_HDR_LEN_WORDS_SHIFT;
-}
-
-static inline void set_ena_eth_io_tx_meta_desc_outr_l3_hdr_len_words(
- struct ena_eth_io_tx_meta_desc *p,
- uint32_t val)
-{
- p->word3 |=
- (val << ENA_ETH_IO_TX_META_DESC_OUTR_L3_HDR_LEN_WORDS_SHIFT)
- & ENA_ETH_IO_TX_META_DESC_OUTR_L3_HDR_LEN_WORDS_MASK;
-}
-
-static inline uint32_t get_ena_eth_io_tx_meta_desc_outr_l3_off_lo(
- const struct ena_eth_io_tx_meta_desc *p)
-{
- return (p->word3 & ENA_ETH_IO_TX_META_DESC_OUTR_L3_OFF_LO_MASK)
- >> ENA_ETH_IO_TX_META_DESC_OUTR_L3_OFF_LO_SHIFT;
-}
-
-static inline void set_ena_eth_io_tx_meta_desc_outr_l3_off_lo(
- struct ena_eth_io_tx_meta_desc *p,
- uint32_t val)
-{
- p->word3 |=
- (val << ENA_ETH_IO_TX_META_DESC_OUTR_L3_OFF_LO_SHIFT)
- & ENA_ETH_IO_TX_META_DESC_OUTR_L3_OFF_LO_MASK;
-}
-
static inline uint8_t get_ena_eth_io_tx_cdesc_phase(
const struct ena_eth_io_tx_cdesc *p)
{
@@ -1231,22 +1070,6 @@ static inline void set_ena_eth_io_rx_cdesc_base_src_vlan_cnt(
& ENA_ETH_IO_RX_CDESC_BASE_SRC_VLAN_CNT_MASK;
}
-static inline uint32_t get_ena_eth_io_rx_cdesc_base_tunnel(
- const struct ena_eth_io_rx_cdesc_base *p)
-{
- return (p->status & ENA_ETH_IO_RX_CDESC_BASE_TUNNEL_MASK)
- >> ENA_ETH_IO_RX_CDESC_BASE_TUNNEL_SHIFT;
-}
-
-static inline void set_ena_eth_io_rx_cdesc_base_tunnel(
- struct ena_eth_io_rx_cdesc_base *p,
- uint32_t val)
-{
- p->status |=
- (val << ENA_ETH_IO_RX_CDESC_BASE_TUNNEL_SHIFT)
- & ENA_ETH_IO_RX_CDESC_BASE_TUNNEL_MASK;
-}
-
static inline uint32_t get_ena_eth_io_rx_cdesc_base_l4_proto_idx(
const struct ena_eth_io_rx_cdesc_base *p)
{
@@ -1255,11 +1078,9 @@ static inline uint32_t get_ena_eth_io_rx_cdesc_base_l4_proto_idx(
}
static inline void set_ena_eth_io_rx_cdesc_base_l4_proto_idx(
- struct ena_eth_io_rx_cdesc_base *p,
- uint32_t val)
+ struct ena_eth_io_rx_cdesc_base *p, uint32_t val)
{
- p->status |=
- (val << ENA_ETH_IO_RX_CDESC_BASE_L4_PROTO_IDX_SHIFT)
+ p->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_L4_PROTO_IDX_SHIFT)
& ENA_ETH_IO_RX_CDESC_BASE_L4_PROTO_IDX_MASK;
}
@@ -1271,11 +1092,9 @@ static inline uint32_t get_ena_eth_io_rx_cdesc_base_l3_csum_err(
}
static inline void set_ena_eth_io_rx_cdesc_base_l3_csum_err(
- struct ena_eth_io_rx_cdesc_base *p,
- uint32_t val)
+ struct ena_eth_io_rx_cdesc_base *p, uint32_t val)
{
- p->status |=
- (val << ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM_ERR_SHIFT)
+ p->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM_ERR_SHIFT)
& ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM_ERR_MASK;
}
@@ -1287,11 +1106,9 @@ static inline uint32_t get_ena_eth_io_rx_cdesc_base_l4_csum_err(
}
static inline void set_ena_eth_io_rx_cdesc_base_l4_csum_err(
- struct ena_eth_io_rx_cdesc_base *p,
- uint32_t val)
+ struct ena_eth_io_rx_cdesc_base *p, uint32_t val)
{
- p->status |=
- (val << ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_ERR_SHIFT)
+ p->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_ERR_SHIFT)
& ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_ERR_MASK;
}
@@ -1303,46 +1120,12 @@ static inline uint32_t get_ena_eth_io_rx_cdesc_base_ipv4_frag(
}
static inline void set_ena_eth_io_rx_cdesc_base_ipv4_frag(
- struct ena_eth_io_rx_cdesc_base *p,
- uint32_t val)
+ struct ena_eth_io_rx_cdesc_base *p, uint32_t val)
{
- p->status |=
- (val << ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_SHIFT)
+ p->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_SHIFT)
& ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_MASK;
}
-static inline uint32_t get_ena_eth_io_rx_cdesc_base_secured_pkt(
- const struct ena_eth_io_rx_cdesc_base *p)
-{
- return (p->status & ENA_ETH_IO_RX_CDESC_BASE_SECURED_PKT_MASK)
- >> ENA_ETH_IO_RX_CDESC_BASE_SECURED_PKT_SHIFT;
-}
-
-static inline void set_ena_eth_io_rx_cdesc_base_secured_pkt(
- struct ena_eth_io_rx_cdesc_base *p,
- uint32_t val)
-{
- p->status |=
- (val << ENA_ETH_IO_RX_CDESC_BASE_SECURED_PKT_SHIFT)
- & ENA_ETH_IO_RX_CDESC_BASE_SECURED_PKT_MASK;
-}
-
-static inline uint32_t get_ena_eth_io_rx_cdesc_base_crypto_status(
- const struct ena_eth_io_rx_cdesc_base *p)
-{
- return (p->status & ENA_ETH_IO_RX_CDESC_BASE_CRYPTO_STATUS_MASK)
- >> ENA_ETH_IO_RX_CDESC_BASE_CRYPTO_STATUS_SHIFT;
-}
-
-static inline void set_ena_eth_io_rx_cdesc_base_crypto_status(
- struct ena_eth_io_rx_cdesc_base *p,
- uint32_t val)
-{
- p->status |=
- (val << ENA_ETH_IO_RX_CDESC_BASE_CRYPTO_STATUS_SHIFT)
- & ENA_ETH_IO_RX_CDESC_BASE_CRYPTO_STATUS_MASK;
-}
-
static inline uint32_t get_ena_eth_io_rx_cdesc_base_phase(
const struct ena_eth_io_rx_cdesc_base *p)
{
@@ -1351,11 +1134,9 @@ static inline uint32_t get_ena_eth_io_rx_cdesc_base_phase(
}
static inline void set_ena_eth_io_rx_cdesc_base_phase(
- struct ena_eth_io_rx_cdesc_base *p,
- uint32_t val)
+ struct ena_eth_io_rx_cdesc_base *p, uint32_t val)
{
- p->status |=
- (val << ENA_ETH_IO_RX_CDESC_BASE_PHASE_SHIFT)
+ p->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_PHASE_SHIFT)
& ENA_ETH_IO_RX_CDESC_BASE_PHASE_MASK;
}
@@ -1367,11 +1148,9 @@ static inline uint32_t get_ena_eth_io_rx_cdesc_base_l3_csum2(
}
static inline void set_ena_eth_io_rx_cdesc_base_l3_csum2(
- struct ena_eth_io_rx_cdesc_base *p,
- uint32_t val)
+ struct ena_eth_io_rx_cdesc_base *p, uint32_t val)
{
- p->status |=
- (val << ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM2_SHIFT)
+ p->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM2_SHIFT)
& ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM2_MASK;
}
@@ -1383,11 +1162,9 @@ static inline uint32_t get_ena_eth_io_rx_cdesc_base_first(
}
static inline void set_ena_eth_io_rx_cdesc_base_first(
- struct ena_eth_io_rx_cdesc_base *p,
- uint32_t val)
+ struct ena_eth_io_rx_cdesc_base *p, uint32_t val)
{
- p->status |=
- (val << ENA_ETH_IO_RX_CDESC_BASE_FIRST_SHIFT)
+ p->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_FIRST_SHIFT)
& ENA_ETH_IO_RX_CDESC_BASE_FIRST_MASK;
}
@@ -1399,30 +1176,12 @@ static inline uint32_t get_ena_eth_io_rx_cdesc_base_last(
}
static inline void set_ena_eth_io_rx_cdesc_base_last(
- struct ena_eth_io_rx_cdesc_base *p,
- uint32_t val)
+ struct ena_eth_io_rx_cdesc_base *p, uint32_t val)
{
- p->status |=
- (val << ENA_ETH_IO_RX_CDESC_BASE_LAST_SHIFT)
+ p->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_LAST_SHIFT)
& ENA_ETH_IO_RX_CDESC_BASE_LAST_MASK;
}
-static inline uint32_t get_ena_eth_io_rx_cdesc_base_inr_l4_csum(
- const struct ena_eth_io_rx_cdesc_base *p)
-{
- return (p->status & ENA_ETH_IO_RX_CDESC_BASE_INR_L4_CSUM_MASK)
- >> ENA_ETH_IO_RX_CDESC_BASE_INR_L4_CSUM_SHIFT;
-}
-
-static inline void set_ena_eth_io_rx_cdesc_base_inr_l4_csum(
- struct ena_eth_io_rx_cdesc_base *p,
- uint32_t val)
-{
- p->status |=
- (val << ENA_ETH_IO_RX_CDESC_BASE_INR_L4_CSUM_SHIFT)
- & ENA_ETH_IO_RX_CDESC_BASE_INR_L4_CSUM_MASK;
-}
-
static inline uint32_t get_ena_eth_io_rx_cdesc_base_buffer(
const struct ena_eth_io_rx_cdesc_base *p)
{
@@ -1431,11 +1190,9 @@ static inline uint32_t get_ena_eth_io_rx_cdesc_base_buffer(
}
static inline void set_ena_eth_io_rx_cdesc_base_buffer(
- struct ena_eth_io_rx_cdesc_base *p,
- uint32_t val)
+ struct ena_eth_io_rx_cdesc_base *p, uint32_t val)
{
- p->status |=
- (val << ENA_ETH_IO_RX_CDESC_BASE_BUFFER_SHIFT)
+ p->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_BUFFER_SHIFT)
& ENA_ETH_IO_RX_CDESC_BASE_BUFFER_MASK;
}
@@ -1446,8 +1203,7 @@ static inline uint32_t get_ena_eth_io_intr_reg_rx_intr_delay(
}
static inline void set_ena_eth_io_intr_reg_rx_intr_delay(
- struct ena_eth_io_intr_reg *p,
- uint32_t val)
+ struct ena_eth_io_intr_reg *p, uint32_t val)
{
p->intr_control |= val & ENA_ETH_IO_INTR_REG_RX_INTR_DELAY_MASK;
}
@@ -1460,11 +1216,9 @@ static inline uint32_t get_ena_eth_io_intr_reg_tx_intr_delay(
}
static inline void set_ena_eth_io_intr_reg_tx_intr_delay(
- struct ena_eth_io_intr_reg *p,
- uint32_t val)
+ struct ena_eth_io_intr_reg *p, uint32_t val)
{
- p->intr_control |=
- (val << ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_SHIFT)
+ p->intr_control |= (val << ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_SHIFT)
& ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_MASK;
}
@@ -1476,13 +1230,37 @@ static inline uint32_t get_ena_eth_io_intr_reg_intr_unmask(
}
static inline void set_ena_eth_io_intr_reg_intr_unmask(
- struct ena_eth_io_intr_reg *p,
- uint32_t val)
+ struct ena_eth_io_intr_reg *p, uint32_t val)
{
- p->intr_control |=
- (val << ENA_ETH_IO_INTR_REG_INTR_UNMASK_SHIFT)
+ p->intr_control |= (val << ENA_ETH_IO_INTR_REG_INTR_UNMASK_SHIFT)
& ENA_ETH_IO_INTR_REG_INTR_UNMASK_MASK;
}
+static inline uint32_t get_ena_eth_io_numa_node_cfg_reg_numa(
+ const struct ena_eth_io_numa_node_cfg_reg *p)
+{
+ return p->numa_cfg & ENA_ETH_IO_NUMA_NODE_CFG_REG_NUMA_MASK;
+}
+
+static inline void set_ena_eth_io_numa_node_cfg_reg_numa(
+ struct ena_eth_io_numa_node_cfg_reg *p, uint32_t val)
+{
+ p->numa_cfg |= val & ENA_ETH_IO_NUMA_NODE_CFG_REG_NUMA_MASK;
+}
+
+static inline uint32_t get_ena_eth_io_numa_node_cfg_reg_enabled(
+ const struct ena_eth_io_numa_node_cfg_reg *p)
+{
+ return (p->numa_cfg & ENA_ETH_IO_NUMA_NODE_CFG_REG_ENABLED_MASK)
+ >> ENA_ETH_IO_NUMA_NODE_CFG_REG_ENABLED_SHIFT;
+}
+
+static inline void set_ena_eth_io_numa_node_cfg_reg_enabled(
+ struct ena_eth_io_numa_node_cfg_reg *p, uint32_t val)
+{
+ p->numa_cfg |= (val << ENA_ETH_IO_NUMA_NODE_CFG_REG_ENABLED_SHIFT)
+ & ENA_ETH_IO_NUMA_NODE_CFG_REG_ENABLED_MASK;
+}
+
#endif /* !defined(ENA_DEFS_LINUX_MAINLINE) */
#endif /*_ENA_ETH_IO_H_ */
diff --git a/drivers/net/ena/base/ena_defs/ena_gen_info.h b/drivers/net/ena/base/ena_defs/ena_gen_info.h
index 4abdffed..3d252096 100644
--- a/drivers/net/ena/base/ena_defs/ena_gen_info.h
+++ b/drivers/net/ena/base/ena_defs/ena_gen_info.h
@@ -31,5 +31,5 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-#define ENA_GEN_DATE "Mon Feb 15 14:33:08 IST 2016"
-#define ENA_GEN_COMMIT "c71ec25"
+#define ENA_GEN_DATE "Sun Jun 5 10:24:39 IDT 2016"
+#define ENA_GEN_COMMIT "17146ed"
diff --git a/drivers/net/ena/base/ena_eth_com.c b/drivers/net/ena/base/ena_eth_com.c
index 459e0bbb..290a5666 100644
--- a/drivers/net/ena/base/ena_eth_com.c
+++ b/drivers/net/ena/base/ena_eth_com.c
@@ -62,7 +62,7 @@ static inline void ena_com_cq_inc_head(struct ena_com_io_cq *io_cq)
/* Switch phase bit in case of wrap around */
if (unlikely((io_cq->head & (io_cq->q_depth - 1)) == 0))
- io_cq->phase = 1 - io_cq->phase;
+ io_cq->phase ^= 1;
}
static inline void *get_sq_desc(struct ena_com_io_sq *io_sq)
@@ -97,7 +97,7 @@ static inline void ena_com_sq_update_tail(struct ena_com_io_sq *io_sq)
/* Switch phase bit in case of wrap around */
if (unlikely((io_sq->tail & (io_sq->q_depth - 1)) == 0))
- io_sq->phase = 1 - io_sq->phase;
+ io_sq->phase ^= 1;
}
static inline int ena_com_write_header(struct ena_com_io_sq *io_sq,
@@ -110,7 +110,10 @@ static inline int ena_com_write_header(struct ena_com_io_sq *io_sq,
if (io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST)
return 0;
- ENA_ASSERT(io_sq->header_addr, "header address is NULL\n");
+ if (unlikely(!io_sq->header_addr)) {
+ ena_trc_err("Push buffer header ptr is NULL\n");
+ return ENA_COM_INVAL;
+ }
memcpy_toio(dev_head_addr, head_src, header_len);
@@ -127,8 +130,7 @@ static inline struct ena_eth_io_rx_cdesc_base *
}
static inline int ena_com_cdesc_rx_pkt_get(struct ena_com_io_cq *io_cq,
- u16 *first_cdesc_idx,
- u16 *nb_hw_desc)
+ u16 *first_cdesc_idx)
{
struct ena_eth_io_rx_cdesc_base *cdesc;
u16 count = 0, head_masked;
@@ -161,8 +163,7 @@ static inline int ena_com_cdesc_rx_pkt_get(struct ena_com_io_cq *io_cq,
count = 0;
}
- *nb_hw_desc = count;
- return 0;
+ return count;
}
static inline bool ena_com_meta_desc_changed(struct ena_com_io_sq *io_sq,
@@ -408,21 +409,20 @@ int ena_com_rx_pkt(struct ena_com_io_cq *io_cq,
u16 cdesc_idx = 0;
u16 nb_hw_desc;
u16 i;
- int rc;
ENA_ASSERT(io_cq->direction == ENA_COM_IO_QUEUE_DIRECTION_RX,
"wrong Q type");
- rc = ena_com_cdesc_rx_pkt_get(io_cq, &cdesc_idx, &nb_hw_desc);
- if (rc || (nb_hw_desc == 0)) {
+ nb_hw_desc = ena_com_cdesc_rx_pkt_get(io_cq, &cdesc_idx);
+ if (nb_hw_desc == 0) {
ena_rx_ctx->descs = nb_hw_desc;
- return rc;
+ return 0;
}
ena_trc_dbg("fetch rx packet: queue %d completed desc: %d\n",
io_cq->qid, nb_hw_desc);
- if (unlikely(nb_hw_desc >= ena_rx_ctx->max_bufs)) {
+ if (unlikely(nb_hw_desc > ena_rx_ctx->max_bufs)) {
ena_trc_err("Too many RX cdescs (%d) > MAX(%d)\n",
nb_hw_desc, ena_rx_ctx->max_bufs);
return ENA_COM_NO_SPACE;
@@ -459,7 +459,7 @@ int ena_com_add_single_rx_desc(struct ena_com_io_sq *io_sq,
"wrong Q type");
if (unlikely(ena_com_sq_empty_space(io_sq) == 0))
- return -1;
+ return ENA_COM_NO_SPACE;
desc = get_sq_desc(io_sq);
memset(desc, 0x0, sizeof(struct ena_eth_io_rx_desc));
@@ -496,9 +496,13 @@ int ena_com_tx_comp_req_id_get(struct ena_com_io_cq *io_cq, u16 *req_id)
((unsigned char *)io_cq->cdesc_addr.virt_addr
+ (masked_head * io_cq->cdesc_entry_size_in_bytes));
+ /* When the current completion descriptor phase isn't the same as the
+ * expected, it mean that the device still didn't update
+ * this completion.
+ */
cdesc_phase = cdesc->flags & ENA_ETH_IO_TX_CDESC_PHASE_MASK;
if (cdesc_phase != expected_phase)
- return -1;
+ return ENA_COM_TRY_AGAIN;
ena_com_cq_inc_head(io_cq);
diff --git a/drivers/net/ena/base/ena_eth_com.h b/drivers/net/ena/base/ena_eth_com.h
index 325d69c0..71a880c0 100644
--- a/drivers/net/ena/base/ena_eth_com.h
+++ b/drivers/net/ena/base/ena_eth_com.h
@@ -142,6 +142,20 @@ static inline int ena_com_update_dev_comp_head(struct ena_com_io_cq *io_cq)
return 0;
}
+static inline void ena_com_update_numa_node(struct ena_com_io_cq *io_cq,
+ u8 numa_node)
+{
+ struct ena_eth_io_numa_node_cfg_reg numa_cfg;
+
+ if (!io_cq->numa_node_cfg_reg)
+ return;
+
+ numa_cfg.numa_cfg = (numa_node & ENA_ETH_IO_NUMA_NODE_CFG_REG_NUMA_MASK)
+ | ENA_ETH_IO_NUMA_NODE_CFG_REG_ENABLED_MASK;
+
+ ENA_REG_WRITE32(numa_cfg.numa_cfg, io_cq->numa_node_cfg_reg);
+}
+
static inline void ena_com_comp_ack(struct ena_com_io_sq *io_sq, u16 elem)
{
io_sq->next_to_comp += elem;
diff --git a/drivers/net/ena/base/ena_plat_dpdk.h b/drivers/net/ena/base/ena_plat_dpdk.h
index 5f693301..87c3bf13 100644
--- a/drivers/net/ena/base/ena_plat_dpdk.h
+++ b/drivers/net/ena/base/ena_plat_dpdk.h
@@ -62,10 +62,10 @@ typedef uint64_t dma_addr_t;
#endif
#define ena_atomic32_t rte_atomic32_t
-#define ena_mem_handle_t void *
+#define ena_mem_handle_t const struct rte_memzone *
-#define SZ_256 (256)
-#define SZ_4K (4096)
+#define SZ_256 (256U)
+#define SZ_4K (4096U)
#define ENA_COM_OK 0
#define ENA_COM_NO_MEM -ENOMEM
@@ -75,6 +75,7 @@ typedef uint64_t dma_addr_t;
#define ENA_COM_PERMISSION -EPERM
#define ENA_COM_TIMER_EXPIRED -ETIME
#define ENA_COM_FAULT -EFAULT
+#define ENA_COM_TRY_AGAIN -EAGAIN
#define ____cacheline_aligned __rte_cache_aligned
@@ -83,6 +84,7 @@ typedef uint64_t dma_addr_t;
#define ENA_MSLEEP(x) rte_delay_ms(x)
#define ENA_UDELAY(x) rte_delay_us(x)
+#define ENA_TOUCH(x) ((void)(x))
#define memcpy_toio memcpy
#define wmb rte_wmb
#define rmb rte_wmb
@@ -182,17 +184,45 @@ typedef uint64_t dma_addr_t;
do { \
const struct rte_memzone *mz; \
char z_name[RTE_MEMZONE_NAMESIZE]; \
- (void)dmadev; (void)handle; \
+ ENA_TOUCH(dmadev); ENA_TOUCH(handle); \
snprintf(z_name, sizeof(z_name), \
"ena_alloc_%d", ena_alloc_cnt++); \
mz = rte_memzone_reserve(z_name, size, SOCKET_ID_ANY, 0); \
+ memset(mz->addr, 0, size); \
virt = mz->addr; \
phys = mz->phys_addr; \
+ handle = mz; \
} while (0)
#define ENA_MEM_FREE_COHERENT(dmadev, size, virt, phys, handle) \
- ({(void)size; rte_free(virt); })
+ ({ ENA_TOUCH(size); ENA_TOUCH(phys); \
+ ENA_TOUCH(dmadev); \
+ rte_memzone_free(handle); })
+
+#define ENA_MEM_ALLOC_COHERENT_NODE(dmadev, size, virt, phys, node, dev_node) \
+ do { \
+ const struct rte_memzone *mz; \
+ char z_name[RTE_MEMZONE_NAMESIZE]; \
+ ENA_TOUCH(dmadev); ENA_TOUCH(dev_node); \
+ snprintf(z_name, sizeof(z_name), \
+ "ena_alloc_%d", ena_alloc_cnt++); \
+ mz = rte_memzone_reserve(z_name, size, node, 0); \
+ virt = mz->addr; \
+ phys = mz->phys_addr; \
+ } while (0)
+
+#define ENA_MEM_ALLOC_NODE(dmadev, size, virt, node, dev_node) \
+ do { \
+ const struct rte_memzone *mz; \
+ char z_name[RTE_MEMZONE_NAMESIZE]; \
+ ENA_TOUCH(dmadev); ENA_TOUCH(dev_node); \
+ snprintf(z_name, sizeof(z_name), \
+ "ena_alloc_%d", ena_alloc_cnt++); \
+ mz = rte_memzone_reserve(z_name, size, node, 0); \
+ virt = mz->addr; \
+ } while (0)
+
#define ENA_MEM_ALLOC(dmadev, size) rte_zmalloc(NULL, size, 1)
-#define ENA_MEM_FREE(dmadev, ptr) ({(void)dmadev; rte_free(ptr); })
+#define ENA_MEM_FREE(dmadev, ptr) ({ENA_TOUCH(dmadev); rte_free(ptr); })
static inline void writel(u32 value, volatile void *addr)
{
diff --git a/drivers/net/ena/ena_ethdev.c b/drivers/net/ena/ena_ethdev.c
index e157587b..ac0803d6 100644
--- a/drivers/net/ena/ena_ethdev.c
+++ b/drivers/net/ena/ena_ethdev.c
@@ -37,6 +37,8 @@
#include <rte_atomic.h>
#include <rte_dev.h>
#include <rte_errno.h>
+#include <rte_version.h>
+#include <rte_eal_memconfig.h>
#include "ena_ethdev.h"
#include "ena_logs.h"
@@ -49,6 +51,10 @@
#include <ena_admin_defs.h>
#include <ena_eth_io_defs.h>
+#define DRV_MODULE_VER_MAJOR 1
+#define DRV_MODULE_VER_MINOR 0
+#define DRV_MODULE_VER_SUBMINOR 0
+
#define ENA_IO_TXQ_IDX(q) (2 * (q))
#define ENA_IO_RXQ_IDX(q) (2 * (q) + 1)
/*reverse version of ENA_IO_RXQ_IDX*/
@@ -72,6 +78,89 @@
#define ENA_RX_RSS_TABLE_LOG_SIZE 7
#define ENA_RX_RSS_TABLE_SIZE (1 << ENA_RX_RSS_TABLE_LOG_SIZE)
#define ENA_HASH_KEY_SIZE 40
+#define ENA_ETH_SS_STATS 0xFF
+#define ETH_GSTRING_LEN 32
+
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
+enum ethtool_stringset {
+ ETH_SS_TEST = 0,
+ ETH_SS_STATS,
+};
+
+struct ena_stats {
+ char name[ETH_GSTRING_LEN];
+ int stat_offset;
+};
+
+#define ENA_STAT_ENA_COM_ENTRY(stat) { \
+ .name = #stat, \
+ .stat_offset = offsetof(struct ena_com_stats_admin, stat) \
+}
+
+#define ENA_STAT_ENTRY(stat, stat_type) { \
+ .name = #stat, \
+ .stat_offset = offsetof(struct ena_stats_##stat_type, stat) \
+}
+
+#define ENA_STAT_RX_ENTRY(stat) \
+ ENA_STAT_ENTRY(stat, rx)
+
+#define ENA_STAT_TX_ENTRY(stat) \
+ ENA_STAT_ENTRY(stat, tx)
+
+#define ENA_STAT_GLOBAL_ENTRY(stat) \
+ ENA_STAT_ENTRY(stat, dev)
+
+static const struct ena_stats ena_stats_global_strings[] = {
+ ENA_STAT_GLOBAL_ENTRY(tx_timeout),
+ ENA_STAT_GLOBAL_ENTRY(io_suspend),
+ ENA_STAT_GLOBAL_ENTRY(io_resume),
+ ENA_STAT_GLOBAL_ENTRY(wd_expired),
+ ENA_STAT_GLOBAL_ENTRY(interface_up),
+ ENA_STAT_GLOBAL_ENTRY(interface_down),
+ ENA_STAT_GLOBAL_ENTRY(admin_q_pause),
+};
+
+static const struct ena_stats ena_stats_tx_strings[] = {
+ ENA_STAT_TX_ENTRY(cnt),
+ ENA_STAT_TX_ENTRY(bytes),
+ ENA_STAT_TX_ENTRY(queue_stop),
+ ENA_STAT_TX_ENTRY(queue_wakeup),
+ ENA_STAT_TX_ENTRY(dma_mapping_err),
+ ENA_STAT_TX_ENTRY(linearize),
+ ENA_STAT_TX_ENTRY(linearize_failed),
+ ENA_STAT_TX_ENTRY(tx_poll),
+ ENA_STAT_TX_ENTRY(doorbells),
+ ENA_STAT_TX_ENTRY(prepare_ctx_err),
+ ENA_STAT_TX_ENTRY(missing_tx_comp),
+ ENA_STAT_TX_ENTRY(bad_req_id),
+};
+
+static const struct ena_stats ena_stats_rx_strings[] = {
+ ENA_STAT_RX_ENTRY(cnt),
+ ENA_STAT_RX_ENTRY(bytes),
+ ENA_STAT_RX_ENTRY(refil_partial),
+ ENA_STAT_RX_ENTRY(bad_csum),
+ ENA_STAT_RX_ENTRY(page_alloc_fail),
+ ENA_STAT_RX_ENTRY(skb_alloc_fail),
+ ENA_STAT_RX_ENTRY(dma_mapping_err),
+ ENA_STAT_RX_ENTRY(bad_desc_num),
+ ENA_STAT_RX_ENTRY(small_copy_len_pkt),
+};
+
+static const struct ena_stats ena_stats_ena_com_strings[] = {
+ ENA_STAT_ENA_COM_ENTRY(aborted_cmd),
+ ENA_STAT_ENA_COM_ENTRY(submitted_cmd),
+ ENA_STAT_ENA_COM_ENTRY(completed_cmd),
+ ENA_STAT_ENA_COM_ENTRY(out_of_space),
+ ENA_STAT_ENA_COM_ENTRY(no_completion),
+};
+
+#define ENA_STATS_ARRAY_GLOBAL ARRAY_SIZE(ena_stats_global_strings)
+#define ENA_STATS_ARRAY_TX ARRAY_SIZE(ena_stats_tx_strings)
+#define ENA_STATS_ARRAY_RX ARRAY_SIZE(ena_stats_rx_strings)
+#define ENA_STATS_ARRAY_ENA_COM ARRAY_SIZE(ena_stats_ena_com_strings)
/** Vendor ID used by Amazon devices */
#define PCI_VENDOR_ID_AMAZON 0x1D0F
@@ -80,11 +169,9 @@
#define PCI_DEVICE_ID_ENA_LLQ_VF 0xEC21
static struct rte_pci_id pci_id_ena_map[] = {
-#define RTE_PCI_DEV_ID_DECL_ENA(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
-
- RTE_PCI_DEV_ID_DECL_ENA(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_VF)
- RTE_PCI_DEV_ID_DECL_ENA(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_LLQ_VF)
- {.device_id = 0},
+ { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_VF) },
+ { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_LLQ_VF) },
+ { .device_id = 0 },
};
static int ena_device_init(struct ena_com_dev *ena_dev,
@@ -127,6 +214,7 @@ static int ena_rss_reta_update(struct rte_eth_dev *dev,
static int ena_rss_reta_query(struct rte_eth_dev *dev,
struct rte_eth_rss_reta_entry64 *reta_conf,
uint16_t reta_size);
+static int ena_get_sset_count(struct rte_eth_dev *dev, int sset);
static struct eth_dev_ops ena_dev_ops = {
.dev_configure = ena_dev_configure,
@@ -144,6 +232,18 @@ static struct eth_dev_ops ena_dev_ops = {
.reta_query = ena_rss_reta_query,
};
+#define NUMA_NO_NODE SOCKET_ID_ANY
+
+static inline int ena_cpu_to_node(int cpu)
+{
+ struct rte_config *config = rte_eal_get_configuration();
+
+ if (likely(cpu < RTE_MAX_MEMZONE))
+ return config->mem_config->memzone[cpu].socket_id;
+
+ return NUMA_NO_NODE;
+}
+
static inline void ena_rx_mbuf_prepare(struct rte_mbuf *mbuf,
struct ena_com_rx_ctx *ena_rx_ctx)
{
@@ -226,6 +326,103 @@ static inline void ena_tx_mbuf_prepare(struct rte_mbuf *mbuf,
}
}
+static void ena_config_host_info(struct ena_com_dev *ena_dev)
+{
+ struct ena_admin_host_info *host_info;
+ int rc;
+
+ /* Allocate only the host info */
+ rc = ena_com_allocate_host_info(ena_dev);
+ if (rc) {
+ RTE_LOG(ERR, PMD, "Cannot allocate host info\n");
+ return;
+ }
+
+ host_info = ena_dev->host_attr.host_info;
+
+ host_info->os_type = ENA_ADMIN_OS_DPDK;
+ host_info->kernel_ver = RTE_VERSION;
+ strncpy((char *)host_info->kernel_ver_str, rte_version(),
+ strlen(rte_version()));
+ host_info->os_dist = RTE_VERSION;
+ strncpy((char *)host_info->os_dist_str, rte_version(),
+ strlen(rte_version()));
+ host_info->driver_version =
+ (DRV_MODULE_VER_MAJOR) |
+ (DRV_MODULE_VER_MINOR << ENA_ADMIN_HOST_INFO_MINOR_SHIFT) |
+ (DRV_MODULE_VER_SUBMINOR <<
+ ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT);
+
+ rc = ena_com_set_host_attributes(ena_dev);
+ if (rc) {
+ if (rc == -EPERM)
+ RTE_LOG(ERR, PMD, "Cannot set host attributes\n");
+ else
+ RTE_LOG(ERR, PMD, "Cannot set host attributes\n");
+
+ goto err;
+ }
+
+ return;
+
+err:
+ ena_com_delete_host_info(ena_dev);
+}
+
+static int
+ena_get_sset_count(struct rte_eth_dev *dev, int sset)
+{
+ if (sset != ETH_SS_STATS)
+ return -EOPNOTSUPP;
+
+ /* Workaround for clang:
+ * touch internal structures to prevent
+ * compiler error
+ */
+ ENA_TOUCH(ena_stats_global_strings);
+ ENA_TOUCH(ena_stats_tx_strings);
+ ENA_TOUCH(ena_stats_rx_strings);
+ ENA_TOUCH(ena_stats_ena_com_strings);
+
+ return dev->data->nb_tx_queues *
+ (ENA_STATS_ARRAY_TX + ENA_STATS_ARRAY_RX) +
+ ENA_STATS_ARRAY_GLOBAL + ENA_STATS_ARRAY_ENA_COM;
+}
+
+static void ena_config_debug_area(struct ena_adapter *adapter)
+{
+ u32 debug_area_size;
+ int rc, ss_count;
+
+ ss_count = ena_get_sset_count(adapter->rte_dev, ETH_SS_STATS);
+ if (ss_count <= 0) {
+ RTE_LOG(ERR, PMD, "SS count is negative\n");
+ return;
+ }
+
+ /* allocate 32 bytes for each string and 64bit for the value */
+ debug_area_size = ss_count * ETH_GSTRING_LEN + sizeof(u64) * ss_count;
+
+ rc = ena_com_allocate_debug_area(&adapter->ena_dev, debug_area_size);
+ if (rc) {
+ RTE_LOG(ERR, PMD, "Cannot allocate debug area\n");
+ return;
+ }
+
+ rc = ena_com_set_host_attributes(&adapter->ena_dev);
+ if (rc) {
+ if (rc == -EPERM)
+ RTE_LOG(WARNING, PMD, "Cannot set host attributes\n");
+ else
+ RTE_LOG(ERR, PMD, "Cannot set host attributes\n");
+ goto err;
+ }
+
+ return;
+err:
+ ena_com_delete_debug_area(&adapter->ena_dev);
+}
+
static void ena_close(struct rte_eth_dev *dev)
{
struct ena_adapter *adapter =
@@ -742,6 +939,10 @@ static int ena_tx_queue_setup(struct rte_eth_dev *dev,
__rte_unused unsigned int socket_id,
__rte_unused const struct rte_eth_txconf *tx_conf)
{
+ struct ena_com_create_io_ctx ctx =
+ /* policy set to _HOST just to satisfy icc compiler */
+ { ENA_ADMIN_PLACEMENT_POLICY_HOST,
+ ENA_COM_IO_QUEUE_DIRECTION_TX, 0, 0, 0, 0 };
struct ena_ring *txq = NULL;
struct ena_adapter *adapter =
(struct ena_adapter *)(dev->data->dev_private);
@@ -767,11 +968,15 @@ static int ena_tx_queue_setup(struct rte_eth_dev *dev,
}
ena_qid = ENA_IO_TXQ_IDX(queue_idx);
- rc = ena_com_create_io_queue(ena_dev, ena_qid,
- ENA_COM_IO_QUEUE_DIRECTION_TX,
- ena_dev->tx_mem_queue_type,
- -1 /* admin interrupts is not used */,
- nb_desc);
+
+ ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_TX;
+ ctx.qid = ena_qid;
+ ctx.msix_vector = -1; /* admin interrupts not used */
+ ctx.mem_queue_type = ena_dev->tx_mem_queue_type;
+ ctx.queue_size = adapter->tx_ring_size;
+ ctx.numa_node = ena_cpu_to_node(queue_idx);
+
+ rc = ena_com_create_io_queue(ena_dev, &ctx);
if (rc) {
RTE_LOG(ERR, PMD,
"failed to create io TX queue #%d (qid:%d) rc: %d\n",
@@ -780,6 +985,17 @@ static int ena_tx_queue_setup(struct rte_eth_dev *dev,
txq->ena_com_io_cq = &ena_dev->io_cq_queues[ena_qid];
txq->ena_com_io_sq = &ena_dev->io_sq_queues[ena_qid];
+ rc = ena_com_get_io_handlers(ena_dev, ena_qid,
+ &txq->ena_com_io_sq,
+ &txq->ena_com_io_cq);
+ if (rc) {
+ RTE_LOG(ERR, PMD,
+ "Failed to get TX queue handlers. TX queue num %d rc: %d\n",
+ queue_idx, rc);
+ ena_com_destroy_io_queue(ena_dev, ena_qid);
+ goto err;
+ }
+
txq->port_id = dev->data->port_id;
txq->next_to_clean = 0;
txq->next_to_use = 0;
@@ -808,7 +1024,7 @@ static int ena_tx_queue_setup(struct rte_eth_dev *dev,
/* Store pointer to this queue in upper layer */
txq->configured = 1;
dev->data->tx_queues[queue_idx] = txq;
-
+err:
return rc;
}
@@ -819,6 +1035,10 @@ static int ena_rx_queue_setup(struct rte_eth_dev *dev,
__rte_unused const struct rte_eth_rxconf *rx_conf,
struct rte_mempool *mp)
{
+ struct ena_com_create_io_ctx ctx =
+ /* policy set to _HOST just to satisfy icc compiler */
+ { ENA_ADMIN_PLACEMENT_POLICY_HOST,
+ ENA_COM_IO_QUEUE_DIRECTION_RX, 0, 0, 0, 0 };
struct ena_adapter *adapter =
(struct ena_adapter *)(dev->data->dev_private);
struct ena_ring *rxq = NULL;
@@ -842,11 +1062,15 @@ static int ena_rx_queue_setup(struct rte_eth_dev *dev,
}
ena_qid = ENA_IO_RXQ_IDX(queue_idx);
- rc = ena_com_create_io_queue(ena_dev, ena_qid,
- ENA_COM_IO_QUEUE_DIRECTION_RX,
- ENA_ADMIN_PLACEMENT_POLICY_HOST,
- -1 /* admin interrupts not used */,
- nb_desc);
+
+ ctx.qid = ena_qid;
+ ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_RX;
+ ctx.mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
+ ctx.msix_vector = -1; /* admin interrupts not used */
+ ctx.queue_size = adapter->rx_ring_size;
+ ctx.numa_node = ena_cpu_to_node(queue_idx);
+
+ rc = ena_com_create_io_queue(ena_dev, &ctx);
if (rc)
RTE_LOG(ERR, PMD, "failed to create io RX queue #%d rc: %d\n",
queue_idx, rc);
@@ -854,6 +1078,16 @@ static int ena_rx_queue_setup(struct rte_eth_dev *dev,
rxq->ena_com_io_cq = &ena_dev->io_cq_queues[ena_qid];
rxq->ena_com_io_sq = &ena_dev->io_sq_queues[ena_qid];
+ rc = ena_com_get_io_handlers(ena_dev, ena_qid,
+ &rxq->ena_com_io_sq,
+ &rxq->ena_com_io_cq);
+ if (rc) {
+ RTE_LOG(ERR, PMD,
+ "Failed to get RX queue handlers. RX queue num %d rc: %d\n",
+ queue_idx, rc);
+ ena_com_destroy_io_queue(ena_dev, ena_qid);
+ }
+
rxq->port_id = dev->data->port_id;
rxq->next_to_clean = 0;
rxq->next_to_use = 0;
@@ -920,10 +1154,14 @@ static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count)
next_to_use = ENA_RX_RING_IDX_NEXT(next_to_use, ring_size);
}
- rte_wmb();
- rxq->next_to_use = next_to_use;
- /* let HW know that it can fill buffers with data */
- ena_com_write_sq_doorbell(rxq->ena_com_io_sq);
+ /* When we submitted free recources to device... */
+ if (i > 0) {
+ /* ...let HW know that it can fill buffers with data */
+ rte_wmb();
+ ena_com_write_sq_doorbell(rxq->ena_com_io_sq);
+
+ rxq->next_to_use = next_to_use;
+ }
return i;
}
@@ -932,6 +1170,7 @@ static int ena_device_init(struct ena_com_dev *ena_dev,
struct ena_com_dev_get_features_ctx *get_feat_ctx)
{
int rc;
+ bool readless_supported;
/* Initialize mmio registers */
rc = ena_com_mmio_reg_read_request_init(ena_dev);
@@ -940,6 +1179,14 @@ static int ena_device_init(struct ena_com_dev *ena_dev,
return rc;
}
+ /* The PCIe configuration space revision id indicate if mmio reg
+ * read is disabled.
+ */
+ readless_supported =
+ !(((struct rte_pci_device *)ena_dev->dmadev)->id.class_id
+ & ENA_MMIO_DISABLE_REG_READ);
+ ena_com_set_mmio_read_mode(ena_dev, readless_supported);
+
/* reset device */
rc = ena_com_dev_reset(ena_dev);
if (rc) {
@@ -964,6 +1211,8 @@ static int ena_device_init(struct ena_com_dev *ena_dev,
goto err_mmio_read_less;
}
+ ena_config_host_info(ena_dev);
+
/* To enable the msix interrupts the driver needs to know the number
* of queues. So the driver uses polling mode to retrieve this
* information.
@@ -1077,6 +1326,8 @@ static int eth_ena_dev_init(struct rte_eth_dev *eth_dev)
/* prepare ring structures */
ena_init_rings(adapter);
+ ena_config_debug_area(adapter);
+
/* Set max MTU for this device */
adapter->max_mtu = get_feat_ctx.dev_attr.max_mtu;
@@ -1316,7 +1567,7 @@ static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
struct ena_tx_buffer *tx_info;
struct ena_com_buf *ebuf;
uint16_t rc, req_id, total_tx_descs = 0;
- int sent_idx = 0;
+ uint16_t sent_idx = 0;
int nb_hw_desc;
/* Check adapter state */
@@ -1395,9 +1646,14 @@ static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
next_to_use = ENA_TX_RING_IDX_NEXT(next_to_use, ring_size);
}
- /* Let HW do it's best :-) */
- rte_wmb();
- ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq);
+ /* If there are ready packets to be xmitted... */
+ if (sent_idx > 0) {
+ /* ...let HW do its best :-) */
+ rte_wmb();
+ ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq);
+
+ tx_ring->next_to_use = next_to_use;
+ }
/* Clear complete packets */
while (ena_com_tx_comp_req_id_get(tx_ring->ena_com_io_cq, &req_id) >= 0) {
@@ -1420,9 +1676,11 @@ static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
break;
}
- /* acknowledge completion of sent packets */
- ena_com_comp_ack(tx_ring->ena_com_io_sq, total_tx_descs);
- tx_ring->next_to_use = next_to_use;
+ if (total_tx_descs > 0) {
+ /* acknowledge completion of sent packets */
+ ena_com_comp_ack(tx_ring->ena_com_io_sq, total_tx_descs);
+ }
+
return sent_idx;
}
@@ -1445,9 +1703,9 @@ rte_ena_pmd_init(const char *name __rte_unused,
};
struct rte_driver ena_pmd_drv = {
- .name = "ena_driver",
.type = PMD_PDEV,
.init = rte_ena_pmd_init,
};
-PMD_REGISTER_DRIVER(ena_pmd_drv);
+PMD_REGISTER_DRIVER(ena_pmd_drv, ena);
+DRIVER_REGISTER_PCI_TABLE(ena, pci_id_ena_map);
diff --git a/drivers/net/ena/ena_ethdev.h b/drivers/net/ena/ena_ethdev.h
index aca853c1..61390a93 100644
--- a/drivers/net/ena/ena_ethdev.h
+++ b/drivers/net/ena/ena_ethdev.h
@@ -54,6 +54,8 @@
#define ENA_PKT_MAX_BUFS 17
+#define ENA_MMIO_DISABLE_REG_READ BIT(0)
+
#define ENA_CIRC_COUNT(head, tail, size) \
(((uint16_t)((uint16_t)(head) - (uint16_t)(tail))) & ((size) - 1))
@@ -124,6 +126,43 @@ struct ena_driver_stats {
rte_atomic64_t rx_nombuf;
};
+struct ena_stats_dev {
+ u64 tx_timeout;
+ u64 io_suspend;
+ u64 io_resume;
+ u64 wd_expired;
+ u64 interface_up;
+ u64 interface_down;
+ u64 admin_q_pause;
+};
+
+struct ena_stats_tx {
+ u64 cnt;
+ u64 bytes;
+ u64 queue_stop;
+ u64 prepare_ctx_err;
+ u64 queue_wakeup;
+ u64 dma_mapping_err;
+ u64 linearize;
+ u64 linearize_failed;
+ u64 tx_poll;
+ u64 doorbells;
+ u64 missing_tx_comp;
+ u64 bad_req_id;
+};
+
+struct ena_stats_rx {
+ u64 cnt;
+ u64 bytes;
+ u64 refil_partial;
+ u64 bad_csum;
+ u64 page_alloc_fail;
+ u64 skb_alloc_fail;
+ u64 dma_mapping_err;
+ u64 bad_desc_num;
+ u64 small_copy_len_pkt;
+};
+
/* board specific private data structure */
struct ena_adapter {
/* OS defined structs */
diff --git a/drivers/net/enic/base/vnic_wq.c b/drivers/net/enic/base/vnic_wq.c
index 9b9ff4d7..7c4119c3 100644
--- a/drivers/net/enic/base/vnic_wq.c
+++ b/drivers/net/enic/base/vnic_wq.c
@@ -197,6 +197,8 @@ void vnic_wq_clean(struct vnic_wq *wq,
wq->head_idx = 0;
wq->tail_idx = 0;
+ wq->last_completed_index = 0;
+ *((uint32_t *)wq->cqmsg_rz->addr) = 0;
iowrite32(0, &wq->ctrl->fetch_index);
iowrite32(0, &wq->ctrl->posted_index);
diff --git a/drivers/net/enic/enic.h b/drivers/net/enic/enic.h
index 53fed0b8..a5e2e389 100644
--- a/drivers/net/enic/enic.h
+++ b/drivers/net/enic/enic.h
@@ -152,6 +152,12 @@ struct enic {
/* software counters */
struct enic_soft_stats soft_stats;
+ /* configured resources on vic */
+ unsigned int conf_rq_count;
+ unsigned int conf_wq_count;
+ unsigned int conf_cq_count;
+ unsigned int conf_intr_count;
+
/* linked list storing memory allocations */
LIST_HEAD(enic_memzone_list, enic_memzone_entry) memzone_list;
rte_spinlock_t memzone_list_lock;
@@ -221,18 +227,6 @@ enic_ring_incr(uint32_t n_descriptors, uint32_t idx)
return idx;
}
-#if RTE_LOG_LEVEL >= RTE_LOG_DEBUG
-#define ENIC_ASSERT(cond) \
- do { \
- if (unlikely(!(cond))) { \
- rte_panic("line %d\tassert \"" #cond "\"" \
- "failed\n", __LINE__); \
- } \
- } while (0)
-#else
-#define ENIC_ASSERT(cond) do {} while (0)
-#endif
-
extern void enic_fdir_stats_get(struct enic *enic,
struct rte_eth_fdir_stats *stats);
extern int enic_fdir_add_fltr(struct enic *enic,
diff --git a/drivers/net/enic/enic_ethdev.c b/drivers/net/enic/enic_ethdev.c
index a7ce064f..3c87b49e 100644
--- a/drivers/net/enic/enic_ethdev.c
+++ b/drivers/net/enic/enic_ethdev.c
@@ -57,15 +57,11 @@
/*
* The set of PCI devices this driver supports
*/
+#define CISCO_PCI_VENDOR_ID 0x1137
static const struct rte_pci_id pci_id_enic_map[] = {
-#define RTE_PCI_DEV_ID_DECL_ENIC(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
-#ifndef PCI_VENDOR_ID_CISCO
-#define PCI_VENDOR_ID_CISCO 0x1137
-#endif
-#include "rte_pci_dev_ids.h"
-RTE_PCI_DEV_ID_DECL_ENIC(PCI_VENDOR_ID_CISCO, PCI_DEVICE_ID_CISCO_VIC_ENET)
-RTE_PCI_DEV_ID_DECL_ENIC(PCI_VENDOR_ID_CISCO, PCI_DEVICE_ID_CISCO_VIC_ENET_VF)
-{.vendor_id = 0, /* Sentinal */},
+ { RTE_PCI_DEVICE(CISCO_PCI_VENDOR_ID, PCI_DEVICE_ID_CISCO_VIC_ENET) },
+ { RTE_PCI_DEVICE(CISCO_PCI_VENDOR_ID, PCI_DEVICE_ID_CISCO_VIC_ENET_VF) },
+ {.vendor_id = 0, /* sentinel */},
};
static int
@@ -436,8 +432,9 @@ static void enicpmd_dev_info_get(struct rte_eth_dev *eth_dev,
struct enic *enic = pmd_priv(eth_dev);
ENICPMD_FUNC_TRACE();
- device_info->max_rx_queues = enic->rq_count;
- device_info->max_tx_queues = enic->wq_count;
+ /* Scattered Rx uses two receive queues per rx queue exposed to dpdk */
+ device_info->max_rx_queues = enic->conf_rq_count / 2;
+ device_info->max_tx_queues = enic->conf_wq_count;
device_info->min_rx_bufsize = ENIC_MIN_MTU;
device_info->max_rx_pktlen = enic->rte_dev->data->mtu
+ ETHER_HDR_LEN + 4;
@@ -636,4 +633,5 @@ static struct rte_driver rte_enic_driver = {
.init = rte_enic_pmd_init,
};
-PMD_REGISTER_DRIVER(rte_enic_driver);
+PMD_REGISTER_DRIVER(rte_enic_driver, enic);
+DRIVER_REGISTER_PCI_TABLE(enic, pci_id_enic_map);
diff --git a/drivers/net/enic/enic_main.c b/drivers/net/enic/enic_main.c
index dc831b48..d8669cc0 100644
--- a/drivers/net/enic/enic_main.c
+++ b/drivers/net/enic/enic_main.c
@@ -203,7 +203,7 @@ void enic_set_mac_address(struct enic *enic, uint8_t *mac_addr)
return;
}
- err = vnic_dev_del_addr(enic->vdev, mac_addr);
+ err = vnic_dev_del_addr(enic->vdev, enic->mac_addr);
if (err) {
dev_err(enic, "del mac addr failed\n");
return;
@@ -334,6 +334,7 @@ enic_alloc_rx_queue_mbufs(struct enic *enic, struct vnic_rq *rq)
dev_debug(enic, "port=%u, qidx=%u, Write %u posted idx, %u sw held\n",
enic->port_id, rq->index, rq->posted_index, rq->rx_nb_hold);
iowrite32(rq->posted_index, &rq->ctrl->posted_index);
+ iowrite32(0, &rq->ctrl->fetch_index);
rte_rmb();
return 0;
@@ -455,6 +456,8 @@ int enic_enable(struct enic *enic)
for (index = 0; index < enic->rq_count; index++)
enic_start_rq(enic, index);
+ vnic_dev_add_addr(enic->vdev, enic->mac_addr);
+
vnic_dev_enable_wait(enic->vdev);
/* Register and enable error interrupt */
@@ -971,8 +974,6 @@ int enic_setup_finish(struct enic *enic)
return -1;
}
- vnic_dev_add_addr(enic->vdev, enic->mac_addr);
-
/* Default conf */
vnic_dev_packet_filter(enic->vdev,
1 /* directed */,
@@ -1015,21 +1016,23 @@ int enic_set_vnic_res(struct enic *enic)
/* With Rx scatter support, two RQs are now used per RQ used by
* the application.
*/
- if (enic->rq_count < (eth_dev->data->nb_rx_queues * 2)) {
+ if (enic->conf_rq_count < eth_dev->data->nb_rx_queues) {
dev_err(dev, "Not enough Receive queues. Requested:%u which uses %d RQs on VIC, Configured:%u\n",
eth_dev->data->nb_rx_queues,
- eth_dev->data->nb_rx_queues * 2, enic->rq_count);
+ eth_dev->data->nb_rx_queues * 2, enic->conf_rq_count);
rc = -EINVAL;
}
- if (enic->wq_count < eth_dev->data->nb_tx_queues) {
+ if (enic->conf_wq_count < eth_dev->data->nb_tx_queues) {
dev_err(dev, "Not enough Transmit queues. Requested:%u, Configured:%u\n",
- eth_dev->data->nb_tx_queues, enic->wq_count);
+ eth_dev->data->nb_tx_queues, enic->conf_wq_count);
rc = -EINVAL;
}
- if (enic->cq_count < (enic->rq_count + enic->wq_count)) {
+ if (enic->conf_cq_count < (eth_dev->data->nb_rx_queues +
+ eth_dev->data->nb_tx_queues)) {
dev_err(dev, "Not enough Completion queues. Required:%u, Configured:%u\n",
- enic->rq_count + enic->wq_count, enic->cq_count);
+ (eth_dev->data->nb_rx_queues +
+ eth_dev->data->nb_tx_queues), enic->conf_cq_count);
rc = -EINVAL;
}
diff --git a/drivers/net/enic/enic_res.c b/drivers/net/enic/enic_res.c
index b271d340..84c5d336 100644
--- a/drivers/net/enic/enic_res.c
+++ b/drivers/net/enic/enic_res.c
@@ -215,14 +215,14 @@ void enic_free_vnic_resources(struct enic *enic)
void enic_get_res_counts(struct enic *enic)
{
- enic->wq_count = vnic_dev_get_res_count(enic->vdev, RES_TYPE_WQ);
- enic->rq_count = vnic_dev_get_res_count(enic->vdev, RES_TYPE_RQ);
- enic->cq_count = vnic_dev_get_res_count(enic->vdev, RES_TYPE_CQ);
- enic->intr_count = vnic_dev_get_res_count(enic->vdev,
+ enic->conf_wq_count = vnic_dev_get_res_count(enic->vdev, RES_TYPE_WQ);
+ enic->conf_rq_count = vnic_dev_get_res_count(enic->vdev, RES_TYPE_RQ);
+ enic->conf_cq_count = vnic_dev_get_res_count(enic->vdev, RES_TYPE_CQ);
+ enic->conf_intr_count = vnic_dev_get_res_count(enic->vdev,
RES_TYPE_INTR_CTRL);
dev_info(enic_get_dev(enic),
"vNIC resources avail: wq %d rq %d cq %d intr %d\n",
- enic->wq_count, enic->rq_count,
- enic->cq_count, enic->intr_count);
+ enic->conf_wq_count, enic->conf_rq_count,
+ enic->conf_cq_count, enic->conf_intr_count);
}
diff --git a/drivers/net/enic/enic_rxtx.c b/drivers/net/enic/enic_rxtx.c
index 5ac1d69c..2f4a08c5 100644
--- a/drivers/net/enic/enic_rxtx.c
+++ b/drivers/net/enic/enic_rxtx.c
@@ -400,7 +400,7 @@ static inline void enic_free_wq_bufs(struct vnic_wq *wq, u16 completed_index)
buf = &wq->bufs[tail_idx];
m = (struct rte_mbuf *)(buf->mb);
if (likely(m->pool == pool)) {
- ENIC_ASSERT(nb_free < ENIC_MAX_WQ_DESCS);
+ RTE_ASSERT(nb_free < ENIC_MAX_WQ_DESCS);
free[nb_free++] = m;
} else {
rte_mempool_put_bulk(pool, (void *)free, nb_free);
diff --git a/drivers/net/fm10k/fm10k_ethdev.c b/drivers/net/fm10k/fm10k_ethdev.c
index eb77705e..217853fb 100644
--- a/drivers/net/fm10k/fm10k_ethdev.c
+++ b/drivers/net/fm10k/fm10k_ethdev.c
@@ -3049,9 +3049,9 @@ eth_fm10k_dev_uninit(struct rte_eth_dev *dev)
* and SRIOV-VF devices.
*/
static const struct rte_pci_id pci_id_fm10k_map[] = {
-#define RTE_PCI_DEV_ID_DECL_FM10K(vend, dev) { RTE_PCI_DEVICE(vend, dev) },
-#define RTE_PCI_DEV_ID_DECL_FM10KVF(vend, dev) { RTE_PCI_DEVICE(vend, dev) },
-#include "rte_pci_dev_ids.h"
+ { RTE_PCI_DEVICE(FM10K_INTEL_VENDOR_ID, FM10K_DEV_ID_PF) },
+ { RTE_PCI_DEVICE(FM10K_INTEL_VENDOR_ID, FM10K_DEV_ID_SDI_FM10420_QDA2) },
+ { RTE_PCI_DEVICE(FM10K_INTEL_VENDOR_ID, FM10K_DEV_ID_VF) },
{ .vendor_id = 0, /* sentinel */ },
};
@@ -3086,4 +3086,5 @@ static struct rte_driver rte_fm10k_driver = {
.init = rte_pmd_fm10k_init,
};
-PMD_REGISTER_DRIVER(rte_fm10k_driver);
+PMD_REGISTER_DRIVER(rte_fm10k_driver, fm10k);
+DRIVER_REGISTER_PCI_TABLE(fm10k, pci_id_fm10k_map);
diff --git a/drivers/net/fm10k/fm10k_rxtx.c b/drivers/net/fm10k/fm10k_rxtx.c
index dd92a91e..5b2d04bf 100644
--- a/drivers/net/fm10k/fm10k_rxtx.c
+++ b/drivers/net/fm10k/fm10k_rxtx.c
@@ -114,10 +114,10 @@ fm10k_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
nb_pkts = RTE_MIN(nb_pkts, q->alloc_thresh);
for (count = 0; count < nb_pkts; ++count) {
+ if (!(q->hw_ring[next_dd].d.staterr & FM10K_RXD_STATUS_DD))
+ break;
mbuf = q->sw_ring[next_dd];
desc = q->hw_ring[next_dd];
- if (!(desc.d.staterr & FM10K_RXD_STATUS_DD))
- break;
#ifdef RTE_LIBRTE_FM10K_DEBUG_RX
dump_rxd(&desc);
#endif
@@ -228,10 +228,10 @@ fm10k_recv_scattered_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
nb_seg = RTE_MIN(nb_pkts, q->alloc_thresh);
for (count = 0; count < nb_seg; count++) {
+ if (!(q->hw_ring[next_dd].d.staterr & FM10K_RXD_STATUS_DD))
+ break;
mbuf = q->sw_ring[next_dd];
desc = q->hw_ring[next_dd];
- if (!(desc.d.staterr & FM10K_RXD_STATUS_DD))
- break;
#ifdef RTE_LIBRTE_FM10K_DEBUG_RX
dump_rxd(&desc);
#endif
diff --git a/drivers/net/i40e/i40e_ethdev.c b/drivers/net/i40e/i40e_ethdev.c
index f414d938..daac2361 100644
--- a/drivers/net/i40e/i40e_ethdev.c
+++ b/drivers/net/i40e/i40e_ethdev.c
@@ -440,8 +440,6 @@ static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
uint16_t queue_id);
-static int i40e_get_reg_length(struct rte_eth_dev *dev);
-
static int i40e_get_regs(struct rte_eth_dev *dev,
struct rte_dev_reg_info *regs);
@@ -456,9 +454,28 @@ static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
static const struct rte_pci_id pci_id_i40e_map[] = {
-#define RTE_PCI_DEV_ID_DECL_I40E(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
-#include "rte_pci_dev_ids.h"
-{ .vendor_id = 0, /* sentinel */ },
+ { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
+ { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
+ { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
+ { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
+ { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
+ { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
+ { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
+ { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
+ { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
+ { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
+ { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
+ { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
+ { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
+ { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
+ { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
+ { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
+ { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
+ { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
+ { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
+ { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
+ { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_I_X722) },
+ { .vendor_id = 0, /* sentinel */ },
};
static const struct eth_dev_ops i40e_eth_dev_ops = {
@@ -524,7 +541,6 @@ static const struct eth_dev_ops i40e_eth_dev_ops = {
.timesync_adjust_time = i40e_timesync_adjust_time,
.timesync_read_time = i40e_timesync_read_time,
.timesync_write_time = i40e_timesync_write_time,
- .get_reg_length = i40e_get_reg_length,
.get_reg = i40e_get_regs,
.get_eeprom_length = i40e_get_eeprom_length,
.get_eeprom = i40e_get_eeprom,
@@ -705,7 +721,8 @@ static struct rte_driver rte_i40e_driver = {
.init = rte_i40e_pmd_init,
};
-PMD_REGISTER_DRIVER(rte_i40e_driver);
+PMD_REGISTER_DRIVER(rte_i40e_driver, i40e);
+DRIVER_REGISTER_PCI_TABLE(i40e, pci_id_i40e_map);
/*
* Initialize registers for flexible payload, which should be set by NVM.
@@ -2701,12 +2718,16 @@ i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
{
struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
struct i40e_vsi *vsi = pf->main_vsi;
+ struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
if (mask & ETH_VLAN_FILTER_MASK) {
- if (dev->data->dev_conf.rxmode.hw_vlan_filter)
+ if (dev->data->dev_conf.rxmode.hw_vlan_filter) {
+ i40e_aq_set_vsi_vlan_promisc(hw, vsi->seid, false, NULL);
i40e_vsi_config_vlan_filter(vsi, TRUE);
- else
+ } else {
+ i40e_aq_set_vsi_vlan_promisc(hw, vsi->seid, true, NULL);
i40e_vsi_config_vlan_filter(vsi, FALSE);
+ }
}
if (mask & ETH_VLAN_STRIP_MASK) {
@@ -2952,9 +2973,10 @@ i40e_macaddr_add(struct rte_eth_dev *dev,
int ret;
/* If VMDQ not enabled or configured, return */
- if (pool != 0 && (!(pf->flags | I40E_FLAG_VMDQ) || !pf->nb_cfg_vmdq_vsi)) {
+ if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
+ !pf->nb_cfg_vmdq_vsi)) {
PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
- pf->flags | I40E_FLAG_VMDQ ? "configured" : "enabled",
+ pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
pool);
return;
}
@@ -3005,7 +3027,7 @@ i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
vsi = pf->main_vsi;
else {
/* No VMDQ pool enabled or configured */
- if (!(pf->flags | I40E_FLAG_VMDQ) ||
+ if (!(pf->flags & I40E_FLAG_VMDQ) ||
(i > pf->nb_cfg_vmdq_vsi)) {
PMD_DRV_LOG(ERR, "No VMDQ pool enabled"
"/configured");
@@ -3167,13 +3189,16 @@ i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
static int
i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
{
- struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
- struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
+ struct i40e_pf *pf;
+ struct i40e_hw *hw;
int ret;
if (!vsi || !lut)
return -EINVAL;
+ pf = I40E_VSI_TO_PF(vsi);
+ hw = I40E_VSI_TO_HW(vsi);
+
if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
lut, lut_size);
@@ -5752,17 +5777,28 @@ i40e_set_vlan_filter(struct i40e_vsi *vsi,
uint16_t vlan_id, bool on)
{
uint32_t vid_idx, vid_bit;
+ struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
+ struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
+ int ret;
if (vlan_id > ETH_VLAN_ID_MAX)
return;
vid_idx = I40E_VFTA_IDX(vlan_id);
vid_bit = I40E_VFTA_BIT(vlan_id);
+ vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
- if (on)
+ if (on) {
+ ret = i40e_aq_add_vlan(hw, vsi->seid, &vlan_data, 1, NULL);
+ if (ret != I40E_SUCCESS)
+ PMD_DRV_LOG(ERR, "Failed to add vlan filter");
vsi->vfta[vid_idx] |= vid_bit;
- else
+ } else {
+ ret = i40e_aq_remove_vlan(hw, vsi->seid, &vlan_data, 1, NULL);
+ if (ret != I40E_SUCCESS)
+ PMD_DRV_LOG(ERR, "Failed to remove vlan filter");
vsi->vfta[vid_idx] &= ~vid_bit;
+ }
}
/**
@@ -6904,6 +6940,9 @@ i40e_get_hash_filter_global_config(struct i40e_hw *hw,
mask &= ~(1UL << i);
/* Bit set indicats the coresponding flow type is supported */
g_cfg->valid_bit_mask[0] |= (1UL << i);
+ /* if flowtype is invalid, continue */
+ if (!I40E_VALID_FLOW(i))
+ continue;
pctype = i40e_flowtype_to_pctype(i);
reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(pctype));
if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK)
@@ -6975,6 +7014,9 @@ i40e_set_hash_filter_global_config(struct i40e_hw *hw,
if (!(mask0 & (1UL << i)))
continue;
mask0 &= ~(1UL << i);
+ /* if flowtype is invalid, continue */
+ if (!I40E_VALID_FLOW(i))
+ continue;
pctype = i40e_flowtype_to_pctype(i);
reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
@@ -7537,13 +7579,11 @@ i40e_hash_filter_inset_select(struct i40e_hw *hw,
return -EINVAL;
}
- pctype = i40e_flowtype_to_pctype(conf->flow_type);
- if (pctype == 0 || pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD) {
- PMD_DRV_LOG(ERR, "Not supported flow type (%u)",
- conf->flow_type);
+ if (!I40E_VALID_FLOW(conf->flow_type)) {
+ PMD_DRV_LOG(ERR, "invalid flow_type input.");
return -EINVAL;
}
-
+ pctype = i40e_flowtype_to_pctype(conf->flow_type);
ret = i40e_parse_input_set(&input_set, pctype, conf->field,
conf->inset_size);
if (ret) {
@@ -7608,12 +7648,11 @@ i40e_fdir_filter_inset_select(struct i40e_pf *pf,
return -EINVAL;
}
- pctype = i40e_flowtype_to_pctype(conf->flow_type);
- if (pctype == 0 || pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD) {
- PMD_DRV_LOG(ERR, "Not supported flow type (%u)",
- conf->flow_type);
+ if (!I40E_VALID_FLOW(conf->flow_type)) {
+ PMD_DRV_LOG(ERR, "invalid flow_type input.");
return -EINVAL;
}
+ pctype = i40e_flowtype_to_pctype(conf->flow_type);
ret = i40e_parse_input_set(&input_set, pctype, conf->field,
conf->inset_size);
if (ret) {
@@ -9342,12 +9381,6 @@ i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
return 0;
}
-static int i40e_get_reg_length(__rte_unused struct rte_eth_dev *dev)
-{
- /* Highest base addr + 32-bit word */
- return I40E_GLGEN_STAT_CLEAR + 4;
-}
-
static int i40e_get_regs(struct rte_eth_dev *dev,
struct rte_dev_reg_info *regs)
{
@@ -9356,6 +9389,12 @@ static int i40e_get_regs(struct rte_eth_dev *dev,
uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
const struct i40e_reg_info *reg_info;
+ if (ptr_data == NULL) {
+ regs->length = I40E_GLGEN_STAT_CLEAR + 4;
+ regs->width = sizeof(uint32_t);
+ return 0;
+ }
+
/* The first few registers have to be read using AQ operations */
reg_idx = 0;
while (i40e_regs_adminq[reg_idx].name) {
diff --git a/drivers/net/i40e/i40e_ethdev_vf.c b/drivers/net/i40e/i40e_ethdev_vf.c
index 7b6df1d8..a616ae0b 100644
--- a/drivers/net/i40e/i40e_ethdev_vf.c
+++ b/drivers/net/i40e/i40e_ethdev_vf.c
@@ -1110,9 +1110,12 @@ i40evf_get_link_status(struct rte_eth_dev *dev, struct rte_eth_link *link)
}
static const struct rte_pci_id pci_id_i40evf_map[] = {
-#define RTE_PCI_DEV_ID_DECL_I40EVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
-#include "rte_pci_dev_ids.h"
-{ .vendor_id = 0, /* sentinel */ },
+ { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_VF) },
+ { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_VF_HV) },
+ { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0_VF) },
+ { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_VF) },
+ { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_VF_HV) },
+ { .vendor_id = 0, /* sentinel */ },
};
static inline int
@@ -1581,7 +1584,8 @@ static struct rte_driver rte_i40evf_driver = {
.init = rte_i40evf_pmd_init,
};
-PMD_REGISTER_DRIVER(rte_i40evf_driver);
+PMD_REGISTER_DRIVER(rte_i40evf_driver, i40evf);
+DRIVER_REGISTER_PCI_TABLE(i40evf, pci_id_i40evf_map);
static int
i40evf_dev_configure(struct rte_eth_dev *dev)
@@ -2377,13 +2381,16 @@ i40evf_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
static int
i40evf_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
{
- struct i40e_vf *vf = I40E_VSI_TO_VF(vsi);
- struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
+ struct i40e_vf *vf;
+ struct i40e_hw *hw;
int ret;
if (!vsi || !lut)
return -EINVAL;
+ vf = I40E_VSI_TO_VF(vsi);
+ hw = I40E_VSI_TO_HW(vsi);
+
if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, FALSE,
lut, lut_size);
diff --git a/drivers/net/ixgbe/ixgbe_ethdev.c b/drivers/net/ixgbe/ixgbe_ethdev.c
index 0629b426..d478a159 100644
--- a/drivers/net/ixgbe/ixgbe_ethdev.c
+++ b/drivers/net/ixgbe/ixgbe_ethdev.c
@@ -538,7 +538,6 @@ static const struct eth_dev_ops ixgbe_eth_dev_ops = {
.timesync_disable = ixgbe_timesync_disable,
.timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
.timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
- .get_reg_length = ixgbe_get_reg_length,
.get_reg = ixgbe_get_regs,
.get_eeprom_length = ixgbe_get_eeprom_length,
.get_eeprom = ixgbe_get_eeprom,
@@ -589,7 +588,6 @@ static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
.rxq_info_get = ixgbe_rxq_info_get,
.txq_info_get = ixgbe_txq_info_get,
.mac_addr_set = ixgbevf_set_default_mac_addr,
- .get_reg_length = ixgbevf_get_reg_length,
.get_reg = ixgbevf_get_regs,
.reta_update = ixgbe_dev_rss_reta_update,
.reta_query = ixgbe_dev_rss_reta_query,
@@ -6316,6 +6314,12 @@ ixgbe_get_regs(struct rte_eth_dev *dev,
const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
ixgbe_regs_mac_82598EB : ixgbe_regs_others;
+ if (data == NULL) {
+ regs->length = ixgbe_get_reg_length(dev);
+ regs->width = sizeof(uint32_t);
+ return 0;
+ }
+
/* Support only full register dump */
if ((regs->length == 0) ||
(regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
@@ -6340,6 +6344,12 @@ ixgbevf_get_regs(struct rte_eth_dev *dev,
int count = 0;
const struct reg_info *reg_group;
+ if (data == NULL) {
+ regs->length = ixgbevf_get_reg_length(dev);
+ regs->width = sizeof(uint32_t);
+ return 0;
+ }
+
/* Support only full register dump */
if ((regs->length == 0) ||
(regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
@@ -7352,5 +7362,7 @@ static struct rte_driver rte_ixgbevf_driver = {
.init = rte_ixgbevf_pmd_init,
};
-PMD_REGISTER_DRIVER(rte_ixgbe_driver);
-PMD_REGISTER_DRIVER(rte_ixgbevf_driver);
+PMD_REGISTER_DRIVER(rte_ixgbe_driver, ixgbe);
+DRIVER_REGISTER_PCI_TABLE(ixgbe, pci_id_ixgbe_map);
+PMD_REGISTER_DRIVER(rte_ixgbevf_driver, ixgbevf);
+DRIVER_REGISTER_PCI_TABLE(ixgbevf, pci_id_ixgbevf_map);
diff --git a/drivers/net/ixgbe/ixgbe_rxtx_vec_sse.c b/drivers/net/ixgbe/ixgbe_rxtx_vec_sse.c
index 4f95debd..1c4fd7c1 100644
--- a/drivers/net/ixgbe/ixgbe_rxtx_vec_sse.c
+++ b/drivers/net/ixgbe/ixgbe_rxtx_vec_sse.c
@@ -197,7 +197,9 @@ desc_to_olflags_v(__m128i descs[4], uint8_t vlan_flags,
rx_pkts[3]->ol_flags = vol.e[3];
}
#else
-#define desc_to_olflags_v(desc, rx_pkts) do {} while (0)
+#define desc_to_olflags_v(desc, vlan_flags, rx_pkts) do { \
+ RTE_SET_USED(vlan_flags); \
+ } while (0)
#endif
/*
diff --git a/drivers/net/mlx4/mlx4.c b/drivers/net/mlx4/mlx4.c
index f8ed42b8..304c8461 100644
--- a/drivers/net/mlx4/mlx4.c
+++ b/drivers/net/mlx4/mlx4.c
@@ -689,7 +689,7 @@ priv_set_flags(struct priv *priv, unsigned int keep, unsigned int flags)
if (priv_get_sysfs_ulong(priv, "flags", &tmp) == -1)
return -1;
tmp &= keep;
- tmp |= flags;
+ tmp |= (flags & (~keep));
return priv_set_sysfs_ulong(priv, "flags", tmp);
}
@@ -4328,6 +4328,90 @@ mlx4_dev_close(struct rte_eth_dev *dev)
}
/**
+ * Change the link state (UP / DOWN).
+ *
+ * @param priv
+ * Pointer to Ethernet device private data.
+ * @param up
+ * Nonzero for link up, otherwise link down.
+ *
+ * @return
+ * 0 on success, errno value on failure.
+ */
+static int
+priv_set_link(struct priv *priv, int up)
+{
+ struct rte_eth_dev *dev = priv->dev;
+ int err;
+ unsigned int i;
+
+ if (up) {
+ err = priv_set_flags(priv, ~IFF_UP, IFF_UP);
+ if (err)
+ return err;
+ for (i = 0; i < priv->rxqs_n; i++)
+ if ((*priv->rxqs)[i]->sp)
+ break;
+ /* Check if an sp queue exists.
+ * Note: Some old frames might be received.
+ */
+ if (i == priv->rxqs_n)
+ dev->rx_pkt_burst = mlx4_rx_burst;
+ else
+ dev->rx_pkt_burst = mlx4_rx_burst_sp;
+ dev->tx_pkt_burst = mlx4_tx_burst;
+ } else {
+ err = priv_set_flags(priv, ~IFF_UP, ~IFF_UP);
+ if (err)
+ return err;
+ dev->rx_pkt_burst = removed_rx_burst;
+ dev->tx_pkt_burst = removed_tx_burst;
+ }
+ return 0;
+}
+
+/**
+ * DPDK callback to bring the link DOWN.
+ *
+ * @param dev
+ * Pointer to Ethernet device structure.
+ *
+ * @return
+ * 0 on success, errno value on failure.
+ */
+static int
+mlx4_set_link_down(struct rte_eth_dev *dev)
+{
+ struct priv *priv = dev->data->dev_private;
+ int err;
+
+ priv_lock(priv);
+ err = priv_set_link(priv, 0);
+ priv_unlock(priv);
+ return err;
+}
+
+/**
+ * DPDK callback to bring the link UP.
+ *
+ * @param dev
+ * Pointer to Ethernet device structure.
+ *
+ * @return
+ * 0 on success, errno value on failure.
+ */
+static int
+mlx4_set_link_up(struct rte_eth_dev *dev)
+{
+ struct priv *priv = dev->data->dev_private;
+ int err;
+
+ priv_lock(priv);
+ err = priv_set_link(priv, 1);
+ priv_unlock(priv);
+ return err;
+}
+/**
* DPDK callback to get information about the device.
*
* @param dev
@@ -5134,6 +5218,8 @@ static const struct eth_dev_ops mlx4_dev_ops = {
.dev_configure = mlx4_dev_configure,
.dev_start = mlx4_dev_start,
.dev_stop = mlx4_dev_stop,
+ .dev_set_link_down = mlx4_set_link_down,
+ .dev_set_link_up = mlx4_set_link_up,
.dev_close = mlx4_dev_close,
.promiscuous_enable = mlx4_promiscuous_enable,
.promiscuous_disable = mlx4_promiscuous_disable,
@@ -5857,8 +5943,8 @@ rte_mlx4_pmd_init(const char *name, const char *args)
static struct rte_driver rte_mlx4_driver = {
.type = PMD_PDEV,
- .name = MLX4_DRIVER_NAME,
.init = rte_mlx4_pmd_init,
};
-PMD_REGISTER_DRIVER(rte_mlx4_driver)
+PMD_REGISTER_DRIVER(rte_mlx4_driver, mlx4);
+DRIVER_REGISTER_PCI_TABLE(mlx4, mlx4_pci_id_map);
diff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c
index 5aa4adc6..d96a9aff 100644
--- a/drivers/net/mlx5/mlx5.c
+++ b/drivers/net/mlx5/mlx5.c
@@ -758,8 +758,8 @@ rte_mlx5_pmd_init(const char *name, const char *args)
static struct rte_driver rte_mlx5_driver = {
.type = PMD_PDEV,
- .name = MLX5_DRIVER_NAME,
.init = rte_mlx5_pmd_init,
};
-PMD_REGISTER_DRIVER(rte_mlx5_driver)
+PMD_REGISTER_DRIVER(rte_mlx5_driver, mlx5);
+DRIVER_REGISTER_PCI_TABLE(mlx5, mlx5_pci_id_map);
diff --git a/drivers/net/mlx5/mlx5_ethdev.c b/drivers/net/mlx5/mlx5_ethdev.c
index 0e7ed019..130e15d5 100644
--- a/drivers/net/mlx5/mlx5_ethdev.c
+++ b/drivers/net/mlx5/mlx5_ethdev.c
@@ -461,7 +461,7 @@ priv_set_flags(struct priv *priv, unsigned int keep, unsigned int flags)
if (priv_get_sysfs_ulong(priv, "flags", &tmp) == -1)
return -1;
tmp &= keep;
- tmp |= flags;
+ tmp |= (flags & (~keep));
return priv_set_sysfs_ulong(priv, "flags", tmp);
}
@@ -1150,7 +1150,7 @@ priv_dev_interrupt_handler_install(struct priv *priv, struct rte_eth_dev *dev)
/**
* Change the link state (UP / DOWN).
*
- * @param dev
+ * @param priv
* Pointer to Ethernet device structure.
* @param up
* Nonzero for link up, otherwise link down.
diff --git a/drivers/net/mlx5/mlx5_rxtx.c b/drivers/net/mlx5/mlx5_rxtx.c
index 0c352f3f..615de945 100644
--- a/drivers/net/mlx5/mlx5_rxtx.c
+++ b/drivers/net/mlx5/mlx5_rxtx.c
@@ -1572,7 +1572,8 @@ mlx5_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
rte_prefetch0(wqe);
rep = rte_mbuf_raw_alloc(rxq->mp);
if (unlikely(rep == NULL)) {
- while (pkt) {
+ while (pkt != seg) {
+ assert(pkt != (*rxq->elts)[idx]);
seg = NEXT(pkt);
rte_mbuf_refcnt_set(pkt, 0);
__rte_mbuf_raw_free(pkt);
@@ -1599,6 +1600,8 @@ mlx5_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
pkt = seg;
assert(len >= (rxq->crc_present << 2));
/* Update packet information. */
+ pkt->packet_type = 0;
+ pkt->ol_flags = 0;
if (rxq->csum | rxq->csum_l2tun | rxq->vlan_strip |
rxq->crc_present) {
if (rxq->csum) {
diff --git a/drivers/net/mpipe/mpipe_tilegx.c b/drivers/net/mpipe/mpipe_tilegx.c
index 26e14248..93f87308 100644
--- a/drivers/net/mpipe/mpipe_tilegx.c
+++ b/drivers/net/mpipe/mpipe_tilegx.c
@@ -1624,19 +1624,17 @@ rte_pmd_mpipe_devinit(const char *ifname,
}
static struct rte_driver pmd_mpipe_xgbe_drv = {
- .name = "xgbe",
.type = PMD_VDEV,
.init = rte_pmd_mpipe_devinit,
};
static struct rte_driver pmd_mpipe_gbe_drv = {
- .name = "gbe",
.type = PMD_VDEV,
.init = rte_pmd_mpipe_devinit,
};
-PMD_REGISTER_DRIVER(pmd_mpipe_xgbe_drv);
-PMD_REGISTER_DRIVER(pmd_mpipe_gbe_drv);
+PMD_REGISTER_DRIVER(pmd_mpipe_xgbe_drv, xgbe);
+PMD_REGISTER_DRIVER(pmd_mpipe_gbe_drv, gbe);
static void __attribute__((constructor, used))
mpipe_init_contexts(void)
diff --git a/drivers/net/nfp/nfp_net.c b/drivers/net/nfp/nfp_net.c
index 6afd49b1..82e3e4e1 100644
--- a/drivers/net/nfp/nfp_net.c
+++ b/drivers/net/nfp/nfp_net.c
@@ -2486,7 +2486,8 @@ static struct rte_driver rte_nfp_net_driver = {
.init = nfp_net_pmd_init,
};
-PMD_REGISTER_DRIVER(rte_nfp_net_driver);
+PMD_REGISTER_DRIVER(rte_nfp_net_driver, nfp);
+DRIVER_REGISTER_PCI_TABLE(nfp, pci_id_nfp_net_map);
/*
* Local variables:
diff --git a/drivers/net/null/rte_eth_null.c b/drivers/net/null/rte_eth_null.c
index ab440f3b..7a248842 100644
--- a/drivers/net/null/rte_eth_null.c
+++ b/drivers/net/null/rte_eth_null.c
@@ -687,10 +687,12 @@ rte_pmd_null_devuninit(const char *name)
}
static struct rte_driver pmd_null_drv = {
- .name = "eth_null",
.type = PMD_VDEV,
.init = rte_pmd_null_devinit,
.uninit = rte_pmd_null_devuninit,
};
-PMD_REGISTER_DRIVER(pmd_null_drv);
+PMD_REGISTER_DRIVER(pmd_null_drv, eth_null);
+DRIVER_REGISTER_PARAM_STRING(eth_null,
+ "size=<int> "
+ "copy=<int>");
diff --git a/drivers/net/pcap/rte_eth_pcap.c b/drivers/net/pcap/rte_eth_pcap.c
index c86f17b6..7e213ebb 100644
--- a/drivers/net/pcap/rte_eth_pcap.c
+++ b/drivers/net/pcap/rte_eth_pcap.c
@@ -1084,10 +1084,15 @@ rte_pmd_pcap_devuninit(const char *name)
}
static struct rte_driver pmd_pcap_drv = {
- .name = "eth_pcap",
.type = PMD_VDEV,
.init = rte_pmd_pcap_devinit,
.uninit = rte_pmd_pcap_devuninit,
};
-PMD_REGISTER_DRIVER(pmd_pcap_drv);
+PMD_REGISTER_DRIVER(pmd_pcap_drv, eth_pcap);
+DRIVER_REGISTER_PARAM_STRING(eth_pcap,
+ "rx_pcap=<string> "
+ "tx_pcap=<string> "
+ "rx_iface=<ifc> "
+ "tx_iface=<ifc> "
+ "iface=<ifc>");
diff --git a/drivers/net/qede/qede_ethdev.c b/drivers/net/qede/qede_ethdev.c
index bb531be5..82e44b8f 100644
--- a/drivers/net/qede/qede_ethdev.c
+++ b/drivers/net/qede/qede_ethdev.c
@@ -14,6 +14,151 @@ static const struct qed_eth_ops *qed_ops;
static const char *drivername = "qede pmd";
static int64_t timer_period = 1;
+struct rte_qede_xstats_name_off {
+ char name[RTE_ETH_XSTATS_NAME_SIZE];
+ uint64_t offset;
+};
+
+static const struct rte_qede_xstats_name_off qede_xstats_strings[] = {
+ {"rx_unicast_bytes", offsetof(struct ecore_eth_stats, rx_ucast_bytes)},
+ {"rx_multicast_bytes",
+ offsetof(struct ecore_eth_stats, rx_mcast_bytes)},
+ {"rx_broadcast_bytes",
+ offsetof(struct ecore_eth_stats, rx_bcast_bytes)},
+ {"rx_unicast_packets", offsetof(struct ecore_eth_stats, rx_ucast_pkts)},
+ {"rx_multicast_packets",
+ offsetof(struct ecore_eth_stats, rx_mcast_pkts)},
+ {"rx_broadcast_packets",
+ offsetof(struct ecore_eth_stats, rx_bcast_pkts)},
+
+ {"tx_unicast_bytes", offsetof(struct ecore_eth_stats, tx_ucast_bytes)},
+ {"tx_multicast_bytes",
+ offsetof(struct ecore_eth_stats, tx_mcast_bytes)},
+ {"tx_broadcast_bytes",
+ offsetof(struct ecore_eth_stats, tx_bcast_bytes)},
+ {"tx_unicast_packets", offsetof(struct ecore_eth_stats, tx_ucast_pkts)},
+ {"tx_multicast_packets",
+ offsetof(struct ecore_eth_stats, tx_mcast_pkts)},
+ {"tx_broadcast_packets",
+ offsetof(struct ecore_eth_stats, tx_bcast_pkts)},
+
+ {"rx_64_byte_packets",
+ offsetof(struct ecore_eth_stats, rx_64_byte_packets)},
+ {"rx_65_to_127_byte_packets",
+ offsetof(struct ecore_eth_stats, rx_65_to_127_byte_packets)},
+ {"rx_128_to_255_byte_packets",
+ offsetof(struct ecore_eth_stats, rx_128_to_255_byte_packets)},
+ {"rx_256_to_511_byte_packets",
+ offsetof(struct ecore_eth_stats, rx_256_to_511_byte_packets)},
+ {"rx_512_to_1023_byte_packets",
+ offsetof(struct ecore_eth_stats, rx_512_to_1023_byte_packets)},
+ {"rx_1024_to_1518_byte_packets",
+ offsetof(struct ecore_eth_stats, rx_1024_to_1518_byte_packets)},
+ {"rx_1519_to_1522_byte_packets",
+ offsetof(struct ecore_eth_stats, rx_1519_to_1522_byte_packets)},
+ {"rx_1519_to_2047_byte_packets",
+ offsetof(struct ecore_eth_stats, rx_1519_to_2047_byte_packets)},
+ {"rx_2048_to_4095_byte_packets",
+ offsetof(struct ecore_eth_stats, rx_2048_to_4095_byte_packets)},
+ {"rx_4096_to_9216_byte_packets",
+ offsetof(struct ecore_eth_stats, rx_4096_to_9216_byte_packets)},
+ {"rx_9217_to_16383_byte_packets",
+ offsetof(struct ecore_eth_stats,
+ rx_9217_to_16383_byte_packets)},
+ {"tx_64_byte_packets",
+ offsetof(struct ecore_eth_stats, tx_64_byte_packets)},
+ {"tx_65_to_127_byte_packets",
+ offsetof(struct ecore_eth_stats, tx_65_to_127_byte_packets)},
+ {"tx_128_to_255_byte_packets",
+ offsetof(struct ecore_eth_stats, tx_128_to_255_byte_packets)},
+ {"tx_256_to_511_byte_packets",
+ offsetof(struct ecore_eth_stats, tx_256_to_511_byte_packets)},
+ {"tx_512_to_1023_byte_packets",
+ offsetof(struct ecore_eth_stats, tx_512_to_1023_byte_packets)},
+ {"tx_1024_to_1518_byte_packets",
+ offsetof(struct ecore_eth_stats, tx_1024_to_1518_byte_packets)},
+ {"trx_1519_to_1522_byte_packets",
+ offsetof(struct ecore_eth_stats, tx_1519_to_2047_byte_packets)},
+ {"tx_2048_to_4095_byte_packets",
+ offsetof(struct ecore_eth_stats, tx_2048_to_4095_byte_packets)},
+ {"tx_4096_to_9216_byte_packets",
+ offsetof(struct ecore_eth_stats, tx_4096_to_9216_byte_packets)},
+ {"tx_9217_to_16383_byte_packets",
+ offsetof(struct ecore_eth_stats,
+ tx_9217_to_16383_byte_packets)},
+
+ {"rx_mac_crtl_frames",
+ offsetof(struct ecore_eth_stats, rx_mac_crtl_frames)},
+ {"tx_mac_control_frames",
+ offsetof(struct ecore_eth_stats, tx_mac_ctrl_frames)},
+ {"rx_pause_frames", offsetof(struct ecore_eth_stats, rx_pause_frames)},
+ {"tx_pause_frames", offsetof(struct ecore_eth_stats, tx_pause_frames)},
+ {"rx_priority_flow_control_frames",
+ offsetof(struct ecore_eth_stats, rx_pfc_frames)},
+ {"tx_priority_flow_control_frames",
+ offsetof(struct ecore_eth_stats, tx_pfc_frames)},
+
+ {"rx_crc_errors", offsetof(struct ecore_eth_stats, rx_crc_errors)},
+ {"rx_align_errors", offsetof(struct ecore_eth_stats, rx_align_errors)},
+ {"rx_carrier_errors",
+ offsetof(struct ecore_eth_stats, rx_carrier_errors)},
+ {"rx_oversize_packet_errors",
+ offsetof(struct ecore_eth_stats, rx_oversize_packets)},
+ {"rx_jabber_errors", offsetof(struct ecore_eth_stats, rx_jabbers)},
+ {"rx_undersize_packet_errors",
+ offsetof(struct ecore_eth_stats, rx_undersize_packets)},
+ {"rx_fragments", offsetof(struct ecore_eth_stats, rx_fragments)},
+ {"rx_host_buffer_not_available",
+ offsetof(struct ecore_eth_stats, no_buff_discards)},
+ /* Number of packets discarded because they are bigger than MTU */
+ {"rx_packet_too_big_discards",
+ offsetof(struct ecore_eth_stats, packet_too_big_discard)},
+ {"rx_ttl_zero_discards",
+ offsetof(struct ecore_eth_stats, ttl0_discard)},
+ {"rx_multi_function_tag_filter_discards",
+ offsetof(struct ecore_eth_stats, mftag_filter_discards)},
+ {"rx_mac_filter_discards",
+ offsetof(struct ecore_eth_stats, mac_filter_discards)},
+ {"rx_hw_buffer_truncates",
+ offsetof(struct ecore_eth_stats, brb_truncates)},
+ {"rx_hw_buffer_discards",
+ offsetof(struct ecore_eth_stats, brb_discards)},
+ {"tx_lpi_entry_count",
+ offsetof(struct ecore_eth_stats, tx_lpi_entry_count)},
+ {"tx_total_collisions",
+ offsetof(struct ecore_eth_stats, tx_total_collisions)},
+ {"tx_error_drop_packets",
+ offsetof(struct ecore_eth_stats, tx_err_drop_pkts)},
+
+ {"rx_mac_bytes", offsetof(struct ecore_eth_stats, rx_mac_bytes)},
+ {"rx_mac_unicast_packets",
+ offsetof(struct ecore_eth_stats, rx_mac_uc_packets)},
+ {"rx_mac_multicast_packets",
+ offsetof(struct ecore_eth_stats, rx_mac_mc_packets)},
+ {"rx_mac_broadcast_packets",
+ offsetof(struct ecore_eth_stats, rx_mac_bc_packets)},
+ {"rx_mac_frames_ok",
+ offsetof(struct ecore_eth_stats, rx_mac_frames_ok)},
+ {"tx_mac_bytes", offsetof(struct ecore_eth_stats, tx_mac_bytes)},
+ {"tx_mac_unicast_packets",
+ offsetof(struct ecore_eth_stats, tx_mac_uc_packets)},
+ {"tx_mac_multicast_packets",
+ offsetof(struct ecore_eth_stats, tx_mac_mc_packets)},
+ {"tx_mac_broadcast_packets",
+ offsetof(struct ecore_eth_stats, tx_mac_bc_packets)},
+
+ {"lro_coalesced_packets",
+ offsetof(struct ecore_eth_stats, tpa_coalesced_pkts)},
+ {"lro_coalesced_events",
+ offsetof(struct ecore_eth_stats, tpa_coalesced_events)},
+ {"lro_aborts_num",
+ offsetof(struct ecore_eth_stats, tpa_aborts_num)},
+ {"lro_not_coalesced_packets",
+ offsetof(struct ecore_eth_stats, tpa_not_coalesced_pkts)},
+ {"lro_coalesced_bytes",
+ offsetof(struct ecore_eth_stats, tpa_coalesced_bytes)},
+};
+
static void qede_interrupt_action(struct ecore_hwfn *p_hwfn)
{
ecore_int_sp_dpc((osal_int_ptr_t)(p_hwfn));
@@ -651,15 +796,52 @@ qede_get_stats(struct rte_eth_dev *eth_dev, struct rte_eth_stats *eth_stats)
stats.tx_mcast_bytes + stats.tx_bcast_bytes;
eth_stats->oerrors = stats.tx_err_drop_pkts;
+}
+
+static int
+qede_get_xstats_names(__rte_unused struct rte_eth_dev *dev,
+ struct rte_eth_xstat_name *xstats_names, unsigned limit)
+{
+ unsigned int i, stat_cnt = RTE_DIM(qede_xstats_strings);
- DP_INFO(edev,
- "no_buff_discards=%" PRIu64 ""
- " mac_filter_discards=%" PRIu64 ""
- " brb_truncates=%" PRIu64 ""
- " brb_discards=%" PRIu64 "\n",
- stats.no_buff_discards,
- stats.mac_filter_discards,
- stats.brb_truncates, stats.brb_discards);
+ if (xstats_names != NULL)
+ for (i = 0; i < stat_cnt; i++)
+ snprintf(xstats_names[i].name,
+ sizeof(xstats_names[i].name),
+ "%s",
+ qede_xstats_strings[i].name);
+
+ return stat_cnt;
+}
+
+static int
+qede_get_xstats(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
+ unsigned int n)
+{
+ struct qede_dev *qdev = dev->data->dev_private;
+ struct ecore_dev *edev = &qdev->edev;
+ struct ecore_eth_stats stats;
+ unsigned int num = RTE_DIM(qede_xstats_strings);
+
+ if (n < num)
+ return num;
+
+ qdev->ops->get_vport_stats(edev, &stats);
+
+ for (num = 0; num < n; num++)
+ xstats[num].value = *(u64 *)(((char *)&stats) +
+ qede_xstats_strings[num].offset);
+
+ return num;
+}
+
+static void
+qede_reset_xstats(struct rte_eth_dev *dev)
+{
+ struct qede_dev *qdev = dev->data->dev_private;
+ struct ecore_dev *edev = &qdev->edev;
+
+ ecore_reset_vport_stats(edev);
}
int qede_dev_set_link_state(struct rte_eth_dev *eth_dev, bool link_up)
@@ -976,6 +1158,9 @@ static const struct eth_dev_ops qede_eth_dev_ops = {
.dev_close = qede_dev_close,
.stats_get = qede_get_stats,
.stats_reset = qede_reset_stats,
+ .xstats_get = qede_get_xstats,
+ .xstats_reset = qede_reset_xstats,
+ .xstats_get_names = qede_get_xstats_names,
.mac_addr_add = qede_mac_addr_add,
.mac_addr_remove = qede_mac_addr_remove,
.mac_addr_set = qede_mac_addr_set,
@@ -1010,6 +1195,9 @@ static const struct eth_dev_ops qede_eth_vf_dev_ops = {
.dev_close = qede_dev_close,
.stats_get = qede_get_stats,
.stats_reset = qede_reset_stats,
+ .xstats_get = qede_get_xstats,
+ .xstats_reset = qede_reset_xstats,
+ .xstats_get_names = qede_get_xstats_names,
.vlan_offload_set = qede_vlan_offload_set,
.vlan_filter_set = qede_vlan_filter_set,
.dev_supported_ptypes_get = qede_dev_supported_ptypes_get,
@@ -1340,5 +1528,7 @@ static struct rte_driver rte_qede_driver = {
.init = rte_qedevf_pmd_init
};
-PMD_REGISTER_DRIVER(rte_qede_driver);
-PMD_REGISTER_DRIVER(rte_qedevf_driver);
+PMD_REGISTER_DRIVER(rte_qede_driver, qede);
+DRIVER_REGISTER_PCI_TABLE(qede, pci_id_qede_map);
+PMD_REGISTER_DRIVER(rte_qedevf_driver, qedevf);
+DRIVER_REGISTER_PCI_TABLE(qedevf, pci_id_qedevf_map);
diff --git a/drivers/net/ring/rte_eth_ring.c b/drivers/net/ring/rte_eth_ring.c
index b1783c3e..a7048c77 100644
--- a/drivers/net/ring/rte_eth_ring.c
+++ b/drivers/net/ring/rte_eth_ring.c
@@ -624,10 +624,11 @@ rte_pmd_ring_devuninit(const char *name)
}
static struct rte_driver pmd_ring_drv = {
- .name = "eth_ring",
.type = PMD_VDEV,
.init = rte_pmd_ring_devinit,
.uninit = rte_pmd_ring_devuninit,
};
-PMD_REGISTER_DRIVER(pmd_ring_drv);
+PMD_REGISTER_DRIVER(pmd_ring_drv, eth_ring);
+DRIVER_REGISTER_PARAM_STRING(eth_ring,
+ "nodeaction=[attach|detach]");
diff --git a/drivers/net/szedata2/rte_eth_szedata2.c b/drivers/net/szedata2/rte_eth_szedata2.c
index 985a8d60..483d7894 100644
--- a/drivers/net/szedata2/rte_eth_szedata2.c
+++ b/drivers/net/szedata2/rte_eth_szedata2.c
@@ -62,7 +62,7 @@
*/
#define RTE_SZE2_PACKET_HEADER_SIZE_ALIGNED 8
-#define RTE_SZEDATA2_DRIVER_NAME "rte_szedata2_pmd"
+#define RTE_SZEDATA2_DRIVER_NAME rte_szedata2_pmd
#define RTE_SZEDATA2_PCI_DRIVER_NAME "rte_szedata2_pmd"
#define SZEDATA2_DEV_PATH_FMT "/dev/szedataII%u"
@@ -1596,9 +1596,9 @@ rte_szedata2_uninit(const char *name __rte_unused)
static struct rte_driver rte_szedata2_driver = {
.type = PMD_PDEV,
- .name = RTE_SZEDATA2_DRIVER_NAME,
.init = rte_szedata2_init,
.uninit = rte_szedata2_uninit,
};
-PMD_REGISTER_DRIVER(rte_szedata2_driver);
+PMD_REGISTER_DRIVER(rte_szedata2_driver, RTE_SZEDATA2_DRIVER_NAME);
+DRIVER_REGISTER_PCI_TABLE(RTE_SZEDATA2_DRIVER_NAME, rte_szedata2_pci_id_table);
diff --git a/drivers/net/thunderx/base/nicvf_hw_defs.h b/drivers/net/thunderx/base/nicvf_hw_defs.h
index 88ecd175..2f2b2259 100644
--- a/drivers/net/thunderx/base/nicvf_hw_defs.h
+++ b/drivers/net/thunderx/base/nicvf_hw_defs.h
@@ -164,6 +164,7 @@
#define RBDR_QUEUE_SZ_128K (128 * 1024)
#define RBDR_QUEUE_SZ_256K (256 * 1024)
#define RBDR_QUEUE_SZ_512K (512 * 1024)
+#define RBDR_QUEUE_SZ_MAX RBDR_QUEUE_SZ_512K
#define RBDR_SIZE_SHIFT (13) /* 8k */
@@ -174,6 +175,7 @@
#define SND_QUEUE_SZ_16K (16 * 1024)
#define SND_QUEUE_SZ_32K (32 * 1024)
#define SND_QUEUE_SZ_64K (64 * 1024)
+#define SND_QUEUE_SZ_MAX SND_QUEUE_SZ_64K
#define SND_QSIZE_SHIFT (10) /* 1k */
@@ -184,6 +186,7 @@
#define CMP_QUEUE_SZ_16K (16 * 1024)
#define CMP_QUEUE_SZ_32K (32 * 1024)
#define CMP_QUEUE_SZ_64K (64 * 1024)
+#define CMP_QUEUE_SZ_MAX CMP_QUEUE_SZ_64K
#define CMP_QSIZE_SHIFT (10) /* 1k */
diff --git a/drivers/net/thunderx/nicvf_ethdev.c b/drivers/net/thunderx/nicvf_ethdev.c
index 48ed3812..4f875c02 100644
--- a/drivers/net/thunderx/nicvf_ethdev.c
+++ b/drivers/net/thunderx/nicvf_ethdev.c
@@ -189,19 +189,16 @@ nicvf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
}
static int
-nicvf_dev_get_reg_length(struct rte_eth_dev *dev __rte_unused)
-{
- return nicvf_reg_get_count();
-}
-
-static int
nicvf_dev_get_regs(struct rte_eth_dev *dev, struct rte_dev_reg_info *regs)
{
uint64_t *data = regs->data;
struct nicvf *nic = nicvf_pmd_priv(dev);
- if (data == NULL)
- return -EINVAL;
+ if (data == NULL) {
+ regs->length = nicvf_reg_get_count();
+ regs->width = THUNDERX_REG_BYTES;
+ return 0;
+ }
/* Support only full register dump */
if ((regs->length == 0) ||
@@ -495,7 +492,7 @@ nicvf_qset_cq_alloc(struct nicvf *nic, struct nicvf_rxq *rxq, uint16_t qidx,
uint32_t desc_cnt)
{
const struct rte_memzone *rz;
- uint32_t ring_size = desc_cnt * sizeof(union cq_entry_t);
+ uint32_t ring_size = CMP_QUEUE_SZ_MAX * sizeof(union cq_entry_t);
rz = rte_eth_dma_zone_reserve(nic->eth_dev, "cq_ring", qidx, ring_size,
NICVF_CQ_BASE_ALIGN_BYTES, nic->node);
@@ -518,7 +515,7 @@ nicvf_qset_sq_alloc(struct nicvf *nic, struct nicvf_txq *sq, uint16_t qidx,
uint32_t desc_cnt)
{
const struct rte_memzone *rz;
- uint32_t ring_size = desc_cnt * sizeof(union sq_entry_t);
+ uint32_t ring_size = SND_QUEUE_SZ_MAX * sizeof(union sq_entry_t);
rz = rte_eth_dma_zone_reserve(nic->eth_dev, "sq", qidx, ring_size,
NICVF_SQ_BASE_ALIGN_BYTES, nic->node);
@@ -551,7 +548,7 @@ nicvf_qset_rbdr_alloc(struct nicvf *nic, uint32_t desc_cnt, uint32_t buffsz)
return -ENOMEM;
}
- ring_size = sizeof(struct rbdr_entry_t) * desc_cnt;
+ ring_size = sizeof(struct rbdr_entry_t) * RBDR_QUEUE_SZ_MAX;
rz = rte_eth_dma_zone_reserve(nic->eth_dev, "rbdr", 0, ring_size,
NICVF_RBDR_BASE_ALIGN_BYTES, nic->node);
if (rz == NULL) {
@@ -1623,7 +1620,6 @@ static const struct eth_dev_ops nicvf_eth_dev_ops = {
.rx_queue_count = nicvf_dev_rx_queue_count,
.tx_queue_setup = nicvf_dev_tx_queue_setup,
.tx_queue_release = nicvf_dev_tx_queue_release,
- .get_reg_length = nicvf_dev_get_reg_length,
.get_reg = nicvf_dev_get_regs,
};
@@ -1783,9 +1779,9 @@ rte_nicvf_pmd_init(const char *name __rte_unused, const char *para __rte_unused)
}
static struct rte_driver rte_nicvf_driver = {
- .name = "nicvf_driver",
.type = PMD_PDEV,
.init = rte_nicvf_pmd_init,
};
-PMD_REGISTER_DRIVER(rte_nicvf_driver);
+PMD_REGISTER_DRIVER(rte_nicvf_driver, thunderx_nicvf);
+DRIVER_REGISTER_PCI_TABLE(thunderx_nicvf, pci_id_nicvf_map);
diff --git a/drivers/net/thunderx/nicvf_ethdev.h b/drivers/net/thunderx/nicvf_ethdev.h
index 59fa19cf..34447e05 100644
--- a/drivers/net/thunderx/nicvf_ethdev.h
+++ b/drivers/net/thunderx/nicvf_ethdev.h
@@ -36,6 +36,7 @@
#include <rte_ethdev.h>
#define THUNDERX_NICVF_PMD_VERSION "1.0"
+#define THUNDERX_REG_BYTES 8
#define NICVF_INTR_POLL_INTERVAL_MS 50
#define NICVF_HALF_DUPLEX 0x00
diff --git a/drivers/net/vhost/rte_eth_vhost.c b/drivers/net/vhost/rte_eth_vhost.c
index 3b509465..7539cd49 100644
--- a/drivers/net/vhost/rte_eth_vhost.c
+++ b/drivers/net/vhost/rte_eth_vhost.c
@@ -303,6 +303,7 @@ destroy_device(int vid)
struct internal_list *list;
char ifname[PATH_MAX];
unsigned i;
+ struct rte_vhost_vring_state *state;
rte_vhost_get_ifname(vid, ifname, sizeof(ifname));
list = find_internal_resource(ifname);
@@ -345,6 +346,15 @@ destroy_device(int vid)
vq->vid = -1;
}
+ state = vring_states[eth_dev->data->port_id];
+ rte_spinlock_lock(&state->lock);
+ for (i = 0; i <= state->max_vring; i++) {
+ state->cur[i] = false;
+ state->seen[i] = false;
+ }
+ state->max_vring = 0;
+ rte_spinlock_unlock(&state->lock);
+
RTE_LOG(INFO, PMD, "Connection closed\n");
_rte_eth_dev_callback_process(eth_dev, RTE_ETH_EVENT_INTR_LSC);
@@ -915,10 +925,12 @@ rte_pmd_vhost_devuninit(const char *name)
}
static struct rte_driver pmd_vhost_drv = {
- .name = "eth_vhost",
.type = PMD_VDEV,
.init = rte_pmd_vhost_devinit,
.uninit = rte_pmd_vhost_devuninit,
};
-PMD_REGISTER_DRIVER(pmd_vhost_drv);
+PMD_REGISTER_DRIVER(pmd_vhost_drv, eth_vhost);
+DRIVER_REGISTER_PARAM_STRING(eth_vhost,
+ "iface=<ifc> "
+ "queues=<int>");
diff --git a/drivers/net/virtio/virtio_ethdev.c b/drivers/net/virtio/virtio_ethdev.c
index 480daa37..850e3ba5 100644
--- a/drivers/net/virtio/virtio_ethdev.c
+++ b/drivers/net/virtio/virtio_ethdev.c
@@ -103,11 +103,8 @@ static int virtio_dev_queue_stats_mapping_set(
* The set of PCI devices this driver supports
*/
static const struct rte_pci_id pci_id_virtio_map[] = {
-
-#define RTE_PCI_DEV_ID_DECL_VIRTIO(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
-#include "rte_pci_dev_ids.h"
-
-{ .vendor_id = 0, /* sentinel */ },
+ { RTE_PCI_DEVICE(VIRTIO_PCI_VENDORID, VIRTIO_PCI_DEVICEID_MIN) },
+ { .vendor_id = 0, /* sentinel */ },
};
struct rte_virtio_xstats_name_off {
@@ -166,7 +163,7 @@ virtio_send_command(struct virtnet_ctl *cvq, struct virtio_pmd_ctrl *ctrl,
ctrl->status = status;
- if (!cvq && !cvq->vq) {
+ if (!cvq || !cvq->vq) {
PMD_INIT_LOG(ERR, "Control queue is not supported.");
return -1;
}
@@ -1571,4 +1568,5 @@ static struct rte_driver rte_virtio_driver = {
.init = rte_virtio_pmd_init,
};
-PMD_REGISTER_DRIVER(rte_virtio_driver);
+PMD_REGISTER_DRIVER(rte_virtio_driver, virtio_net);
+DRIVER_REGISTER_PCI_TABLE(virtio_net, pci_id_virtio_map);
diff --git a/drivers/net/virtio/virtio_rxtx_simple.c b/drivers/net/virtio/virtio_rxtx_simple.c
index 242ad90d..d8fcc15e 100644
--- a/drivers/net/virtio/virtio_rxtx_simple.c
+++ b/drivers/net/virtio/virtio_rxtx_simple.c
@@ -301,7 +301,7 @@ static inline void
virtio_xmit_cleanup(struct virtqueue *vq)
{
uint16_t i, desc_idx;
- int nb_free = 0;
+ uint32_t nb_free = 0;
struct rte_mbuf *m, *free[VIRTIO_TX_MAX_FREE_BUF_SZ];
desc_idx = (uint16_t)(vq->vq_used_cons_idx &
@@ -319,13 +319,16 @@ virtio_xmit_cleanup(struct virtqueue *vq)
free[nb_free++] = m;
else {
rte_mempool_put_bulk(free[0]->pool,
- (void **)free, nb_free);
+ (void **)free,
+ RTE_MIN(RTE_DIM(free),
+ nb_free));
free[0] = m;
nb_free = 1;
}
}
}
- rte_mempool_put_bulk(free[0]->pool, (void **)free, nb_free);
+ rte_mempool_put_bulk(free[0]->pool, (void **)free,
+ RTE_MIN(RTE_DIM(free), nb_free));
} else {
for (i = 1; i < VIRTIO_TX_FREE_NR; i++) {
m = (struct rte_mbuf *)vq->vq_descx[desc_idx++].cookie;
diff --git a/drivers/net/virtio/virtio_user/vhost_user.c b/drivers/net/virtio/virtio_user/vhost_user.c
index a2b0687f..082e8217 100644
--- a/drivers/net/virtio/virtio_user/vhost_user.c
+++ b/drivers/net/virtio/virtio_user/vhost_user.c
@@ -181,7 +181,7 @@ get_hugepage_file_info(struct hugepage_file_info huges[], int max)
}
huges[idx].addr = v_start;
huges[idx].size = v_end - v_start;
- strcpy(huges[idx].path, tmp);
+ snprintf(huges[idx].path, PATH_MAX, "%s", tmp);
idx++;
}
@@ -392,7 +392,8 @@ vhost_user_setup(const char *path)
}
flag = fcntl(fd, F_GETFD);
- fcntl(fd, F_SETFD, flag | FD_CLOEXEC);
+ if (fcntl(fd, F_SETFD, flag | FD_CLOEXEC) < 0)
+ PMD_DRV_LOG(WARNING, "fcntl failed, %s", strerror(errno));
memset(&un, 0, sizeof(un));
un.sun_family = AF_UNIX;
diff --git a/drivers/net/virtio/virtio_user/virtio_user_dev.c b/drivers/net/virtio/virtio_user/virtio_user_dev.c
index 3d12a320..376c9cf5 100644
--- a/drivers/net/virtio/virtio_user/virtio_user_dev.c
+++ b/drivers/net/virtio/virtio_user/virtio_user_dev.c
@@ -63,12 +63,12 @@ virtio_user_kick_queue(struct virtio_user_dev *dev, uint32_t queue_sel)
/* May use invalid flag, but some backend leverages kickfd and callfd as
* criteria to judge if dev is alive. so finally we use real event_fd.
*/
- callfd = eventfd(0, O_CLOEXEC | O_NONBLOCK);
+ callfd = eventfd(0, EFD_CLOEXEC | EFD_NONBLOCK);
if (callfd < 0) {
PMD_DRV_LOG(ERR, "callfd error, %s\n", strerror(errno));
return -1;
}
- kickfd = eventfd(0, O_CLOEXEC | O_NONBLOCK);
+ kickfd = eventfd(0, EFD_CLOEXEC | EFD_NONBLOCK);
if (kickfd < 0) {
close(callfd);
PMD_DRV_LOG(ERR, "kickfd error, %s\n", strerror(errno));
@@ -181,7 +181,7 @@ int
virtio_user_dev_init(struct virtio_user_dev *dev, char *path, int queues,
int cq, int queue_size, const char *mac)
{
- strncpy(dev->path, path, PATH_MAX);
+ snprintf(dev->path, PATH_MAX, "%s", path);
dev->max_queue_pairs = queues;
dev->queue_pairs = 1; /* mq disabled by default */
dev->queue_size = queue_size;
diff --git a/drivers/net/virtio/virtio_user_ethdev.c b/drivers/net/virtio/virtio_user_ethdev.c
index 5ab24711..782d7d38 100644
--- a/drivers/net/virtio/virtio_user_ethdev.c
+++ b/drivers/net/virtio/virtio_user_ethdev.c
@@ -320,7 +320,7 @@ virtio_user_eth_dev_alloc(const char *name)
static int
virtio_user_pmd_devinit(const char *name, const char *params)
{
- struct rte_kvargs *kvlist;
+ struct rte_kvargs *kvlist = NULL;
struct rte_eth_dev *eth_dev;
struct virtio_hw *hw;
uint64_t queues = VIRTIO_USER_DEF_Q_NUM;
@@ -343,31 +343,60 @@ virtio_user_pmd_devinit(const char *name, const char *params)
}
if (rte_kvargs_count(kvlist, VIRTIO_USER_ARG_PATH) == 1)
- rte_kvargs_process(kvlist, VIRTIO_USER_ARG_PATH,
- &get_string_arg, &path);
+ ret = rte_kvargs_process(kvlist, VIRTIO_USER_ARG_PATH,
+ &get_string_arg, &path);
+ if (ret < 0) {
+ PMD_INIT_LOG(ERR, "error to parse %s",
+ VIRTIO_USER_ARG_PATH);
+ goto end;
+ }
else {
PMD_INIT_LOG(ERR, "arg %s is mandatory for virtio-user\n",
VIRTIO_USER_ARG_QUEUE_SIZE);
goto end;
}
- if (rte_kvargs_count(kvlist, VIRTIO_USER_ARG_MAC) == 1)
- rte_kvargs_process(kvlist, VIRTIO_USER_ARG_MAC,
- &get_string_arg, &mac_addr);
+ if (rte_kvargs_count(kvlist, VIRTIO_USER_ARG_MAC) == 1) {
+ ret = rte_kvargs_process(kvlist, VIRTIO_USER_ARG_MAC,
+ &get_string_arg, &mac_addr);
+ if (ret < 0) {
+ PMD_INIT_LOG(ERR, "error to parse %s",
+ VIRTIO_USER_ARG_MAC);
+ goto end;
+ }
+ }
- if (rte_kvargs_count(kvlist, VIRTIO_USER_ARG_QUEUE_SIZE) == 1)
- rte_kvargs_process(kvlist, VIRTIO_USER_ARG_QUEUE_SIZE,
- &get_integer_arg, &queue_size);
+ if (rte_kvargs_count(kvlist, VIRTIO_USER_ARG_QUEUE_SIZE) == 1) {
+ ret = rte_kvargs_process(kvlist, VIRTIO_USER_ARG_QUEUE_SIZE,
+ &get_integer_arg, &queue_size);
+ if (ret < 0) {
+ PMD_INIT_LOG(ERR, "error to parse %s",
+ VIRTIO_USER_ARG_QUEUE_SIZE);
+ goto end;
+ }
+ }
- if (rte_kvargs_count(kvlist, VIRTIO_USER_ARG_QUEUES_NUM) == 1)
- rte_kvargs_process(kvlist, VIRTIO_USER_ARG_QUEUES_NUM,
- &get_integer_arg, &queues);
+ if (rte_kvargs_count(kvlist, VIRTIO_USER_ARG_QUEUES_NUM) == 1) {
+ ret = rte_kvargs_process(kvlist, VIRTIO_USER_ARG_QUEUES_NUM,
+ &get_integer_arg, &queues);
+ if (ret < 0) {
+ PMD_INIT_LOG(ERR, "error to parse %s",
+ VIRTIO_USER_ARG_QUEUES_NUM);
+ goto end;
+ }
+ }
- if (rte_kvargs_count(kvlist, VIRTIO_USER_ARG_CQ_NUM) == 1)
- rte_kvargs_process(kvlist, VIRTIO_USER_ARG_CQ_NUM,
- &get_integer_arg, &cq);
- else if (queues > 1)
+ if (rte_kvargs_count(kvlist, VIRTIO_USER_ARG_CQ_NUM) == 1) {
+ ret = rte_kvargs_process(kvlist, VIRTIO_USER_ARG_CQ_NUM,
+ &get_integer_arg, &cq);
+ if (ret < 0) {
+ PMD_INIT_LOG(ERR, "error to parse %s",
+ VIRTIO_USER_ARG_CQ_NUM);
+ goto end;
+ }
+ } else if (queues > 1) {
cq = 1;
+ }
if (queues > 1 && cq == 0) {
PMD_INIT_LOG(ERR, "multi-q requires ctrl-q");
@@ -393,6 +422,8 @@ virtio_user_pmd_devinit(const char *name, const char *params)
ret = 0;
end:
+ if (kvlist)
+ rte_kvargs_free(kvlist);
if (path)
free(path);
if (mac_addr)
@@ -431,10 +462,15 @@ virtio_user_pmd_devuninit(const char *name)
}
static struct rte_driver virtio_user_driver = {
- .name = "virtio-user",
.type = PMD_VDEV,
.init = virtio_user_pmd_devinit,
.uninit = virtio_user_pmd_devuninit,
};
-PMD_REGISTER_DRIVER(virtio_user_driver);
+PMD_REGISTER_DRIVER(virtio_user_driver, virtio_user);
+DRIVER_REGISTER_PARAM_STRING(virtio_user,
+ "path=<path> "
+ "mac=<mac addr> "
+ "cq=<int> "
+ "queue_size=<int> "
+ "queues=<int>");
diff --git a/drivers/net/vmxnet3/vmxnet3_ethdev.c b/drivers/net/vmxnet3/vmxnet3_ethdev.c
index 29b469cc..58742153 100644
--- a/drivers/net/vmxnet3/vmxnet3_ethdev.c
+++ b/drivers/net/vmxnet3/vmxnet3_ethdev.c
@@ -100,12 +100,11 @@ static void vmxnet3_process_events(struct vmxnet3_hw *);
/*
* The set of PCI devices this driver supports
*/
+#define VMWARE_PCI_VENDOR_ID 0x15AD
+#define VMWARE_DEV_ID_VMXNET3 0x07B0
static const struct rte_pci_id pci_id_vmxnet3_map[] = {
-
-#define RTE_PCI_DEV_ID_DECL_VMXNET3(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
-#include "rte_pci_dev_ids.h"
-
-{ .vendor_id = 0, /* sentinel */ },
+ { RTE_PCI_DEVICE(VMWARE_PCI_VENDOR_ID, VMWARE_DEV_ID_VMXNET3) },
+ { .vendor_id = 0, /* sentinel */ },
};
static const struct eth_dev_ops vmxnet3_eth_dev_ops = {
@@ -954,4 +953,5 @@ static struct rte_driver rte_vmxnet3_driver = {
.init = rte_vmxnet3_pmd_init,
};
-PMD_REGISTER_DRIVER(rte_vmxnet3_driver);
+PMD_REGISTER_DRIVER(rte_vmxnet3_driver, vmxnet3);
+DRIVER_REGISTER_PCI_TABLE(vmxnet3, pci_id_vmxnet3_map);
diff --git a/drivers/net/xenvirt/rte_eth_xenvirt.c b/drivers/net/xenvirt/rte_eth_xenvirt.c
index 3e45808f..99f6cc81 100644
--- a/drivers/net/xenvirt/rte_eth_xenvirt.c
+++ b/drivers/net/xenvirt/rte_eth_xenvirt.c
@@ -760,10 +760,11 @@ rte_pmd_xenvirt_devuninit(const char *name)
}
static struct rte_driver pmd_xenvirt_drv = {
- .name = "eth_xenvirt",
.type = PMD_VDEV,
.init = rte_pmd_xenvirt_devinit,
.uninit = rte_pmd_xenvirt_devuninit,
};
-PMD_REGISTER_DRIVER(pmd_xenvirt_drv);
+PMD_REGISTER_DRIVER(pmd_xenvirt_drv, eth_xenvirt);
+DRIVER_REGISTER_PARAM_STRING(eth_xenvirt,
+ "mac=<mac addr>");