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+; BSD LICENSE
+;
+; Copyright(c) 2015 Intel Corporation. All rights reserved.
+; All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions
+; are met:
+;
+; * Redistributions of source code must retain the above copyright
+; notice, this list of conditions and the following disclaimer.
+; * Redistributions in binary form must reproduce the above copyright
+; notice, this list of conditions and the following disclaimer in
+; the documentation and/or other materials provided with the
+; distribution.
+; * Neither the name of Intel Corporation nor the names of its
+; contributors may be used to endorse or promote products derived
+; from this software without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+; A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+; OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+; SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+; LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+; DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+; THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+
+; An edge router typically sits between two networks such as the provider
+; core network and the provider access network. A typical packet processing
+; pipeline for the downstream traffic (i.e. traffic from core to access
+; network) contains the following functional blocks: Packet RX & Routing,
+; Traffic management and Packet TX. The input packets are assumed to be
+; IPv4, while the output packets are Q-in-Q IPv4.
+
+; A simple implementation for this functional pipeline is presented below.
+
+; Packet Rx & Traffic Management Packet Tx
+; Routing (Pass-Through) (Pass-Through)
+; _____________________ SWQ0 ______________________ SWQ4 _____________________
+; RXQ0.0 --->| |----->| |----->| |---> TXQ0.0
+; | | SWQ1 | | SWQ5 | |
+; RXQ1.0 --->| |----->| |----->| |---> TXQ1.0
+; | (P1) | SWQ2 | (P2) | SWQ6 | (P3) |
+; RXQ2.0 --->| |----->| |----->| |---> TXQ2.0
+; | | SWQ3 | | SWQ7 | |
+; RXQ3.0 --->| |----->| |----->| |---> TXQ3.0
+; |_____________________| |______________________| |_____________________|
+; | _|_ ^ _|_ ^ _|_ ^ _|_ ^
+; | |___|||___|||___|||___||
+; +--> SINK0 |___|||___|||___|||___||
+; (route miss) |__| |__| |__| |__|
+; TM0 TM1 TM2 TM3
+
+[PIPELINE0]
+type = MASTER
+core = 0
+
+[PIPELINE1]
+type = ROUTING
+core = 1
+pktq_in = RXQ0.0 RXQ1.0 RXQ2.0 RXQ3.0
+pktq_out = SWQ0 SWQ1 SWQ2 SWQ3 SINK0
+encap = ethernet_qinq
+qinq_sched = test
+ip_hdr_offset = 270; mbuf (128) + headroom (128) + ethernet header (14) = 270
+
+[PIPELINE2]
+type = PASS-THROUGH
+core = 2
+pktq_in = SWQ0 SWQ1 SWQ2 SWQ3 TM0 TM1 TM2 TM3
+pktq_out = TM0 TM1 TM2 TM3 SWQ4 SWQ5 SWQ6 SWQ7
+
+[PIPELINE3]
+type = PASS-THROUGH
+core = 3
+pktq_in = SWQ4 SWQ5 SWQ6 SWQ7
+pktq_out = TXQ0.0 TXQ1.0 TXQ2.0 TXQ3.0
+
+[MEMPOOL0]
+pool_size = 2M