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/*
 * Copyright (c) 2016 QLogic Corporation.
 * All rights reserved.
 * www.qlogic.com
 *
 * See LICENSE.qede_pmd for copyright and licensing details.
 */

#ifndef __ECORE_MCP_H__
#define __ECORE_MCP_H__

#include "bcm_osal.h"
#include "mcp_public.h"
#include "ecore_mcp_api.h"

/* Using hwfn number (and not pf_num) is required since in CMT mode,
 * same pf_num may be used by two different hwfn
 * TODO - this shouldn't really be in .h file, but until all fields
 * required during hw-init will be placed in their correct place in shmem
 * we need it in ecore_dev.c [for readin the nvram reflection in shmem].
 */
#define MCP_PF_ID_BY_REL(p_hwfn, rel_pfid) (ECORE_IS_BB((p_hwfn)->p_dev) ? \
					    ((rel_pfid) | \
					     ((p_hwfn)->abs_pf_id & 1) << 3) : \
					     rel_pfid)
#define MCP_PF_ID(p_hwfn) MCP_PF_ID_BY_REL(p_hwfn, (p_hwfn)->rel_pf_id)

#define MFW_PORT(_p_hwfn)	((_p_hwfn)->abs_pf_id % \
				 ((_p_hwfn)->p_dev->num_ports_in_engines * \
				  ecore_device_num_engines((_p_hwfn)->p_dev)))

struct ecore_mcp_info {
	/* Spinlock used for protecting the access to the MFW mailbox */
	osal_spinlock_t lock;
	/* Flag to indicate whether sending a MFW mailbox is forbidden */
	bool block_mb_sending;

	/* Address of the MCP public area */
	u32 public_base;
	/* Address of the driver mailbox */
	u32 drv_mb_addr;
	/* Address of the MFW mailbox */
	u32 mfw_mb_addr;
	/* Address of the port configuration (link) */
	u32 port_addr;

	/* Current driver mailbox sequence */
	u16 drv_mb_seq;
	/* Current driver pulse sequence */
	u16 drv_pulse_seq;

	struct ecore_mcp_link_params       link_input;
	struct ecore_mcp_link_state	   link_output;
	struct ecore_mcp_link_capabilities link_capabilities;

	struct ecore_mcp_function_info	   func_info;

	u8 *mfw_mb_cur;
	u8 *mfw_mb_shadow;
	u16 mfw_mb_length;
	u16 mcp_hist;
};

struct ecore_mcp_mb_params {
	u32 cmd;
	u32 param;
	union drv_union_data *p_data_src;
	union drv_union_data *p_data_dst;
	u32 mcp_resp;
	u32 mcp_param;
};

/**
 * @brief Initialize the interface with the MCP
 *
 * @param p_hwfn - HW func
 * @param p_ptt - PTT required for register access
 *
 * @return enum _ecore_status_t
 */
enum _ecore_status_t ecore_mcp_cmd_init(struct ecore_hwfn *p_hwfn,
					struct ecore_ptt *p_ptt);

/**
 * @brief Initialize the port interface with the MCP
 *
 * @param p_hwfn
 * @param p_ptt
 * Can only be called after `num_ports_in_engines' is set
 */
void ecore_mcp_cmd_port_init(struct ecore_hwfn *p_hwfn,
			     struct ecore_ptt *p_ptt);
/**
 * @brief Releases resources allocated during the init process.
 *
 * @param p_hwfn - HW func
 * @param p_ptt - PTT required for register access
 *
 * @return enum _ecore_status_t
 */

enum _ecore_status_t ecore_mcp_free(struct ecore_hwfn *p_hwfn);

/**
 * @brief This function is called from the DPC context. After
 * pointing PTT to the mfw mb, check for events sent by the MCP
 * to the driver and ack them. In case a critical event
 * detected, it will be handled here, otherwise the work will be
 * queued to a sleepable work-queue.
 *
 * @param p_hwfn - HW function
 * @param p_ptt - PTT required for register access
 * @return enum _ecore_status_t - ECORE_SUCCESS - operation
 * was successul.
 */
enum _ecore_status_t ecore_mcp_handle_events(struct ecore_hwfn *p_hwfn,
					     struct ecore_ptt *p_ptt);

/**
 * @brief When MFW doesn't get driver pulse for couple of seconds, at some
 * threshold before timeout expires, it will generate interrupt
 * through a dedicated status block (DPSB - Driver Pulse Status
 * Block), which the driver should respond immediately, by
 * providing keepalive indication after setting the PTT to the
 * driver-MFW mailbox. This function is called directly from the
 * DPC upon receiving the DPSB attention.
 *
 * @param p_hwfn - hw function
 * @param p_ptt - PTT required for register access
 * @return enum _ecore_status_t - ECORE_SUCCESS - operation
 * was successul.
 */
enum _ecore_status_t ecore_issue_pulse(struct ecore_hwfn *p_hwfn,
				       struct ecore_ptt *p_ptt);

/**
 * @brief Sends a LOAD_REQ to the MFW, and in case operation
 *        succeed, returns whether this PF is the first on the
 *        chip/engine/port or function. This function should be
 *        called when driver is ready to accept MFW events after
 *        Storms initializations are done.
 *
 * @param p_hwfn       - hw function
 * @param p_ptt        - PTT required for register access
 * @param p_load_code  - The MCP response param containing one
 *      of the following:
 *      FW_MSG_CODE_DRV_LOAD_ENGINE
 *      FW_MSG_CODE_DRV_LOAD_PORT
 *      FW_MSG_CODE_DRV_LOAD_FUNCTION
 * @return enum _ecore_status_t -
 *      ECORE_SUCCESS - Operation was successul.
 *      ECORE_BUSY - Operation failed
 */
enum _ecore_status_t ecore_mcp_load_req(struct ecore_hwfn *p_hwfn,
					struct ecore_ptt *p_ptt,
					u32 *p_load_code);

/**
 * @brief Read the MFW mailbox into Current buffer.
 *
 * @param p_hwfn
 * @param p_ptt
 */
void ecore_mcp_read_mb(struct ecore_hwfn *p_hwfn,
		       struct ecore_ptt *p_ptt);

/**
 * @brief Ack to mfw that driver finished FLR process for VFs
 *
 * @param p_hwfn
 * @param p_ptt
 * @param vfs_to_ack - bit mask of all engine VFs for which the PF acks.
 *
 * @param return enum _ecore_status_t - ECORE_SUCCESS upon success.
 */
enum _ecore_status_t ecore_mcp_ack_vf_flr(struct ecore_hwfn *p_hwfn,
					  struct ecore_ptt *p_ptt,
					  u32 *vfs_to_ack);

/**
 * @brief - calls during init to read shmem of all function-related info.
 *
 * @param p_hwfn
 *
 * @param return ECORE_SUCCESS upon success.
 */
enum _ecore_status_t ecore_mcp_fill_shmem_func_info(struct ecore_hwfn *p_hwfn,
						    struct ecore_ptt *p_ptt);

/**
 * @brief - Reset the MCP using mailbox command.
 *
 * @param p_hwfn
 * @param p_ptt
 *
 * @param return ECORE_SUCCESS upon success.
 */
enum _ecore_status_t ecore_mcp_reset(struct ecore_hwfn *p_hwfn,
				     struct ecore_ptt *p_ptt);

/**
 * @brief - Sends an NVM write command request to the MFW with
 *          payload.
 *
 * @param p_hwfn
 * @param p_ptt
 * @param cmd - Command: Either DRV_MSG_CODE_NVM_WRITE_NVRAM or
 *            DRV_MSG_CODE_NVM_PUT_FILE_DATA
 * @param param - [0:23] - Offset [24:31] - Size
 * @param o_mcp_resp - MCP response
 * @param o_mcp_param - MCP response param
 * @param i_txn_size -  Buffer size
 * @param i_buf - Pointer to the buffer
 *
 * @param return ECORE_SUCCESS upon success.
 */
enum _ecore_status_t ecore_mcp_nvm_wr_cmd(struct ecore_hwfn *p_hwfn,
					  struct ecore_ptt *p_ptt,
					  u32 cmd,
					  u32 param,
					  u32 *o_mcp_resp,
					  u32 *o_mcp_param,
					  u32 i_txn_size,
					  u32 *i_buf);

/**
 * @brief - Sends an NVM read command request to the MFW to get
 *        a buffer.
 *
 * @param p_hwfn
 * @param p_ptt
 * @param cmd - Command: DRV_MSG_CODE_NVM_GET_FILE_DATA or
 *            DRV_MSG_CODE_NVM_READ_NVRAM commands
 * @param param - [0:23] - Offset [24:31] - Size
 * @param o_mcp_resp - MCP response
 * @param o_mcp_param - MCP response param
 * @param o_txn_size -  Buffer size output
 * @param o_buf - Pointer to the buffer returned by the MFW.
 *
 * @param return ECORE_SUCCESS upon success.
 */
enum _ecore_status_t ecore_mcp_nvm_rd_cmd(struct ecore_hwfn *p_hwfn,
					  struct ecore_ptt *p_ptt,
					  u32 cmd,
					  u32 param,
					  u32 *o_mcp_resp,
					  u32 *o_mcp_param,
					  u32 *o_txn_size,
					  u32 *o_buf);

/**
 * @brief indicates whether the MFW objects [under mcp_info] are accessible
 *
 * @param p_hwfn
 *
 * @return true iff MFW is running and mcp_info is initialized
 */
bool ecore_mcp_is_init(struct ecore_hwfn *p_hwfn);

/**
 * @brief request MFW to configure MSI-X for a VF
 *
 * @param p_hwfn
 * @param p_ptt
 * @param vf_id - absolute inside engine
 * @param num_sbs - number of entries to request
 *
 * @return enum _ecore_status_t
 */
enum _ecore_status_t ecore_mcp_config_vf_msix(struct ecore_hwfn *p_hwfn,
					      struct ecore_ptt *p_ptt,
					      u8 vf_id, u8 num);

/**
 * @brief - Halt the MCP.
 *
 * @param p_hwfn
 * @param p_ptt
 *
 * @param return ECORE_SUCCESS upon success.
 */
enum _ecore_status_t ecore_mcp_halt(struct ecore_hwfn *p_hwfn,
				    struct ecore_ptt *p_ptt);

/**
 * @brief - Wake up the MCP.
 *
 * @param p_hwfn
 * @param p_ptt
 *
 * @param return ECORE_SUCCESS upon success.
 */
enum _ecore_status_t ecore_mcp_resume(struct ecore_hwfn *p_hwfn,
				      struct ecore_ptt *p_ptt);
int __ecore_configure_pf_max_bandwidth(struct ecore_hwfn *p_hwfn,
				       struct ecore_ptt *p_ptt,
				       struct ecore_mcp_link_state *p_link,
				       u8 max_bw);
int __ecore_configure_pf_min_bandwidth(struct ecore_hwfn *p_hwfn,
				       struct ecore_ptt *p_ptt,
				       struct ecore_mcp_link_state *p_link,
				       u8 min_bw);
enum _ecore_status_t ecore_mcp_mask_parities(struct ecore_hwfn *p_hwfn,
					     struct ecore_ptt *p_ptt,
					     u32 mask_parities);
/**
 * @brief - Sends crash mdump related info to the MFW.
 *
 * @param p_hwfn
 * @param p_ptt
 *
 * @param return ECORE_SUCCESS upon success.
 */
enum _ecore_status_t ecore_mcp_mdump_set_values(struct ecore_hwfn *p_hwfn,
						struct ecore_ptt *p_ptt,
						u32 epoch);

/**
 * @brief - Triggers a MFW crash dump procedure.
 *
 * @param p_hwfn
 * @param p_ptt
 *
 * @param return ECORE_SUCCESS upon success.
 */
enum _ecore_status_t ecore_mcp_mdump_trigger(struct ecore_hwfn *p_hwfn,
					     struct ecore_ptt *p_ptt);

/**
 * @brief - Clears the MFW crash dump logs.
 *
 * @param p_hwfn
 * @param p_ptt
 *
 * @param return ECORE_SUCCESS upon success.
 */
enum _ecore_status_t ecore_mcp_mdump_clear_logs(struct ecore_hwfn *p_hwfn,
						struct ecore_ptt *p_ptt);

/**
 * @brief - Gets the MFW crash dump configuration and logs info.
 *
 * @param p_hwfn
 * @param p_ptt
 *
 * @param return ECORE_SUCCESS upon success.
 */
enum _ecore_status_t ecore_mcp_mdump_get_info(struct ecore_hwfn *p_hwfn,
					      struct ecore_ptt *p_ptt);

enum _ecore_status_t ecore_mcp_get_resc_info(struct ecore_hwfn *p_hwfn,
					     struct ecore_ptt *p_ptt,
					     struct resource_info *p_resc_info,
					     u32 *p_mcp_resp, u32 *p_mcp_param);

/**
 * @brief - Initiates PF FLR
 *
 * @param p_hwfn
 * @param p_ptt
 *
 * @param return ECORE_SUCCESS upon success.
 */
enum _ecore_status_t ecore_mcp_initiate_pf_flr(struct ecore_hwfn *p_hwfn,
					       struct ecore_ptt *p_ptt);

#endif /* __ECORE_MCP_H__ */
an class="n">szedata2_mac_check_mode cgmii_ibuf_mac_mode_read(volatile struct szedata2_cgmii_ibuf *ibuf) { switch (rte_le_to_cpu_32(ibuf->mac_chmode) & 0x3) { case 0x0: return SZEDATA2_MAC_CHMODE_PROMISC; case 0x1: return SZEDATA2_MAC_CHMODE_ONLY_VALID; case 0x2: return SZEDATA2_MAC_CHMODE_ALL_BROADCAST; case 0x3: return SZEDATA2_MAC_CHMODE_ALL_MULTICAST; default: return SZEDATA2_MAC_CHMODE_PROMISC; } } /* * Writes "mode" in MAC address check mode register. */ static inline void cgmii_ibuf_mac_mode_write(volatile struct szedata2_cgmii_ibuf *ibuf, enum szedata2_mac_check_mode mode) { ibuf->mac_chmode = rte_cpu_to_le_32( (rte_le_to_cpu_32(ibuf->mac_chmode) & ~0x3) | mode); } /* * Structure describes CGMII OBUF address space */ struct szedata2_cgmii_obuf { /** Total Sent Frames Counter low part */ uint32_t tsfcl; /** Octets Sent Counter low part */ uint32_t oscl; /** Total Discarded Frames Counter low part */ uint32_t tdfcl; /** reserved */ uint32_t reserved1; /** Total Sent Frames Counter high part */ uint32_t tsfch; /** Octets Sent Counter high part */ uint32_t osch; /** Total Discarded Frames Counter high part */ uint32_t tdfch; /** reserved */ uint32_t reserved2; /** OBUF enable register */ uint32_t obuf_en; /** reserved */ uint64_t reserved3; /** OBUF control register */ uint32_t ctrl; /** OBUF status register */ uint32_t obuf_st; } __rte_packed; /* * @return * true if OBUF is enabled * false if OBUF is disabled */ static inline bool cgmii_obuf_is_enabled(volatile struct szedata2_cgmii_obuf *obuf) { return ((rte_le_to_cpu_32(obuf->obuf_en) & 0x1) != 0) ? true : false; } /* * Enables OBUF. */ static inline void cgmii_obuf_enable(volatile struct szedata2_cgmii_obuf *obuf) { obuf->obuf_en = rte_cpu_to_le_32(rte_le_to_cpu_32(obuf->obuf_en) | 0x1); } /* * Disables OBUF. */ static inline void cgmii_obuf_disable(volatile struct szedata2_cgmii_obuf *obuf) { obuf->obuf_en = rte_cpu_to_le_32(rte_le_to_cpu_32(obuf->obuf_en) & ~0x1); } /* * Function takes value from IBUF status register. Values in IBUF and OBUF * should be same. * * @return Link speed constant. */ static inline enum szedata2_link_speed cgmii_link_speed(volatile struct szedata2_cgmii_ibuf *ibuf) { uint32_t speed = (rte_le_to_cpu_32(ibuf->ibuf_st) & 0x70) >> 4; switch (speed) { case 0x03: return SZEDATA2_LINK_SPEED_10G; case 0x04: return SZEDATA2_LINK_SPEED_40G; case 0x05: return SZEDATA2_LINK_SPEED_100G; default: return SZEDATA2_LINK_SPEED_DEFAULT; } } /* * IBUFs and OBUFs can generally be located at different offsets in different * firmwares. * This part defines base offsets of IBUFs and OBUFs through various firmwares. * Currently one firmware type is supported. * Type of firmware is set through configuration option * CONFIG_RTE_LIBRTE_PMD_SZEDATA_AS. * Possible values are: * 0 - for firmwares: * NIC_100G1_LR4 * HANIC_100G1_LR4 * HANIC_100G1_SR10 */ #if !defined(RTE_LIBRTE_PMD_SZEDATA2_AS) #error "RTE_LIBRTE_PMD_SZEDATA2_AS has to be defined" #elif RTE_LIBRTE_PMD_SZEDATA2_AS == 0 /* * CGMII IBUF offset from the beginning of PCI resource address space. */ #define SZEDATA2_CGMII_IBUF_BASE_OFF 0x8000 /* * Size of CGMII IBUF. */ #define SZEDATA2_CGMII_IBUF_SIZE 0x200 /* * GCMII OBUF offset from the beginning of PCI resource address space. */ #define SZEDATA2_CGMII_OBUF_BASE_OFF 0x9000 /* * Size of CGMII OBUF. */ #define SZEDATA2_CGMII_OBUF_SIZE 0x100 #else #error "RTE_LIBRTE_PMD_SZEDATA2_AS has wrong value, see comments in config file" #endif #endif