1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
|
/*
* BSD LICENSE
*
* Copyright (C) IBM Corporation 2014.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* * Neither the name of IBM Corporation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _RTE_CYCLES_PPC_64_H_
#define _RTE_CYCLES_PPC_64_H_
#ifdef __cplusplus
extern "C" {
#endif
#include "generic/rte_cycles.h"
#include <rte_byteorder.h>
#include <rte_common.h>
/**
* Read the time base register.
*
* @return
* The time base for this lcore.
*/
static inline uint64_t
rte_rdtsc(void)
{
union {
uint64_t tsc_64;
RTE_STD_C11
struct {
#if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
uint32_t hi_32;
uint32_t lo_32;
#else
uint32_t lo_32;
uint32_t hi_32;
#endif
};
} tsc;
uint32_t tmp;
asm volatile(
"0:\n"
"mftbu %[hi32]\n"
"mftb %[lo32]\n"
"mftbu %[tmp]\n"
"cmpw %[tmp],%[hi32]\n"
"bne 0b\n"
: [hi32] "=r"(tsc.hi_32), [lo32] "=r"(tsc.lo_32),
[tmp] "=r"(tmp)
);
return tsc.tsc_64;
}
static inline uint64_t
rte_rdtsc_precise(void)
{
rte_mb();
return rte_rdtsc();
}
static inline uint64_t
rte_get_tsc_cycles(void) { return rte_rdtsc(); }
#ifdef __cplusplus
}
#endif
#endif /* _RTE_CYCLES_PPC_64_H_ */
|