blob: 45ddf44cc951f6d8d1b90a950ba2fd12ae0dc3ef (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
|
DPDK_2.2 {
global:
_rte_eth_dev_callback_process;
rte_eth_add_rx_callback;
rte_eth_add_tx_callback;
rte_eth_allmulticast_disable;
rte_eth_allmulticast_enable;
rte_eth_allmulticast_get;
rte_eth_copy_pci_info;
rte_eth_dev_allocate;
rte_eth_dev_allocated;
rte_eth_dev_attach;
rte_eth_dev_bypass_event_show;
rte_eth_dev_bypass_event_store;
rte_eth_dev_bypass_init;
rte_eth_dev_bypass_state_set;
rte_eth_dev_bypass_state_show;
rte_eth_dev_bypass_ver_show;
rte_eth_dev_bypass_wd_reset;
rte_eth_dev_bypass_wd_timeout_show;
rte_eth_dev_callback_process;
rte_eth_dev_callback_register;
rte_eth_dev_callback_unregister;
rte_eth_dev_close;
rte_eth_dev_configure;
rte_eth_dev_count;
rte_eth_dev_default_mac_addr_set;
rte_eth_dev_detach;
rte_eth_dev_filter_ctrl;
rte_eth_dev_filter_supported;
rte_eth_dev_flow_ctrl_get;
rte_eth_dev_flow_ctrl_set;
rte_eth_dev_get_dcb_info;
rte_eth_dev_get_eeprom;
rte_eth_dev_get_eeprom_length;
rte_eth_dev_get_mtu;
rte_eth_dev_get_reg_info;
rte_eth_dev_get_vlan_offload;
rte_eth_devices;
rte_eth_dev_info_get;
rte_eth_dev_is_valid_port;
rte_eth_dev_mac_addr_add;
rte_eth_dev_mac_addr_remove;
rte_eth_dev_priority_flow_ctrl_set;
rte_eth_dev_release_port;
rte_eth_dev_rss_hash_conf_get;
rte_eth_dev_rss_hash_update;
rte_eth_dev_rss_reta_query;
rte_eth_dev_rss_reta_update;
rte_eth_dev_rx_intr_ctl;
rte_eth_dev_rx_intr_ctl_q;
rte_eth_dev_rx_intr_disable;
rte_eth_dev_rx_intr_enable;
rte_eth_dev_rx_queue_start;
rte_eth_dev_rx_queue_stop;
rte_eth_dev_set_eeprom;
rte_eth_dev_set_link_down;
rte_eth_dev_set_link_up;
rte_eth_dev_set_mc_addr_list;
rte_eth_dev_set_mtu;
rte_eth_dev_set_rx_queue_stats_mapping;
rte_eth_dev_set_tx_queue_stats_mapping;
rte_eth_dev_set_vf_rx;
rte_eth_dev_set_vf_rxmode;
rte_eth_dev_set_vf_tx;
rte_eth_dev_set_vf_vlan_filter;
rte_eth_dev_set_vlan_offload;
rte_eth_dev_set_vlan_pvid;
rte_eth_dev_set_vlan_strip_on_queue;
rte_eth_dev_socket_id;
rte_eth_dev_start;
rte_eth_dev_stop;
rte_eth_dev_tx_queue_start;
rte_eth_dev_tx_queue_stop;
rte_eth_dev_uc_all_hash_table_set;
rte_eth_dev_uc_hash_table_set;
rte_eth_dev_vlan_filter;
rte_eth_dev_wd_timeout_store;
rte_eth_dma_zone_reserve;
rte_eth_driver_register;
rte_eth_led_off;
rte_eth_led_on;
rte_eth_link;
rte_eth_link_get;
rte_eth_link_get_nowait;
rte_eth_macaddr_get;
rte_eth_mirror_rule_reset;
rte_eth_mirror_rule_set;
rte_eth_promiscuous_disable;
rte_eth_promiscuous_enable;
rte_eth_promiscuous_get;
rte_eth_remove_rx_callback;
rte_eth_remove_tx_callback;
rte_eth_rx_queue_info_get;
rte_eth_rx_queue_setup;
rte_eth_set_queue_rate_limit;
rte_eth_set_vf_rate_limit;
rte_eth_stats;
rte_eth_stats_get;
rte_eth_stats_reset;
rte_eth_timesync_adjust_time;
rte_eth_timesync_disable;
rte_eth_timesync_enable;
rte_eth_timesync_read_rx_timestamp;
rte_eth_timesync_read_time;
rte_eth_timesync_read_tx_timestamp;
rte_eth_timesync_write_time;
rte_eth_tx_queue_info_get;
rte_eth_tx_queue_setup;
rte_eth_xstats_get;
rte_eth_xstats_reset;
local: *;
};
DPDK_16.04 {
global:
rte_eth_dev_get_supported_ptypes;
rte_eth_dev_l2_tunnel_eth_type_conf;
rte_eth_dev_l2_tunnel_offload_set;
rte_eth_dev_set_vlan_ether_type;
rte_eth_dev_udp_tunnel_port_add;
rte_eth_dev_udp_tunnel_port_delete;
rte_eth_speed_bitflag;
rte_eth_tx_buffer_count_callback;
rte_eth_tx_buffer_drop_callback;
rte_eth_tx_buffer_init;
rte_eth_tx_buffer_set_err_callback;
} DPDK_2.2;
DPDK_16.07 {
global:
rte_eth_add_first_rx_callback;
rte_eth_dev_get_name_by_port;
rte_eth_dev_get_port_by_name;
rte_eth_xstats_get_names;
} DPDK_16.04;
|
