diff options
| -rw-r--r-- | scripts/automation/regression/stateless_tests/stl_rx_test.py | 20 | ||||
| -rw-r--r-- | src/main_dpdk.cpp | 15 |
2 files changed, 15 insertions, 20 deletions
diff --git a/scripts/automation/regression/stateless_tests/stl_rx_test.py b/scripts/automation/regression/stateless_tests/stl_rx_test.py index 16029908..3127a196 100644 --- a/scripts/automation/regression/stateless_tests/stl_rx_test.py +++ b/scripts/automation/regression/stateless_tests/stl_rx_test.py @@ -28,10 +28,11 @@ class STLRX_Test(CStlGeneral_Test): self.skip('port {0} does not support RX'.format(self.rx_port)) self.cap = cap - self.rate_percent = per_driver_params[port_info['driver']][0] - self.total_pkts = per_driver_params[port_info['driver']][1] - if len(per_driver_params[port_info['driver']]) > 2: - self.rate_lat = per_driver_params[port_info['driver']][2] + drv_name = port_info['driver'] + self.rate_percent = per_driver_params[drv_name][0] + self.total_pkts = per_driver_params[drv_name][1] + if len(per_driver_params[drv_name]) > 2: + self.rate_lat = per_driver_params[drv_name][2] else: self.rate_lat = self.rate_percent self.drops_expected = False @@ -41,8 +42,6 @@ class STLRX_Test(CStlGeneral_Test): self.large_pkt = STLPktBuilder(pkt = Ether()/IP(src="16.0.0.1",dst="48.0.0.1")/UDP(dport=12,sport=1025)/('a'*1000)) self.pkt_9k = STLPktBuilder(pkt = Ether()/IP(src="16.0.0.1",dst="48.0.0.1")/UDP(dport=12,sport=1025)/('a'*9000)) - - drv_name=port_info['driver'] self.latency_9k_enable=per_driver_params[drv_name][3] if self.latency_9k_enable: self.latency_9k_max_average = per_driver_params[drv_name][4] @@ -120,7 +119,7 @@ class STLRX_Test(CStlGeneral_Test): tmp = 'TX pkts mismatch - got: {0}, expected: {1}'.format(tx_pkts, total_pkts) assert False, tmp - if tx_bytes != (total_pkts * (pkt_len + 4)): # + 4 for ethernet CRC + if tx_bytes != (total_pkts * pkt_len): pprint.pprint(flow_stats) tmp = 'TX bytes mismatch - got: {0}, expected: {1}'.format(tx_bytes, (total_pkts * pkt_len)) assert False, tmp @@ -132,7 +131,7 @@ class STLRX_Test(CStlGeneral_Test): if "rx_bytes" in self.cap: rx_bytes = flow_stats['rx_bytes'].get(self.rx_port, 0) - if rx_bytes != (total_pkts * (pkt_len + 4)) and not self.drops_expected: # +4 for ethernet CRC + if rx_bytes != (total_pkts * pkt_len) and not self.drops_expected: pprint.pprint(flow_stats) tmp = 'RX bytes mismatch - got: {0}, expected: {1}'.format(rx_bytes, (total_pkts * pkt_len)) assert False, tmp @@ -148,12 +147,13 @@ class STLRX_Test(CStlGeneral_Test): stats = self.c.get_stats() for exp in exp_list: - self.__verify_flow(exp['pg_id'], exp['total_pkts'], exp['pkt_len'], stats) + # Expecting to get pkt_len + 4 because of ethernet FCS + self.__verify_flow(exp['pg_id'], exp['total_pkts'], exp['pkt_len'] + 4, stats) # one stream on TX --> RX def test_one_stream(self): - total_pkts = self.total_pkts * 10 + total_pkts = self.total_pkts try: s1 = STLStream(name = 'rx', diff --git a/src/main_dpdk.cpp b/src/main_dpdk.cpp index 2ef06157..45e46810 100644 --- a/src/main_dpdk.cpp +++ b/src/main_dpdk.cpp @@ -4341,20 +4341,15 @@ bool CCoreEthIF::process_rx_pkt(pkt_dir_t dir, } bool send=false; + // e1000 on ESXI hands us the packet with the ethernet FCS + if (parser.getPktSize() < m->pkt_len) { + rte_pktmbuf_trim(m, m->pkt_len - parser.getPktSize()); + } + if ( get_is_stateless() ) { // In stateless RX, we only care about flow stat packets if ((parser.getIpId() & 0xff00) == IP_ID_RESERVE_BASE) { send = true; - if (parser.getIpId() == FLOW_STAT_PAYLOAD_IP_ID) { - // e1000 on ESXI appends 4 bytes to the packet. - // This is a best effort hack to get our latency info which we put at the end of the packet - uint8_t *p = rte_pktmbuf_mtod(m, uint8_t*); - struct flow_stat_payload_header *fsp_head = (struct flow_stat_payload_header *) - (p + m->pkt_len - sizeof(struct flow_stat_payload_header)); - if (fsp_head->magic != FLOW_STAT_PAYLOAD_MAGIC) { - rte_pktmbuf_trim(m, 4); - } - } } } else { CLatencyPktMode *c_l_pkt_mode = g_trex.m_mg.c_l_pkt_mode; |