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-rw-r--r--src/dpdk22/drivers/net/i40e/i40e_ethdev.c50
-rw-r--r--src/dpdk22/drivers/net/i40e/i40e_fdir.c22
-rw-r--r--src/dpdk22/drivers/net/ixgbe/ixgbe_fdir.c23
3 files changed, 88 insertions, 7 deletions
diff --git a/src/dpdk22/drivers/net/i40e/i40e_ethdev.c b/src/dpdk22/drivers/net/i40e/i40e_ethdev.c
index 57de71d5..7542ade1 100644
--- a/src/dpdk22/drivers/net/i40e/i40e_ethdev.c
+++ b/src/dpdk22/drivers/net/i40e/i40e_ethdev.c
@@ -690,6 +690,52 @@ static inline void i40e_flex_payload_reg_init(struct i40e_hw *hw)
#define I40E_FLOW_CONTROL_ETHERTYPE 0x8808
+#define TREX_PATCH
+#ifdef TREX_PATCH
+#define I40E_PRTQF_FD_INSET(_i, _j) (0x00250000 + ((_i) * 64 + (_j) * 32))
+#define I40E_GLQF_FD_MSK(_i, _j) (0x00267200 + ((_i) * 4 + (_j) * 8))
+
+static void i40e_dump_filter_regs(struct i40e_hw *hw)
+{
+ int reg_nums[] = {31, 33, 34, 35, 41, 43};
+ int i;
+ uint32_t reg;
+
+ for (i =0; i < sizeof (reg_nums)/sizeof(int); i++) {
+ reg = I40E_READ_REG(hw,I40E_PRTQF_FD_INSET(reg_nums[i], 0));
+ printf("I40E_PRTQF_FD_INSET(%d, 0): 0x%08x\n", reg_nums[i], reg);
+ reg = I40E_READ_REG(hw,I40E_PRTQF_FD_INSET(reg_nums[i], 1));
+ printf("I40E_PRTQF_FD_INSET(%d, 1): 0x%08x\n", reg_nums[i], reg);
+ }
+}
+
+static inline void i40e_filter_fields_reg_init(struct i40e_hw *hw)
+{
+ uint32_t reg;
+
+ I40E_WRITE_REG(hw, I40E_GLQF_ORT(12), 0x00000062);
+ I40E_WRITE_REG(hw, I40E_GLQF_PIT(2), 0x000024A0);
+ I40E_WRITE_REG(hw, I40E_PRTQF_FD_INSET(31, 0), 0);
+ I40E_WRITE_REG(hw, I40E_PRTQF_FD_INSET(31, 1), 0x00040000);
+ I40E_WRITE_REG(hw, I40E_PRTQF_FD_INSET(33, 0), 0);
+ I40E_WRITE_REG(hw, I40E_PRTQF_FD_INSET(33, 1), 0x00040000);
+ I40E_WRITE_REG(hw, I40E_PRTQF_FD_INSET(41, 0), 0);
+ I40E_WRITE_REG(hw, I40E_PRTQF_FD_INSET(41, 1), 0x00080000);
+ I40E_WRITE_REG(hw, I40E_PRTQF_FD_INSET(43, 0), 0);
+ I40E_WRITE_REG(hw, I40E_PRTQF_FD_INSET(43, 1), 0x00080000);
+ I40E_WRITE_REG(hw, I40E_PRTQF_FD_INSET(34, 0), 0);
+ I40E_WRITE_REG(hw, I40E_PRTQF_FD_INSET(34, 1), 0x00040000);
+ // filter IP according to ttl and L4 protocol
+ I40E_WRITE_REG(hw, I40E_PRTQF_FD_INSET(35, 0), 0);
+ I40E_WRITE_REG(hw, I40E_PRTQF_FD_INSET(35, 1), 0x00040000);
+ I40E_WRITE_REG(hw, I40E_PRTQF_FD_INSET(44, 0), 0);
+ I40E_WRITE_REG(hw, I40E_PRTQF_FD_INSET(44, 1), 0x00080000);
+ I40E_WRITE_REG(hw, I40E_GLQF_FD_MSK(0, 34), 0x000DFF00);
+ I40E_WRITE_REG(hw, I40E_GLQF_FD_MSK(0,44), 0x000C00FF);
+ I40E_WRITE_FLUSH(hw);
+}
+#endif //TREX_PATCH
+
/*
* Add a ethertype filter to drop all flow control frames transmitted
* from VSIs.
@@ -786,7 +832,11 @@ eth_i40e_dev_init(struct rte_eth_dev *dev)
* for flexible payload by software.
* It should be removed once issues are fixed in NVM.
*/
+#ifdef TREX_PATCH
+ i40e_filter_fields_reg_init(hw);
+#else
i40e_flex_payload_reg_init(hw);
+#endif
/* Initialize the parameters for adminq */
i40e_init_adminq_parameter(hw);
diff --git a/src/dpdk22/drivers/net/i40e/i40e_fdir.c b/src/dpdk22/drivers/net/i40e/i40e_fdir.c
index 9ad6981c..194f8629 100644
--- a/src/dpdk22/drivers/net/i40e/i40e_fdir.c
+++ b/src/dpdk22/drivers/net/i40e/i40e_fdir.c
@@ -719,7 +719,8 @@ i40e_fdir_fill_eth_ip_head(const struct rte_eth_fdir_input *fdir_input,
ip->version_ihl = I40E_FDIR_IP_DEFAULT_VERSION_IHL;
/* set len to by default */
ip->total_length = rte_cpu_to_be_16(I40E_FDIR_IP_DEFAULT_LEN);
- ip->time_to_live = I40E_FDIR_IP_DEFAULT_TTL;
+ // TREX_PATCH
+ ip->time_to_live = fdir_input->flow.ip4_flow.ttl;
/*
* The source and destination fields in the transmitted packet
* need to be presented in a reversed order with respect
@@ -727,7 +728,13 @@ i40e_fdir_fill_eth_ip_head(const struct rte_eth_fdir_input *fdir_input,
*/
ip->src_addr = fdir_input->flow.ip4_flow.dst_ip;
ip->dst_addr = fdir_input->flow.ip4_flow.src_ip;
- ip->next_proto_id = next_proto[fdir_input->flow_type];
+ // TREX_PATCH
+ if (fdir_input->flow_type == RTE_ETH_FLOW_FRAG_IPV4
+ || fdir_input->flow_type == RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) {
+ ip->next_proto_id = fdir_input->flow.ip4_flow.l4_protocol;
+ } else {
+ ip->next_proto_id = next_proto[fdir_input->flow_type];
+ }
break;
case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
@@ -741,7 +748,8 @@ i40e_fdir_fill_eth_ip_head(const struct rte_eth_fdir_input *fdir_input,
rte_cpu_to_be_32(I40E_FDIR_IPv6_DEFAULT_VTC_FLOW);
ip6->payload_len =
rte_cpu_to_be_16(I40E_FDIR_IPv6_PAYLOAD_LEN);
- ip6->hop_limits = I40E_FDIR_IPv6_DEFAULT_HOP_LIMITS;
+ // TREX_PATCH
+ ip6->hop_limits = fdir_input->flow.ipv6_flow.hop_limit;
/*
* The source and destination fields in the transmitted packet
@@ -754,7 +762,13 @@ i40e_fdir_fill_eth_ip_head(const struct rte_eth_fdir_input *fdir_input,
rte_memcpy(&(ip6->dst_addr),
&(fdir_input->flow.ipv6_flow.src_ip),
IPV6_ADDR_LEN);
- ip6->proto = next_proto[fdir_input->flow_type];
+ // TREX_PATCH
+ if (fdir_input->flow_type == RTE_ETH_FLOW_FRAG_IPV6
+ || fdir_input->flow_type == RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) {
+ ip6->proto = fdir_input->flow.ipv6_flow.l4_protocol;
+ } else {
+ ip6->proto = next_proto[fdir_input->flow_type];
+ }
break;
default:
PMD_DRV_LOG(ERR, "unknown flow type %u.",
diff --git a/src/dpdk22/drivers/net/ixgbe/ixgbe_fdir.c b/src/dpdk22/drivers/net/ixgbe/ixgbe_fdir.c
index e03219b1..3ebeac4a 100644
--- a/src/dpdk22/drivers/net/ixgbe/ixgbe_fdir.c
+++ b/src/dpdk22/drivers/net/ixgbe/ixgbe_fdir.c
@@ -49,6 +49,7 @@
#include "base/ixgbe_common.h"
#include "ixgbe_ethdev.h"
+#define TREX_PATCH
/* To get PBALLOC (Packet Buffer Allocation) bits from FDIRCTRL value */
#define FDIRCTRL_PBALLOC_MASK 0x03
@@ -248,9 +249,13 @@ configure_fdir_flags(const struct rte_fdir_conf *conf, uint32_t *fdirctrl)
PMD_INIT_LOG(ERR, "Invalid fdir_conf->status value");
return -EINVAL;
};
-
+#define TREX_PATCH
+#ifdef TREX_PATCH
+ *fdirctrl |= (conf->flexbytes_offset << IXGBE_FDIRCTRL_FLEX_SHIFT);
+#else
*fdirctrl |= (IXGBE_DEFAULT_FLEXBYTES_OFFSET / sizeof(uint16_t)) <<
IXGBE_FDIRCTRL_FLEX_SHIFT;
+#endif
if (conf->mode >= RTE_FDIR_MODE_PERFECT &&
conf->mode <= RTE_FDIR_MODE_PERFECT_TUNNEL) {
@@ -507,7 +512,7 @@ ixgbe_set_fdir_flex_conf(struct rte_eth_dev *dev,
uint16_t i;
fdirm = IXGBE_READ_REG(hw, IXGBE_FDIRM);
-
+#ifndef TREX_PATCH
if (conf == NULL) {
PMD_DRV_LOG(ERR, "NULL pointer.");
return -EINVAL;
@@ -548,6 +553,11 @@ ixgbe_set_fdir_flex_conf(struct rte_eth_dev *dev,
return -EINVAL;
}
}
+#else
+ fdirm &= ~IXGBE_FDIRM_FLEX;
+ flexbytes = 1;
+ // fdirctrl gets flex_bytes_offset in configure_fdir_flags
+#endif
IXGBE_WRITE_REG(hw, IXGBE_FDIRM, fdirm);
info->mask.flex_bytes_mask = flexbytes ? UINT16_MAX : 0;
info->flex_bytes_offset = (uint8_t)((*fdirctrl &
@@ -577,7 +587,11 @@ ixgbe_fdir_configure(struct rte_eth_dev *dev)
if (hw->mac.type != ixgbe_mac_X550 &&
hw->mac.type != ixgbe_mac_X550EM_x &&
mode != RTE_FDIR_MODE_SIGNATURE &&
- mode != RTE_FDIR_MODE_PERFECT)
+ mode != RTE_FDIR_MODE_PERFECT
+#ifdef TREX_PATCH
+ && mode != RTE_FDIR_MODE_PERFECT_MAC_VLAN
+#endif
+ )
return -ENOSYS;
err = configure_fdir_flags(&dev->data->dev_conf.fdir_conf, &fdirctrl);
@@ -1116,11 +1130,14 @@ ixgbe_add_del_fdir_filter(struct rte_eth_dev *dev,
return err;
if (is_perfect) {
+#ifndef TREX_PATCH
+ // No reason not use IPV6 in perfect filters. It is working.
if (input.formatted.flow_type & IXGBE_ATR_L4TYPE_IPV6_MASK) {
PMD_DRV_LOG(ERR, "IPv6 is not supported in"
" perfect mode!");
return -ENOTSUP;
}
+#endif
fdirhash = atr_compute_perfect_hash_82599(&input,
dev->data->dev_conf.fdir_conf.pballoc);
fdirhash |= fdir_filter->soft_id <<