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path: root/src/bp_sim.cpp
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2016-06-14coverity fixesIdo Barnea1-1/+1
2016-06-05Merge branch 'master' into cpu_per_coreYaroslav Brustinov1-0/+9
2016-06-05cpu utilization: don't return vectors, only change passed arguments.Yaroslav Brustinov1-8/+6
2016-06-02cpu utilization per thread + mbufs per socket + add in tuiYaroslav Brustinov1-44/+23
2016-06-02watchdog phase 2imarom1-0/+9
2016-05-31add rpc command get_cpu_util_full to cppYaroslav Brustinov1-0/+10
2016-05-18unit tests + simulator workIdo Barnea1-183/+200
2016-05-10cpu% without tscHanoh Haim1-1/+4
2016-05-10merge from masterHanoh Haim1-264/+149
2016-05-10refactor the schduler to be with minimum TSC instructionsHanoh Haim1-0/+291
2016-05-09PCAP remote gtestsimarom1-18/+49
2016-05-09PCAP remote code review fixesimarom1-85/+106
2016-05-09PCAP refinementimarom1-9/+6
2016-05-09first remote PCAP push - draftimarom1-61/+81
2016-05-08add cache to CPHanoh Haim1-9/+15
2016-05-08add cache capability to stateless node objectHanoh Haim1-3/+17
2016-05-03bp_sim: correct description of supported stateful layersYaroslav Brustinov1-2/+2
main_dpdk: send bw_per_core with json, return back precision of low values jsonrpcserver: disable logging regression: use bw_per_core from cpp calculation correct test name for GA
2016-04-10memory error on simulationimarom1-1/+6
2016-04-10Merge trex-197 bug fixHanoh Haim1-1/+5
2016-04-10fix trex-197Hanoh Haim1-2/+71
2016-04-10NULL stream and multi core better support for streamsimarom1-1/+5
2016-03-2310G and VM workIdo Barnea1-1/+6
2016-03-03changing "latency" to "rx" + rx core options logic fixIdo Barnea1-26/+26
indentation fix, whitespace cleanup
2016-02-23some mods to the rateimarom1-1/+4
2016-02-15add support for dp mac replace mode-golden were changedHanoh Haim1-0/+12
2016-02-01Merge from originHanoh Haim1-6/+15
2016-02-01fix for http://trex-tgn.cisco.com/youtrack/issue/trex-174imarom1-6/+15
2016-02-01trex-173, remove support for one-app-server in global configuration.wenxian li1-6/+4
2016-01-19Adding option to pass NAT info in TCP ACK of first SYNIdo Barnea1-78/+113
2016-01-07stateless sim dry was "too much" dry - no only I/O is skippedimarom1-12/+6
2016-01-07yet another stateless simulation phaseimarom1-0/+2
2016-01-07more options to the stateless simulationimarom1-4/+1
2016-01-05Merge branch 'random_pkt'Hanoh Haim1-14/+32
2016-01-05stateful load 9k packetsHanoh Haim1-4/+1
2016-01-059k packet size does not work for VMXNET3Hanoh Haim1-2/+2
2016-01-05stateless sim - core_index and all cores simulationimarom1-7/+18
2016-01-04simulation end to endimarom1-4/+9
2015-12-28maximum packet size support 9k - simulationHanoh Haim1-11/+32
2015-12-15Merging lastest 'master' to side branch 'vm'imarom1-0/+2
Conflicts: scripts/automation/trex_control_plane/console/trex_console.py
2015-12-15fixing crash in ipv6 rx-check modeIdo Barnea1-0/+2
2015-12-14merge from masterHanoh Haim1-897/+3
2015-12-01Added ICMP latency packet modesIdo Barnea1-897/+3
2015-11-30vm mode works - first testHanoh Haim1-4/+15
2015-11-22fix stop on duration per portHanoh Haim1-2/+3
2015-11-19support debug logs in case of dpdk debug imageHanoh Haim1-1/+5
2015-11-19 minor typo fixHanoh Haim1-4/+4
2015-11-18add support for a program of streams. refactor the dp codeHanoh Haim1-5/+39
2015-11-16 clean termination - stateless and stateful - fix pure virtual function errorHanoh Haim1-1/+7
2015-11-11add support for multi-burstHanoh Haim1-1/+0
2015-11-11add first stl test and cleanup valgrindHanoh Haim1-48/+126