summaryrefslogtreecommitdiffstats
path: root/src/sim/trex_sim.h
AgeCommit message (Collapse)AuthorFilesLines
2016-08-15core mask - first phaseimarom1-0/+3
2016-04-10NULL stream and multi core better support for streamsimarom1-2/+4
2016-03-10RX stats - major refactorimarom1-0/+2
2016-03-02TX barrierimarom1-1/+0
2016-02-25port attributes - promiscuous and etc.imarom1-45/+0
2016-02-24Rx stat per flow. Low level working for xl710, and partly for i350.Ido Barnea1-0/+5
added full clone (with CP VM) to stream
2016-02-24virtual NICs does not add 4 bytes of CRCimarom1-1/+5
2016-02-23global srand messed up stuffimarom1-2/+3
moved to local rand_r
2016-02-23some mods to the rateimarom1-6/+55
2016-01-07stateless sim dry was "too much" dry - no only I/O is skippedimarom1-1/+1
2016-01-07yet another stateless simulation phaseimarom1-1/+5
2016-01-07more options to the stateless simulationimarom1-1/+16
2016-01-05stateless sim - core_index and all cores simulationimarom1-2/+4
2016-01-04some additions to the stateless simulation modeimarom1-3/+14
2016-01-04a script to inject simulation stateless filesimarom1-0/+3
2016-01-04simulation end to endimarom1-0/+132