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authorTibor Frank <tifrank@cisco.com>2018-01-30 09:45:16 +0100
committerTibor Frank <tifrank@cisco.com>2018-01-30 09:45:16 +0100
commit2cf48780a763a774c2b0f4173a3b7c82bbd09158 (patch)
tree590b49050a0ae46f5d96e470b98f73129239c829
parented69178aaddaba42d67c9def3deb8bad12129028 (diff)
Report: add source data
Change-Id: I471eb0d703f47d81b32ce0d1eb4f8cc6eb8d15ea Signed-off-by: Tibor Frank <tifrank@cisco.com>
-rw-r--r--resources/tools/presentation/specification.yaml13
1 files changed, 9 insertions, 4 deletions
diff --git a/resources/tools/presentation/specification.yaml b/resources/tools/presentation/specification.yaml
index 183de7c2e7..cb51e8c016 100644
--- a/resources/tools/presentation/specification.yaml
+++ b/resources/tools/presentation/specification.yaml
@@ -108,7 +108,9 @@
# TODO: Add the data sources
plot-throughput-speedup-analysis:
csit-vpp-perf-1801-all:
- - 12
+ - 13
+ - 14
+ - 21
performance-improvements:
csit-vpp-perf-1707-all:
- 9
@@ -136,6 +138,7 @@
csit-vpp-perf-1801-all:
- 13
- 14
+ - 21
csit-ligato-perf-1710-all:
- 5
- 7
@@ -179,6 +182,7 @@
csit-vpp-perf-1801-all:
- 13
- 14
+ - 21
plot-dpdk-throughput-latency:
csit-dpdk-perf-1801-all:
- 1
@@ -379,9 +383,10 @@
- 23
# TODO:
csit-vpp-perf-1801-all:
- - 12
- - 13
- - 14
+ - 12 # full
+ - 13 # sel
+ - 14 # sel
+ - 21 # sel
csit-ligato-perf-1710-all:
- 5
- 7