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| author |   Vratko Polak <vrpolak@cisco.com> | 2020-03-31 20:10:46 +0200 |
|---|---|---|
| committer | Vratko Polak <vrpolak@cisco.com> | 2020-04-01 14:30:09 +0000 |
| commit | 925c5bfcffb2bc6b833a8e64b7f3a06bbca52197 (patch) | |
| tree | 3e36b681a3f0696ae907ea542c98e5bb0c31186b /PyPI | |
| parent | 919d9ebab430db35c303a26f52be0751962183be (diff) | |
Tweak TRex cores and RDMA pps limit
The previous values lead to duration stretching,
which affects MRR results (making receive rate bigger than it really is).
+ Move timestamp for starting of traffic,
the previous position was too conservative.
Change-Id: Ie983f0d3eacf56d57caa551d1b7fbb87ece6c158
Signed-off-by: Vratko Polak <vrpolak@cisco.com>
Diffstat (limited to 'PyPI')
0 files changed, 0 insertions, 0 deletions