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authorTibor Frank <tifrank@cisco.com>2018-11-05 15:01:37 +0100
committerTibor Frank <tifrank@cisco.com>2018-11-05 15:01:37 +0100
commitb641b5bf12a0d1b63ac9afb7c89133297d3b63fe (patch)
tree88342914639827399e40c68bf6c029f9e53cea3b /docs/report/dpdk_performance_tests/packet_latency_graphs
parent312e541e0cc53a10429c40b41ad7f22ae4b8adc2 (diff)
CSIT-1342: Edit the static content for CSIT-1810 report
Change-Id: I44abd4ad646813cc70e9fa2b46b51ee7613dc501 Signed-off-by: Tibor Frank <tifrank@cisco.com>
Diffstat (limited to 'docs/report/dpdk_performance_tests/packet_latency_graphs')
-rw-r--r--docs/report/dpdk_performance_tests/packet_latency_graphs/ip4.rst4
-rw-r--r--docs/report/dpdk_performance_tests/packet_latency_graphs/l2.rst4
2 files changed, 8 insertions, 0 deletions
diff --git a/docs/report/dpdk_performance_tests/packet_latency_graphs/ip4.rst b/docs/report/dpdk_performance_tests/packet_latency_graphs/ip4.rst
index 9dd2add5aa..8f5b807240 100644
--- a/docs/report/dpdk_performance_tests/packet_latency_graphs/ip4.rst
+++ b/docs/report/dpdk_performance_tests/packet_latency_graphs/ip4.rst
@@ -39,6 +39,10 @@ a.k.a. L3FWD data plane thread(s), and their physical CPU core(s) placement.
CSIT source code for the test cases used for plots can be found in
`CSIT git repository <https://git.fd.io/csit/tree/tests/dpdk/perf?h=rls1810>`_.
+.. raw:: latex
+
+ \clearpage
+
3n-hsw-x520
~~~~~~~~~~~
diff --git a/docs/report/dpdk_performance_tests/packet_latency_graphs/l2.rst b/docs/report/dpdk_performance_tests/packet_latency_graphs/l2.rst
index a673dc1318..32dec95c00 100644
--- a/docs/report/dpdk_performance_tests/packet_latency_graphs/l2.rst
+++ b/docs/report/dpdk_performance_tests/packet_latency_graphs/l2.rst
@@ -40,6 +40,10 @@ thread(s), and their physical CPU core(s) placement.
CSIT source code for the test cases used for plots can be found in
`CSIT git repository <https://git.fd.io/csit/tree/tests/dpdk/perf?h=rls1810>`_.
+.. raw:: latex
+
+ \clearpage
+
3n-hsw-x520
~~~~~~~~~~~