diff options
| author |   Tibor Frank <tifrank@cisco.com> | 2018-11-05 15:01:37 +0100 |
|---|---|---|
| committer | Tibor Frank <tifrank@cisco.com> | 2018-11-05 15:01:37 +0100 |
| commit | b641b5bf12a0d1b63ac9afb7c89133297d3b63fe (patch) | |
| tree | 88342914639827399e40c68bf6c029f9e53cea3b /docs/report/dpdk_performance_tests | |
| parent | 312e541e0cc53a10429c40b41ad7f22ae4b8adc2 (diff) | |
CSIT-1342: Edit the static content for CSIT-1810 report
Change-Id: I44abd4ad646813cc70e9fa2b46b51ee7613dc501
Signed-off-by: Tibor Frank <tifrank@cisco.com>
Diffstat (limited to 'docs/report/dpdk_performance_tests')
4 files changed, 16 insertions, 4 deletions
diff --git a/docs/report/dpdk_performance_tests/packet_latency_graphs/ip4.rst b/docs/report/dpdk_performance_tests/packet_latency_graphs/ip4.rst index 9dd2add5aa..8f5b807240 100644 --- a/docs/report/dpdk_performance_tests/packet_latency_graphs/ip4.rst +++ b/docs/report/dpdk_performance_tests/packet_latency_graphs/ip4.rst @@ -39,6 +39,10 @@ a.k.a. L3FWD data plane thread(s), and their physical CPU core(s) placement. CSIT source code for the test cases used for plots can be found in `CSIT git repository <https://git.fd.io/csit/tree/tests/dpdk/perf?h=rls1810>`_. +.. raw:: latex + + \clearpage + 3n-hsw-x520 ~~~~~~~~~~~ diff --git a/docs/report/dpdk_performance_tests/packet_latency_graphs/l2.rst b/docs/report/dpdk_performance_tests/packet_latency_graphs/l2.rst index a673dc1318..32dec95c00 100644 --- a/docs/report/dpdk_performance_tests/packet_latency_graphs/l2.rst +++ b/docs/report/dpdk_performance_tests/packet_latency_graphs/l2.rst @@ -40,6 +40,10 @@ thread(s), and their physical CPU core(s) placement. CSIT source code for the test cases used for plots can be found in `CSIT git repository <https://git.fd.io/csit/tree/tests/dpdk/perf?h=rls1810>`_. +.. raw:: latex + + \clearpage + 3n-hsw-x520 ~~~~~~~~~~~ diff --git a/docs/report/dpdk_performance_tests/packet_throughput_graphs/ip4.rst b/docs/report/dpdk_performance_tests/packet_throughput_graphs/ip4.rst index 77ed39ad32..190aa3d6ac 100644 --- a/docs/report/dpdk_performance_tests/packet_throughput_graphs/ip4.rst +++ b/docs/report/dpdk_performance_tests/packet_throughput_graphs/ip4.rst @@ -40,6 +40,10 @@ data plane thread(s), and their physical CPU core(s) placement. CSIT source code for the test cases used for plots can be found in `CSIT git repository <https://git.fd.io/csit/tree/tests/dpdk/perf?h=rls1810>`_. +.. raw:: latex + + \clearpage + 3n-hsw-x520 ~~~~~~~~~~~ diff --git a/docs/report/dpdk_performance_tests/packet_throughput_graphs/l2.rst b/docs/report/dpdk_performance_tests/packet_throughput_graphs/l2.rst index eeb4d652d5..143b864e8f 100644 --- a/docs/report/dpdk_performance_tests/packet_throughput_graphs/l2.rst +++ b/docs/report/dpdk_performance_tests/packet_throughput_graphs/l2.rst @@ -1,8 +1,4 @@ -.. raw:: latex - - \clearpage - .. raw:: html <script type="text/javascript"> @@ -40,6 +36,10 @@ data plane thread(s), and their physical CPU core(s) placement. CSIT source code for the test cases used for plots can be found in `CSIT git repository <https://git.fd.io/csit/tree/tests/dpdk/perf?h=rls1810>`_. +.. raw:: latex + + \clearpage + 3n-hsw-x520 ~~~~~~~~~~~ |