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author | Tibor Frank <tifrank@cisco.com> | 2019-02-05 10:20:41 +0100 |
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committer | Tibor Frank <tifrank@cisco.com> | 2019-02-05 13:30:25 +0000 |
commit | 124101d22151239b0411a73ae4d2bf8d70970937 (patch) | |
tree | 3910b6e04d4737cbfc3295a25f86e7aaa3050d6a /docs/report/introduction/methodology_packet_latency.rst | |
parent | a221ffe6144eb0f372521fbbc828b8a225af12cd (diff) |
CSIT-1420: Split methodology section to more files
Change-Id: I861e578434abdf72244d684fca8cfd66e1db9c28
Signed-off-by: Tibor Frank <tifrank@cisco.com>
Diffstat (limited to 'docs/report/introduction/methodology_packet_latency.rst')
-rw-r--r-- | docs/report/introduction/methodology_packet_latency.rst | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/docs/report/introduction/methodology_packet_latency.rst b/docs/report/introduction/methodology_packet_latency.rst new file mode 100644 index 0000000000..550d12f688 --- /dev/null +++ b/docs/report/introduction/methodology_packet_latency.rst @@ -0,0 +1,23 @@ +Packet Latency +-------------- + +TRex Traffic Generator (TG) is used for measuring latency of VPP DUTs. +Reported latency values are measured using following methodology: + +- Latency tests are performed at 100% of discovered NDR and PDR rates + for each throughput test and packet size (except IMIX). +- TG sends dedicated latency streams, one per direction, each at the + rate of 9 kpps at the prescribed packet size; these are sent in + addition to the main load streams. +- TG reports min/avg/max latency values per stream direction, hence two + sets of latency values are reported per test case; future release of + TRex is expected to report latency percentiles. +- Reported latency values are aggregate across two SUTs due to three + node topology used for all performance tests; for per SUT latency, + reported value should be divided by two. +- 1usec is the measurement accuracy advertised by TRex TG for the setup + used in FD.io labs used by CSIT project. +- TRex setup introduces an always-on error of about 2*2usec per latency + flow additonal Tx/Rx interface latency induced by TRex SW writing and + reading packet timestamps on CPU cores without HW acceleration on NICs + closer to the interface line. |