aboutsummaryrefslogtreecommitdiffstats
path: root/docs/report/introduction/physical_testbeds.rst
diff options
context:
space:
mode:
authorTibor Frank <tifrank@cisco.com>2023-01-04 11:08:47 +0100
committerTibor Frank <tifrank@cisco.com>2023-01-05 06:18:00 +0100
commit3055ecfbb0b619318f7cfbbb18ba142968b4c617 (patch)
tree659f77115b28be3b6c2ffab992f3905f87874fca /docs/report/introduction/physical_testbeds.rst
parent2468e5040c36889c62105ba937b9e6412727aa47 (diff)
Report: Remove DNV testbeds
Signed-off-by: Tibor Frank <tifrank@cisco.com> Change-Id: Id54919579a245ef9f44a9599b8e2d4f3bd320e84
Diffstat (limited to 'docs/report/introduction/physical_testbeds.rst')
-rw-r--r--docs/report/introduction/physical_testbeds.rst82
1 files changed, 0 insertions, 82 deletions
diff --git a/docs/report/introduction/physical_testbeds.rst b/docs/report/introduction/physical_testbeds.rst
index 2497de88b9..5a9b1edf97 100644
--- a/docs/report/introduction/physical_testbeds.rst
+++ b/docs/report/introduction/physical_testbeds.rst
@@ -241,88 +241,6 @@ SUT and TG NICs:
All Intel Xeon Icelake servers run with Intel Hyper-Threading enabled,
doubling the number of logical cores exposed to Linux.
-.. _physical_testbeds_2n_dnv:
-
-2-Node Atom Denverton (2n-dnv)
-------------------------------
-
-2n-dnv testbed is built with: i) one Intel S2600WFT server acting as TG
-and equipped with two Intel Xeon Skylake Platinum 8180 processors (38.5
-MB Cache, 2.50 GHz, 28 cores), and ii) one SuperMicro SYS-E300-9A server
-acting as SUT and equipped with one Intel Atom C3858 processor (12 MB
-Cache, 2.00 GHz, 12 cores). 2n-dnv physical topology is shown below.
-
-.. only:: latex
-
- .. raw:: latex
-
- \begin{figure}[H]
- \centering
- \graphicspath{{../_tmp/src/introduction/}}
- \includegraphics[width=0.90\textwidth]{testbed-2n-dnv}
- \label{fig:testbed-2n-dnv}
- \end{figure}
-
-.. only:: html
-
- .. figure:: testbed-2n-dnv.svg
- :alt: testbed-2n-dnv
- :align: center
-
-SUT 10GE NIC ports:
-
-#. P-1: x553 copper port.
-#. P-2: x553 copper port.
-#. P-3: x553 fiber port.
-#. P-4: x553 fiber port.
-
-TG NICs:
-
-#. NIC-1: x550-T2 2p10GE Intel.
-#. NIC-2: x550-T2 2p10GE Intel.
-#. NIC-3: x520-DA2 2p10GE Intel.
-#. NIC-4: x520-DA2 2p10GE Intel.
-
-The 2n-dnv testbed is in operation in Intel SH labs.
-
-.. _physical_testbeds_3n_dnv:
-
-3-Node Atom Denverton (3n-dnv)
-------------------------------
-
-One 3n-dnv testbed is built with: i) one SuperMicro SYS-7049GP-TRT
-server acting as TG and equipped with two Intel Xeon Skylake Platinum
-8180 processors (38.5 MB Cache, 2.50 GHz, 28 cores), and ii) one
-SuperMicro SYS-E300-9A server acting as SUT and equipped with one Intel
-Atom C3858 processor (12 MB Cache, 2.00 GHz, 12 cores). 3n-dnv physical
-topology is shown below.
-
-.. only:: latex
-
- .. raw:: latex
-
- \begin{figure}[H]
- \centering
- \graphicspath{{../_tmp/src/introduction/}}
- \includegraphics[width=0.90\textwidth]{testbed-3n-dnv}
- \label{fig:testbed-3n-dnv}
- \end{figure}
-
-.. only:: html
-
- .. figure:: testbed-3n-dnv.svg
- :alt: testbed-3n-dnv
- :align: center
-
-SUT1 and SUT2 NICs:
-
-#. NIC-1: x553 2p10GE fiber Intel.
-#. NIC-2: x553 2p10GE copper Intel.
-
-TG NICs:
-
-#. NIC-1: x710-DA4 4p10GE Intel.
-
.. _physical_testbeds_3n_alt:
3-Node ARM Altra (3n-alt)