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author | Peter Mikus <pmikus@cisco.com> | 2020-01-15 13:12:48 +0000 |
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committer | Peter Mikus <pmikus@cisco.com> | 2020-01-15 13:15:32 +0000 |
commit | c5e84fbee876a45d3495cde6f4e2d8140cacbe5a (patch) | |
tree | b73fc4b82dc459a8437ac84731e321d5ffc3c447 /docs/report/introduction/physical_testbeds.rst | |
parent | 39c81e3674295df82172ac8df1fe3c1184b1d896 (diff) |
Docs: Update report sections
Signed-off-by: Peter Mikus <pmikus@cisco.com>
Change-Id: Ib6e9ac003c1d91673984c52baf2f3eec30c9d21d
Diffstat (limited to 'docs/report/introduction/physical_testbeds.rst')
-rw-r--r-- | docs/report/introduction/physical_testbeds.rst | 51 |
1 files changed, 50 insertions, 1 deletions
diff --git a/docs/report/introduction/physical_testbeds.rst b/docs/report/introduction/physical_testbeds.rst index 9babb5fb1f..8860638d43 100644 --- a/docs/report/introduction/physical_testbeds.rst +++ b/docs/report/introduction/physical_testbeds.rst @@ -26,7 +26,8 @@ Two physical server topology types are used: Current FD.io production testbeds are built with SUT servers based on the following processor architectures: -- Intel Xeon: Skylake Platinum 8180 and Haswell-SP E5-2699v3. +- Intel Xeon: Skylake Platinum 8180, Haswell-SP E5-2699v3, + Cascadelake Platinum 8280, Cascadelake 6252N. - Intel Atom: Denverton C3858. - ARM: TaiShan 2280, hip07-d05. @@ -40,6 +41,54 @@ https://git.fd.io/csit/tree/docs/lab/testbed_specifications.md. Following is the description of existing production testbeds. +2-Node Xeon Cascadelake (2n-clx) +-------------------------------- + +Three 2n-clx testbeds are in operation in FD.io labs. Each 2n-clx testbed +is built with two SuperMicro SYS-7049GP-TRT servers, SUTs are equipped with two +Intel Xeon Gold 6252N processors (35.75 MB Cache, 2.30 GHz, 24 cores). +TGs are equiped with Intel Xeon Cascadelake Platinum 8280 processors (38.5 MB +Cache, 2.70 GHz, 28 cores). 2n-clx physical topology is shown below. + +.. only:: latex + + .. raw:: latex + + \begin{figure}[H] + \centering + \graphicspath{{../_tmp/src/introduction/}} + \includegraphics[width=0.90\textwidth]{testbed-2n-clx} + \label{fig:testbed-2n-clx} + \end{figure} + +.. only:: html + + .. figure:: testbed-2n-clx.svg + :alt: testbed-2n-clx + :align: center + +SUT servers are populated with the following NIC models: + +#. NIC-1: x710-DA4 4p10GE Intel. +#. NIC-2: xxv710-DA2 2p25GE Intel. +#. NIC-3: mcx556a-edat ConnectX5 2p100GE Mellanox. (Only testbed t27, t28) +#. NIC-4: empty, future expansion. +#. NIC-5: empty, future expansion. +#. NIC-6: empty, future expansion. + +TG servers run T-Rex application and are populated with the following +NIC models: + +#. NIC-1: x710-DA4 4p10GE Intel. +#. NIC-2: xxv710-DA2 2p25GE Intel. +#. NIC-3: mcx556a-edat ConnectX5 2p100GE Mellanox. (Only testbed t27, t28) +#. NIC-4: empty, future expansion. +#. NIC-5: empty, future expansion. +#. NIC-6: x710-DA4 4p10GE Intel. (For self-tests.) + +All Intel Xeon Cascadelake servers run with Intel Hyper-Threading enabled, +doubling the number of logical cores exposed to Linux. + 2-Node Xeon Skylake (2n-skx) ---------------------------- |