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authorJuraj Linkeš <juraj.linkes@pantheon.tech>2022-06-30 14:20:43 +0200
committerPeter Mikus <peter.mikus@protonmail.ch>2022-07-01 07:06:53 +0000
commitbf0fa247e2e95c14bc76dae43a0df26be410d931 (patch)
tree1c8dfd770ff8bb1c9cc461d2221e79afa5bf24cc /docs/report/introduction/physical_testbeds.rst
parentb9dd086436d08c4afd6651fdb46a29473a3db072 (diff)
Report: add 3n-alt static content
Also unify the order of testbeds in documents where 3n-alt appears. Change-Id: I571dc1a2f87f45c4039080b28cfbeeb09d8d990e Signed-off-by: Juraj Linkeš <juraj.linkes@pantheon.tech>
Diffstat (limited to 'docs/report/introduction/physical_testbeds.rst')
-rw-r--r--docs/report/introduction/physical_testbeds.rst38
1 files changed, 38 insertions, 0 deletions
diff --git a/docs/report/introduction/physical_testbeds.rst b/docs/report/introduction/physical_testbeds.rst
index cfd43d0653..30a4698f8b 100644
--- a/docs/report/introduction/physical_testbeds.rst
+++ b/docs/report/introduction/physical_testbeds.rst
@@ -402,6 +402,44 @@ TG NICs:
#. NIC-1: x710-DA4 4p10GE Intel.
+.. _physical_testbeds_3n_alt:
+
+3-Node ARM Altra (3n-alt)
+---------------------------
+
+One 3n-tsh testbed is built with: i) one SuperMicro SYS-740GP-TNRT
+server acting as TG and equipped with two Intel Xeon Icelake Platinum
+8358 processors (80 MB Cache, 2.60 GHz, 32 cores), and ii) one Ampere
+Altra server acting as SUT and equipped with two Q80-30 processors
+(80* ARM Neoverse N1). 3n-alt physical topology is shown below.
+
+.. only:: latex
+
+ .. raw:: latex
+
+ \begin{figure}[H]
+ \centering
+ \graphicspath{{../_tmp/src/introduction/}}
+ \includegraphics[width=0.90\textwidth]{testbed-3n-alt}
+ \label{fig:testbed-3n-alt}
+ \end{figure}
+
+.. only:: html
+
+ .. figure:: testbed-3n-alt.svg
+ :alt: testbed-3n-alt
+ :align: center
+
+SUT1 and SUT2 NICs:
+
+#. NIC-1: xl710-QDA2-2p40GE Intel.
+
+TG NICs:
+
+#. NIC-1: xxv710-DA2-2p25GE Intel.
+#. NIC-2: e810-XXVDA4-4p25GE Intel.
+#. NIC-3: e810-2CQDA2-2p100GE Intel.
+
3-Node ARM TaiShan (3n-tsh)
---------------------------