diff options
| author |   Tibor Frank <tifrank@cisco.com> | 2020-01-22 15:27:29 +0100 |
|---|---|---|
| committer | Tibor Frank <tifrank@cisco.com> | 2020-01-23 09:35:42 +0100 |
| commit | 25a8fe0aa594ca010b7f1aad449a2af2b6625bd7 (patch) | |
| tree | 9a53afbae053e1cf0f77f7a78819e4edffd28fd2 /docs/report/introduction/test_environment_intro.rst | |
| parent | 774d8a344d8c2610199aea5758e81b29535fc1f8 (diff) | |
Report: Add diagrams for testbeds
- Diagrams for testbeds:
- 3n-dnv
- 3n-tsh
- 2n-clx
- Replace s/Cascadelake/Cascade Lake
Change-Id: I77e7659a0aba4766a28577f940b7e44e60cbd82d
Signed-off-by: Tibor Frank <tifrank@cisco.com>
Diffstat (limited to 'docs/report/introduction/test_environment_intro.rst')
| -rw-r--r-- | docs/report/introduction/test_environment_intro.rst | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/docs/report/introduction/test_environment_intro.rst b/docs/report/introduction/test_environment_intro.rst index b02520b99d..0d35acee72 100644 --- a/docs/report/introduction/test_environment_intro.rst +++ b/docs/report/introduction/test_environment_intro.rst @@ -15,7 +15,7 @@ topology types are used: server as TG both connected in ring topology. Tested SUT servers are based on a range of processors including Intel -Xeon Haswell-SP, Intel Xeon Skylake-SP, Intel Xeon Cascadelake-SP, Arm, Intel +Xeon Haswell-SP, Intel Xeon Skylake-SP, Intel Xeon Cascade Lake-SP, Arm, Intel Atom. More detailed description is provided in :ref:`tested_physical_topologies`. Tested logical topologies are described in :ref:`tested_logical_topologies`. @@ -25,7 +25,7 @@ Server Specifications Complete technical specifications of compute servers used in CSIT physical testbeds are maintained in FD.io CSIT repository: -`FD.io CSIT testbeds - Xeon Cascadelake`_, +`FD.io CSIT testbeds - Xeon Cascade Lake`_, `FD.io CSIT testbeds - Xeon Skylake, Arm, Atom`_ and `FD.io CSIT Testbeds - Xeon Haswell`_. |