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authorTibor Frank <tifrank@cisco.com>2019-08-19 15:25:47 +0200
committerTibor Frank <tifrank@cisco.com>2019-08-26 07:23:06 +0000
commit39d8a85dd7bcec88318469308c8ce576aae7dfb1 (patch)
tree6a791903e3608cfe04724e8e01b6c9948a9ba708 /docs/report/vpp_performance_tests/packet_latency_graphs/container_memif.rst
parent426ddf0d4bc727a8cd9522980ab96309d45af0f6 (diff)
Report: Select tests by name, specifications
Change-Id: Ibcc5e67d49fba9c02b07af462a74d2a062412979 Signed-off-by: Tibor Frank <tifrank@cisco.com> (cherry picked from commit 33cfe1217cb2d6bc9655b01f200b0ec8d5ccb466)
Diffstat (limited to 'docs/report/vpp_performance_tests/packet_latency_graphs/container_memif.rst')
-rw-r--r--docs/report/vpp_performance_tests/packet_latency_graphs/container_memif.rst10
1 files changed, 2 insertions, 8 deletions
diff --git a/docs/report/vpp_performance_tests/packet_latency_graphs/container_memif.rst b/docs/report/vpp_performance_tests/packet_latency_graphs/container_memif.rst
index 0ffeef5546..3c3fceb7dd 100644
--- a/docs/report/vpp_performance_tests/packet_latency_graphs/container_memif.rst
+++ b/docs/report/vpp_performance_tests/packet_latency_graphs/container_memif.rst
@@ -13,15 +13,9 @@ VPP worker thread(s), a.k.a. VPP data plane thread(s), and their
physical CPU core(s) placement.
CSIT source code for the test cases used for plots can be found in
-`CSIT git repository <https://git.fd.io/csit/tree/tests/vpp/perf/container_memif?h=rls1901>`_.
+`CSIT git repository <https://git.fd.io/csit/tree/tests/vpp/perf/container_memif?h=rls1908>`_.
.. toctree::
- container_memif-3n-hsw-x520
- container_memif-3n-hsw-x710
- container_memif-3n-hsw-xl710
- container_memif-3n-skx-x710
- container_memif-2n-skx-x710
-
-..
container_memif-2n-skx-xxv710
+ container_memif-3n-skx-xxv710