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| author |   Tibor Frank <tifrank@cisco.com> | 2020-01-09 15:02:10 +0100 |
|---|---|---|
| committer | Tibor Frank <tifrank@cisco.com> | 2020-01-10 07:50:26 +0000 |
| commit | 80e558550b0f076857618c4451987fb60ced19b9 (patch) | |
| tree | 78a2fe2dcd9e59405449e5493f5a16d4803cfa24 /docs/report/vpp_performance_tests/packet_latency_graphs/l2.rst | |
| parent | a08fc340f548a4b223c7c139b4fe59531cf7c694 (diff) | |
Report: Add 2n-clx
Change-Id: I34dc11c28d21f0b9fed87d76942fe8b8cdd86c88
Signed-off-by: Tibor Frank <tifrank@cisco.com>
Diffstat (limited to 'docs/report/vpp_performance_tests/packet_latency_graphs/l2.rst')
| -rw-r--r-- | docs/report/vpp_performance_tests/packet_latency_graphs/l2.rst | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/docs/report/vpp_performance_tests/packet_latency_graphs/l2.rst b/docs/report/vpp_performance_tests/packet_latency_graphs/l2.rst index 9643740888..b1a87deadb 100644 --- a/docs/report/vpp_performance_tests/packet_latency_graphs/l2.rst +++ b/docs/report/vpp_performance_tests/packet_latency_graphs/l2.rst @@ -13,7 +13,7 @@ VPP worker thread(s), a.k.a. VPP data plane thread(s), and their physical CPU core(s) placement. CSIT source code for the test cases used for plots can be found in -`CSIT git repository <https://git.fd.io/csit/tree/tests/vpp/perf/l2?h=rls1908>`_. +`CSIT git repository <https://git.fd.io/csit/tree/tests/vpp/perf/l2?h=rls2001>`_. .. toctree:: @@ -21,5 +21,7 @@ CSIT source code for the test cases used for plots can be found in l2-2n-skx-x710 l2-3n-skx-xxv710 l2-3n-skx-x710 + l2-2n-clx-xxv710 + l2-2n-clx-x710 l2-3n-hsw-xl710 l2-3n-tsh-x520 |