diff options
author | Tibor Frank <tifrank@cisco.com> | 2018-11-05 15:01:37 +0100 |
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committer | Tibor Frank <tifrank@cisco.com> | 2018-11-05 15:01:37 +0100 |
commit | b641b5bf12a0d1b63ac9afb7c89133297d3b63fe (patch) | |
tree | 88342914639827399e40c68bf6c029f9e53cea3b /docs/report/vpp_performance_tests/packet_latency_graphs | |
parent | 312e541e0cc53a10429c40b41ad7f22ae4b8adc2 (diff) |
CSIT-1342: Edit the static content for CSIT-1810 report
Change-Id: I44abd4ad646813cc70e9fa2b46b51ee7613dc501
Signed-off-by: Tibor Frank <tifrank@cisco.com>
Diffstat (limited to 'docs/report/vpp_performance_tests/packet_latency_graphs')
11 files changed, 44 insertions, 4 deletions
diff --git a/docs/report/vpp_performance_tests/packet_latency_graphs/container_memif.rst b/docs/report/vpp_performance_tests/packet_latency_graphs/container_memif.rst index 4c27c89b48..0199276303 100644 --- a/docs/report/vpp_performance_tests/packet_latency_graphs/container_memif.rst +++ b/docs/report/vpp_performance_tests/packet_latency_graphs/container_memif.rst @@ -40,6 +40,10 @@ physical CPU core(s) placement. CSIT source code for the test cases used for plots can be found in `CSIT git repository <https://git.fd.io/csit/tree/tests/vpp/perf/container_memif?h=rls1810>`_. +.. raw:: latex + + \clearpage + 3n-hsw-x520 ~~~~~~~~~~~ diff --git a/docs/report/vpp_performance_tests/packet_latency_graphs/container_orchestrated.rst b/docs/report/vpp_performance_tests/packet_latency_graphs/container_orchestrated.rst index d746c53674..f975f2ddd0 100644 --- a/docs/report/vpp_performance_tests/packet_latency_graphs/container_orchestrated.rst +++ b/docs/report/vpp_performance_tests/packet_latency_graphs/container_orchestrated.rst @@ -40,6 +40,10 @@ physical CPU core(s) placement. CSIT source code for the test cases used for plots can be found in `CSIT git repository <https://git.fd.io/csit/tree/tests/kubernetes/perf/container_memif?h=rls1810>`_. +.. raw:: latex + + \clearpage + 3n-hsw-x520 ~~~~~~~~~~~ diff --git a/docs/report/vpp_performance_tests/packet_latency_graphs/ip4.rst b/docs/report/vpp_performance_tests/packet_latency_graphs/ip4.rst index a88e007464..08907610a7 100644 --- a/docs/report/vpp_performance_tests/packet_latency_graphs/ip4.rst +++ b/docs/report/vpp_performance_tests/packet_latency_graphs/ip4.rst @@ -40,6 +40,10 @@ physical CPU core(s) placement. CSIT source code for the test cases used for plots can be found in `CSIT git repository <https://git.fd.io/csit/tree/tests/vpp/perf/ip4?h=rls1810>`_. +.. raw:: latex + + \clearpage + 3n-hsw-x520 ~~~~~~~~~~~ diff --git a/docs/report/vpp_performance_tests/packet_latency_graphs/ip4_tunnels.rst b/docs/report/vpp_performance_tests/packet_latency_graphs/ip4_tunnels.rst index db0cfd0852..27e83c4359 100644 --- a/docs/report/vpp_performance_tests/packet_latency_graphs/ip4_tunnels.rst +++ b/docs/report/vpp_performance_tests/packet_latency_graphs/ip4_tunnels.rst @@ -40,6 +40,10 @@ physical CPU core(s) placement. CSIT source code for the test cases used for plots can be found in `CSIT git repository <https://git.fd.io/csit/tree/tests/vpp/perf/ip4_tunnels?h=rls1810>`_. +.. raw:: latex + + \clearpage + 3n-hsw-x520 ~~~~~~~~~~~ diff --git a/docs/report/vpp_performance_tests/packet_latency_graphs/ip6.rst b/docs/report/vpp_performance_tests/packet_latency_graphs/ip6.rst index 5ba63dc9de..0ad3e342c6 100644 --- a/docs/report/vpp_performance_tests/packet_latency_graphs/ip6.rst +++ b/docs/report/vpp_performance_tests/packet_latency_graphs/ip6.rst @@ -40,6 +40,10 @@ physical CPU core(s) placement. CSIT source code for the test cases used for plots can be found in `CSIT git repository <https://git.fd.io/csit/tree/tests/vpp/perf/ip6?h=rls1810>`_. +.. raw:: latex + + \clearpage + 3n-hsw-x520 ~~~~~~~~~~~ diff --git a/docs/report/vpp_performance_tests/packet_latency_graphs/ip6_tunnels.rst b/docs/report/vpp_performance_tests/packet_latency_graphs/ip6_tunnels.rst index a193e7913a..050ace5069 100644 --- a/docs/report/vpp_performance_tests/packet_latency_graphs/ip6_tunnels.rst +++ b/docs/report/vpp_performance_tests/packet_latency_graphs/ip6_tunnels.rst @@ -40,6 +40,10 @@ physical CPU core(s) placement. CSIT source code for the test cases used for plots can be found in `CSIT git repository <https://git.fd.io/csit/tree/tests/vpp/perf/ip6_tunnels?h=rls1810>`_. +.. raw:: latex + + \clearpage + 3n-hsw-x520 ~~~~~~~~~~~ diff --git a/docs/report/vpp_performance_tests/packet_latency_graphs/ipsec.rst b/docs/report/vpp_performance_tests/packet_latency_graphs/ipsec.rst index 3978a8c136..30363a73d2 100644 --- a/docs/report/vpp_performance_tests/packet_latency_graphs/ipsec.rst +++ b/docs/report/vpp_performance_tests/packet_latency_graphs/ipsec.rst @@ -43,6 +43,10 @@ placement. CSIT source code for the test cases used for plots can be found in `CSIT git repository <https://git.fd.io/csit/tree/tests/vpp/perf/crypto?h=rls1810>`_. +.. raw:: latex + + \clearpage + 3n-hsw-xl710 ~~~~~~~~~~~~ diff --git a/docs/report/vpp_performance_tests/packet_latency_graphs/l2.rst b/docs/report/vpp_performance_tests/packet_latency_graphs/l2.rst index ca30ee470f..db767807f4 100644 --- a/docs/report/vpp_performance_tests/packet_latency_graphs/l2.rst +++ b/docs/report/vpp_performance_tests/packet_latency_graphs/l2.rst @@ -1,8 +1,4 @@ -.. raw:: latex - - \clearpage - .. raw:: html <script type="text/javascript"> @@ -40,6 +36,10 @@ physical CPU core(s) placement. CSIT source code for the test cases used for plots can be found in `CSIT git repository <https://git.fd.io/csit/tree/tests/vpp/perf/l2?h=rls1810>`_. +.. raw:: latex + + \clearpage + 3n-hsw-x520 ~~~~~~~~~~~ diff --git a/docs/report/vpp_performance_tests/packet_latency_graphs/srv6.rst b/docs/report/vpp_performance_tests/packet_latency_graphs/srv6.rst index a070b8130a..3fa202bfd1 100644 --- a/docs/report/vpp_performance_tests/packet_latency_graphs/srv6.rst +++ b/docs/report/vpp_performance_tests/packet_latency_graphs/srv6.rst @@ -40,6 +40,10 @@ physical CPU core(s) placement. CSIT source code for the test cases used for plots can be found in `CSIT git repository <https://git.fd.io/csit/tree/tests/vpp/perf/srv6?h=rls1810>`_. +.. raw:: latex + + \clearpage + 3n-hsw-x520 ~~~~~~~~~~~ diff --git a/docs/report/vpp_performance_tests/packet_latency_graphs/vm_vhost.rst b/docs/report/vpp_performance_tests/packet_latency_graphs/vm_vhost.rst index 1efd705e63..11072ccceb 100644 --- a/docs/report/vpp_performance_tests/packet_latency_graphs/vm_vhost.rst +++ b/docs/report/vpp_performance_tests/packet_latency_graphs/vm_vhost.rst @@ -41,6 +41,10 @@ placement. CSIT source code for the test cases used for plots can be found in `CSIT git repository <https://git.fd.io/csit/tree/tests/vpp/perf/vm_vhost?h=rls1810>`_. +.. raw:: latex + + \clearpage + 3n-hsw-x520 ~~~~~~~~~~~ diff --git a/docs/report/vpp_performance_tests/packet_latency_graphs/vts.rst b/docs/report/vpp_performance_tests/packet_latency_graphs/vts.rst index cc114bb8dc..26d1e6b201 100644 --- a/docs/report/vpp_performance_tests/packet_latency_graphs/vts.rst +++ b/docs/report/vpp_performance_tests/packet_latency_graphs/vts.rst @@ -41,6 +41,10 @@ placement. CSIT source code for the test cases used for plots can be found in `CSIT git repository <https://git.fd.io/csit/tree/tests/vpp/perf/vts?h=rls1810>`_. +.. raw:: latex + + \clearpage + 3n-hsw-x520 ~~~~~~~~~~~ |