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author | Tibor Frank <tifrank@cisco.com> | 2020-10-05 14:50:31 +0200 |
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committer | Tibor Frank <tifrank@cisco.com> | 2020-10-05 15:25:36 +0200 |
commit | 881f1a4c12fe727274b15551b12c37b364dd32e2 (patch) | |
tree | 3ee0024c3371beccfdb09b4873caff3e912c2978 /docs/report/vpp_performance_tests/throughput_speedup_multi_core/ip4_tunnels.rst | |
parent | 92fe102505f8d10a5133313a976f8a07da1192d1 (diff) |
Report: Add data
- DNV VPP tests
- 3n-tsh MRR 2005-5
- MRR Comparisons for skx, hsw and clx
Change-Id: Ibb73e0f8234d2eb27b6a386675492efc9f050247
Signed-off-by: Tibor Frank <tifrank@cisco.com>
Diffstat (limited to 'docs/report/vpp_performance_tests/throughput_speedup_multi_core/ip4_tunnels.rst')
-rw-r--r-- | docs/report/vpp_performance_tests/throughput_speedup_multi_core/ip4_tunnels.rst | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/docs/report/vpp_performance_tests/throughput_speedup_multi_core/ip4_tunnels.rst b/docs/report/vpp_performance_tests/throughput_speedup_multi_core/ip4_tunnels.rst index 4c444a9155..1cf1faac10 100644 --- a/docs/report/vpp_performance_tests/throughput_speedup_multi_core/ip4_tunnels.rst +++ b/docs/report/vpp_performance_tests/throughput_speedup_multi_core/ip4_tunnels.rst @@ -15,13 +15,11 @@ running in multiple configurations of VPP worker thread(s), a.k.a. VPP data plane thread(s), and their physical CPU core(s) placement. CSIT source code for the test cases used for plots can be found in -`CSIT git repository <https://git.fd.io/csit/tree/tests/vpp/perf/ip4_tunnels?h=rls2001>`_. +`CSIT git repository <https://git.fd.io/csit/tree/tests/vpp/perf/ip4_tunnels?h=rls2009>`_. .. toctree:: ip4_tunnels-3n-skx-xxv710 ip4_tunnels-3n-hsw-xl710 ip4_tunnels-3n-tsh-x520 - -.. ip4_tunnels-3n-dnv-x553 |