diff options
70 files changed, 2543 insertions, 9617 deletions
diff --git a/docs/report/csit_framework_documentation/index.rst b/docs/report/csit_framework_documentation/index.rst index 82031e38ae..44db73de4b 100644 --- a/docs/report/csit_framework_documentation/index.rst +++ b/docs/report/csit_framework_documentation/index.rst @@ -5,5 +5,4 @@ CSIT Framework csit_design csit_test_naming - pal_lld csit_tag_description diff --git a/docs/report/csit_framework_documentation/pal_func_diagram.svg b/docs/report/csit_framework_documentation/pal_func_diagram.svg deleted file mode 100644 index 14f59605f9..0000000000 --- a/docs/report/csit_framework_documentation/pal_func_diagram.svg +++ /dev/null @@ -1,1413 +0,0 @@ -<?xml version="1.0" encoding="UTF-8"?> - -<svg version="1.2" baseProfile="tiny" width="210.06mm" height="270.76mm" viewBox="0 0 21006 27076" preserveAspectRatio="xMidYMid" fill-rule="evenodd" stroke-width="28.222" stroke-linejoin="round" xmlns="http://www.w3.org/2000/svg" xmlns:ooo="http://xml.openoffice.org/svg/export" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:presentation="http://sun.com/xmlns/staroffice/presentation" xmlns:smil="http://www.w3.org/2001/SMIL20/" xmlns:anim="urn:oasis:names:tc:opendocument:xmlns:animation:1.0" xml:space="preserve"> - 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\ No newline at end of file diff --git a/docs/report/csit_framework_documentation/pal_lld.rst b/docs/report/csit_framework_documentation/pal_lld.rst deleted file mode 100644 index ddd4de0994..0000000000 --- a/docs/report/csit_framework_documentation/pal_lld.rst +++ /dev/null @@ -1 +0,0 @@ -.. include:: ../../../../../../resources/tools/presentation/doc/pal_lld.rst diff --git a/docs/report/dpdk_performance_tests/test_environment.rst b/docs/report/dpdk_performance_tests/test_environment.rst index 95bbd9d621..1c86c5a29e 100644 --- a/docs/report/dpdk_performance_tests/test_environment.rst +++ b/docs/report/dpdk_performance_tests/test_environment.rst @@ -5,9 +5,9 @@ .. _dpdk_test_environment: -.. include:: ../introduction/test_environment_intro.rst +.. include:: ../introduction/environment/intro.rst -.. include:: ../introduction/test_environment_sut_conf_1.rst +.. include:: ../introduction/environment/sut_conf_1.rst DUT Settings - DPDK @@ -47,20 +47,30 @@ Startup command template: l3fwd -v -l $$CORE_LIST -w $$INT1 -w $$INT2 --master-lcore 0 --in-memory -- --parse-ptype --eth-dest="0,${adj_mac0}" --eth-dest="1,${adj_mac1}" --config="${port_config}" [--enable-jumbo] -P -L -p 0x3 -.. include:: ../introduction/test_environment_tg.rst +.. include:: ../introduction/environment/tg.rst -.. include:: ../introduction/test_environment_pre_test_server_calib.rst +.. include:: ../introduction/environment/pre_test_server_calib.rst -.. include:: ../introduction/test_environment_sut_calib_icx.rst +.. include:: ../introduction/environment/sut_calib_icx.rst +.. include:: ../introduction/environment/sut_meltspec_icx.rst -.. include:: ../introduction/test_environment_sut_calib_clx.rst +.. include:: ../introduction/environment/sut_calib_clx.rst +.. include:: ../introduction/environment/sut_meltspec_clx.rst -.. include:: ../introduction/test_environment_sut_calib_hsw.rst +.. include:: ../introduction/environment/sut_calib_zn2.rst +.. include:: ../introduction/environment/sut_meltspec_zn2.rst -.. include:: ../introduction/test_environment_sut_calib_dnv.rst +.. include:: ../introduction/environment/sut_calib_dnv.rst +.. include:: ../introduction/environment/sut_meltspec_dnv.rst -.. include:: ../introduction/test_environment_sut_calib_alt.rst +.. include:: ../introduction/environment/sut_calib_snr.rst +.. include:: ../introduction/environment/sut_meltspec_snr.rst -.. include:: ../introduction/test_environment_sut_calib_tsh.rst +.. include:: ../introduction/environment/sut_calib_alt.rst +.. include:: ../introduction/environment/sut_meltspec_alt.rst -.. include:: ../introduction/test_environment_sut_calib_tx2.rst +.. include:: ../introduction/environment/sut_calib_tsh.rst +.. include:: ../introduction/environment/sut_meltspec_tsh.rst + +.. include:: ../introduction/environment/sut_calib_tx2.rst +.. include:: ../introduction/environment/sut_meltspec_tx2.rst diff --git a/docs/report/index.html.template b/docs/report/index.html.template index 1f4299e6c7..e4ea7c8787 100644 --- a/docs/report/index.html.template +++ b/docs/report/index.html.template @@ -10,7 +10,7 @@ CSIT-2210 introduction/test_scenarios_overview introduction/physical_testbeds introduction/methodology - introduction/documentation/index + introduction/documentation .. toctree:: :maxdepth: 2 @@ -93,11 +93,4 @@ CSIT-2210 csit_framework_documentation/csit_design csit_framework_documentation/csit_test_naming - csit_framework_documentation/pal_lld csit_framework_documentation/csit_tag_description - -.. toctree:: - :maxdepth: 2 - :caption: Statistics - - stats/durations diff --git a/docs/report/introduction/documentation/documentation.rst b/docs/report/introduction/documentation.rst index 3635516924..3635516924 100644 --- a/docs/report/introduction/documentation/documentation.rst +++ b/docs/report/introduction/documentation.rst diff --git a/docs/report/introduction/documentation/index.rst b/docs/report/introduction/documentation/index.rst deleted file mode 100644 index 42afab7506..0000000000 --- a/docs/report/introduction/documentation/index.rst +++ /dev/null @@ -1,12 +0,0 @@ - -.. raw:: latex - - \clearpage - -Documentation -============= - -.. toctree:: - - documentation - diff --git a/docs/report/introduction/test_environment_changes_tg.rst b/docs/report/introduction/environment/changes_tg.rst index d21e43e04a..d21e43e04a 100644 --- a/docs/report/introduction/test_environment_changes_tg.rst +++ b/docs/report/introduction/environment/changes_tg.rst diff --git a/docs/report/introduction/test_environment_changes_vpp.rst b/docs/report/introduction/environment/changes_vpp.rst index 5f3d3bf3e9..b720766b48 100644 --- a/docs/report/introduction/test_environment_changes_vpp.rst +++ b/docs/report/introduction/environment/changes_vpp.rst @@ -17,10 +17,8 @@ topology types are used: - **2-Node Topology**: Consisting of one server acting as SUTs and one server as TG both connected in ring topology. -Tested SUT servers are based on a range of processors including -Intel Xeon Icelake-SP, Intel Xeon Skylake-SP, Intel Xeon Cascade Lake-SP, Arm, -Intel Atom. More detailed description is provided in -:ref:`tested_physical_topologies`. Tested logical topologies are +Tested SUT servers are based on a range of processors. More detailed description +is provided in :ref:`tested_physical_topologies`. Tested logical topologies are described in :ref:`tested_logical_topologies`. Server Specifications @@ -29,4 +27,7 @@ Server Specifications Complete technical specifications of compute servers used in CSIT physical testbeds are maintained in FD.io CSIT repository: `FD.io CSIT testbeds - Xeon Cascade Lake`_, -`FD.io CSIT testbeds - Xeon Skylake, Arm, Atom`_. +`FD.io CSIT testbeds - Xeon Ice Lake`_, +`FD.io CSIT testbeds - EPYC Zen2`_, +`FD.io CSIT testbeds - Atom Denverton`_, +`FD.io CSIT testbeds - Atom Snowridge`_. diff --git a/docs/report/introduction/test_environment_intro.rst b/docs/report/introduction/environment/intro.rst index 10ba083a12..1cba24a2bb 100644 --- a/docs/report/introduction/test_environment_intro.rst +++ b/docs/report/introduction/environment/intro.rst @@ -29,18 +29,11 @@ versions and SW source code, within a specific CSIT version. Components included in the CSIT environment versioning include: - **HW** Server hardware firmware and BIOS (motherboard, processsor, - NIC(s), accelerator card(s)), tracked in CSIT branch in - :file:`./docs/lab/<server_platform_name>_hw_bios_cfg.md`, e.g. `Xeon - Skylake servers - <https://git.fd.io/csit/tree/docs/lab/testbeds_sm_skx_hw_bios_cfg.md#n556>`_. + NIC(s), accelerator card(s)), tracked in CSIT branch. - **Linux** Server Linux OS version and configuration, tracked in CSIT - Reports in `SUT Settings - <https://s3-docs.fd.io/csit/master/report/vpp_performance_tests/test_environment.html#sut-settings-linux>`_ - and `Pre-Test Server Calibration - <https://s3-docs.fd.io/csit/master/report/vpp_performance_tests/test_environment.html#id21>`_. + Reports. - **TRex** TRex Traffic Generator version, drivers and configuration - tracked in `TG Settings - <https://s3-docs.fd.io/csit/master/report/vpp_performance_tests/test_environment.html#tg-settings-trex>`_. + tracked in TG Settings. - **CSIT** CSIT framework code tracked in CSIT release branches. Following is the list of CSIT versions to date: @@ -123,4 +116,17 @@ Following is the list of CSIT versions to date: - Mellanox 556A series firmware upgrade based on DPDK compatibility matrix. - Intel IceLake all core turbo frequency turned off. Current base frequency - is 2.6GHz.
\ No newline at end of file + is 2.6GHz. + +- Ver. 11 associated with CSIT rls2210 branch (`HW + <https://git.fd.io/csit/tree/docs/lab?h=rls2210>`_, `Linux + <https://s3-docs.fd.io/csit/rls2210/report/vpp_performance_tests/test_environment.html#sut-settings-linux>`_, + `TRex + <https://s3-docs.fd.io/csit/rls2210/report/vpp_performance_tests/test_environment.html#tg-settings-trex>`_, + `CSIT <https://git.fd.io/csit/tree/?h=rls2210>`_). + + - Intel NIC 700/800 series firmware upgrade based on DPDK compatibility + matrix. + - Mellanox 556A series firmware upgrade based on DPDK compatibility + matrix. + - Ubuntu 22.04 LTS upgrade. diff --git a/docs/report/introduction/test_environment_pre_test_server_calib.rst b/docs/report/introduction/environment/pre_test_server_calib.rst index 325c61b212..325c61b212 100644 --- a/docs/report/introduction/test_environment_pre_test_server_calib.rst +++ b/docs/report/introduction/environment/pre_test_server_calib.rst diff --git a/docs/report/introduction/environment/sut_calib_alt.rst b/docs/report/introduction/environment/sut_calib_alt.rst new file mode 100644 index 0000000000..fb799b9a9b --- /dev/null +++ b/docs/report/introduction/environment/sut_calib_alt.rst @@ -0,0 +1,22 @@ +Altra +~~~~~ + +Following sections include sample calibration data measured on server running in +one of the Altra testbeds. + + +Linux cmdline +^^^^^^^^^^^^^ + +:: + + $ cat /proc/cmdline + BOOT_IMAGE=/boot/vmlinuz-5.15.0-46-generic root=UUID=7d1d0e77-4df0-43df-9619-a99db29ffb83 ro audit=0 default_hugepagesz=2M hugepagesz=1G hugepages=32 hugepagesz=2M hugepages=32768 iommu.passthrough=1 isolcpus=1-10,29-38 nmi_watchdog=0 nohz_full=1-10,29-38 nosoftlockup processor.max_cstate=1 rcu_nocbs=1-10,29-38 console=ttyAMA0,115200n8 quiet + +Linux uname +^^^^^^^^^^^ + +:: + + $ uname -a + Linux 5.15.0-46-generic #49-Ubuntu SMP Thu Aug 4 18:08:11 UTC 2022 aarch64 aarch64 aarch64 GNU/Linux diff --git a/docs/report/introduction/environment/sut_calib_clx.rst b/docs/report/introduction/environment/sut_calib_clx.rst new file mode 100644 index 0000000000..af4ee098b1 --- /dev/null +++ b/docs/report/introduction/environment/sut_calib_clx.rst @@ -0,0 +1,65 @@ +Cascade Lake +~~~~~~~~~~~~ + +Following sections include sample calibration data measured on server running in +one of the Intel Xeon Skylake testbeds. + +Linux cmdline +^^^^^^^^^^^^^ + +:: + + $ cat /proc/cmdline + BOOT_IMAGE=/boot/vmlinuz-5.15.0-46-generic root=UUID=2d6f4d44-76b1-4343-bc73-c066a3e95b32 ro audit=0 default_hugepagesz=2M hugepagesz=1G hugepages=32 hugepagesz=2M hugepages=32768 hpet=disable intel_idle.max_cstate=1 intel_iommu=on intel_pstate=disable iommu=pt isolcpus=1-23,25-47,49-71,73-95 mce=off nmi_watchdog=0 nohz_full=1-23,25-47,49-71,73-95 nosoftlockup numa_balancing=disable processor.max_cstate=1 rcu_nocbs=1-23,25-47,49-71,73-95 tsc=reliable console=ttyS0,115200n8 quiet + +Linux uname +^^^^^^^^^^^ + +:: + + $ uname -a + Linux 5.15.0-46-generic #49-Ubuntu SMP Thu Aug 4 18:03:25 UTC 2022 x86_64 x86_64 x86_64 GNU/Linux + +System-level Core Jitter +^^^^^^^^^^^^^^^^^^^^^^^^ + +:: + + $ sudo taskset -c 3 /home/testuser/pma_tools/jitter/jitter -i 30 + Linux Jitter testing program version 1.9 + Iterations=20 + The pragram will execute a dummy function 80000 times + Display is updated every 20000 displayUpdate intervals + Thread affinity will be set to core_id:7 + Timings are in CPU Core cycles + Inst_Min: Minimum Excution time during the display update interval(default is ~1 second) + Inst_Max: Maximum Excution time during the display update interval(default is ~1 second) + Inst_jitter: Jitter in the Excution time during rhe display update interval. This is the value of interest + last_Exec: The Excution time of last iteration just before the display update + Abs_Min: Absolute Minimum Excution time since the program started or statistics were reset + Abs_Max: Absolute Maximum Excution time since the program started or statistics were reset + tmp: Cumulative value calcualted by the dummy function + Interval: Time interval between the display updates in Core Cycles + Sample No: Sample number + + Inst_Min,Inst_Max,Inst_jitter,last_Exec,Abs_min,Abs_max,tmp,Interval,Sample No + 160026,167568,7542,160032,160026,167568,183238656,3204033176,1 + 160026,171174,11148,160028,160026,171174,3563847680,3204142488,2 + 160024,170002,9978,160032,160024,171174,2649489408,3204224288,3 + 160026,169124,9098,160032,160024,171174,1735131136,3204142126,4 + 160026,169096,9070,160030,160024,171174,820772864,3204069082,5 + 160026,168788,8762,160028,160024,171174,4201381888,3204056954,6 + 160024,169196,9172,160030,160024,171174,3287023616,3204364824,7 + 160026,168176,8150,160028,160024,171174,2372665344,3204073670,8 + 160026,169466,9440,160032,160024,171174,1458307072,3204068092,9 + 160026,168858,8832,160032,160024,171174,543948800,3204109862,10 + 160026,169418,9392,160028,160024,171174,3924557824,3204289508,11 + 160026,167776,7750,160032,160024,171174,3010199552,3204089538,12 + 160024,170538,10514,160032,160024,171174,2095841280,3204109170,13 + 160026,169320,9294,160034,160024,171174,1181483008,3204108772,14 + 160026,169976,9950,160034,160024,171174,267124736,3204259754,15 + 160026,166826,6800,160030,160024,171174,3647733760,3204058488,16 + 160026,168314,8288,160032,160024,171174,2733375488,3204110518,17 + 160026,170176,10150,160028,160024,171174,1819017216,3204283146,18 + 160024,168698,8674,160030,160024,171174,904658944,3204162904,19 + 160026,168234,8208,160034,160024,171174,4285267968,3204059562,20 diff --git a/docs/report/introduction/environment/sut_calib_dnv.rst b/docs/report/introduction/environment/sut_calib_dnv.rst new file mode 100644 index 0000000000..310d8df039 --- /dev/null +++ b/docs/report/introduction/environment/sut_calib_dnv.rst @@ -0,0 +1,67 @@ +Denverton +~~~~~~~~~ + +Following sections include sample calibration data measured on +server running in one of the Intel Atom Denverton testbeds. + + +Linux cmdline +^^^^^^^^^^^^^ + +:: + + $ cat /proc/cmdline + BOOT_IMAGE=/boot/vmlinuz-5.4.0-65-generic root=UUID=26ca7b0f-904a-462d-a1c6-98c420c29515 ro audit=0 hpet=disable intel_idle.max_cstate=1 intel_iommu=on intel_pstate=disable iommu=pt isolcpus=1-5 mce=off nmi_watchdog=0 nohz_full=1-5 nosoftlockup numa_balancing=disable processor.max_cstate=1 rcu_nocbs=1-5 tsc=reliable console=tty0 console=ttyS0,115200n8 + + +Linux uname +^^^^^^^^^^^ + +:: + + $ uname -a + Linux 5.4.0-65-generic #73-Ubuntu SMP Mon Jan 18 17:25:17 UTC 2021 x86_64 x86_64 x86_64 GNU/Linux + + +System-level Core Jitter +^^^^^^^^^^^^^^^^^^^^^^^^ + +:: + + $ sudo taskset -c 2 /home/testuser/pma_tools/jitter/jitter -c 2 -i 20 + Linux Jitter testing program version 1.9 + Iterations=20 + The pragram will execute a dummy function 80000 times + Display is updated every 20000 displayUpdate intervals + Thread affinity will be set to core_id:7 + Timings are in CPU Core cycles + Inst_Min: Minimum Excution time during the display update interval(default is ~1 second) + Inst_Max: Maximum Excution time during the display update interval(default is ~1 second) + Inst_jitter: Jitter in the Excution time during rhe display update interval. This is the value of interest + last_Exec: The Excution time of last iteration just before the display update + Abs_Min: Absolute Minimum Excution time since the program started or statistics were reset + Abs_Max: Absolute Maximum Excution time since the program started or statistics were reset + tmp: Cumulative value calcualted by the dummy function + Interval: Time interval between the display updates in Core Cycles + Sample No: Sample number + Inst_Min,Inst_Max,Inst_jitter,last_Exec,Abs_min,Abs_max,tmp,Interval,Sample No + 177008,217292,40284,177552,177008,217292,80543744,3555521762,1 + 167862,222370,54508,177552,167862,222370,191692800,3555482758,2 + 172576,251932,79356,177538,167862,251932,302841856,3556013278,3 + 177368,215300,37932,177552,167862,251932,413990912,3555428816,4 + 167914,215066,47152,177552,167862,251932,525139968,3555415700,5 + 177494,241748,64254,177552,167862,251932,636289024,3555835494,6 + 177038,210186,33148,177552,167862,251932,747438080,3555398164,7 + 170956,211022,40066,177552,167862,251932,858587136,3555435464,8 + 174130,237428,63298,177552,167862,251932,969736192,3555771752,9 + 174726,205252,30526,177552,167862,251932,1080885248,3555426516,10 + 177104,234502,57398,177554,167862,251932,1192034304,3555785760,11 + 175304,240416,65112,177550,167862,251932,1303183360,3555908234,12 + 166674,216176,49502,177552,166674,251932,1414332416,3555468016,13 + 177532,205792,28260,177552,166674,251932,1525481472,3555440968,14 + 177516,235032,57516,177550,166674,251932,1636630528,3555832414,15 + 177522,207292,29770,177552,166674,251932,1747779584,3555495058,16 + 177532,205174,27642,177552,166674,251932,1858928640,3555458754,17 + 177528,234230,56702,177552,166674,251932,1970077696,3555837046,18 + 177530,209364,31834,177552,166674,251932,2081226752,3555469590,19 + 177530,205002,27472,177552,166674,251932,2192375808,3555397840,20 diff --git a/docs/report/introduction/environment/sut_calib_icx.rst b/docs/report/introduction/environment/sut_calib_icx.rst new file mode 100644 index 0000000000..d9d725319c --- /dev/null +++ b/docs/report/introduction/environment/sut_calib_icx.rst @@ -0,0 +1,65 @@ +Ice Lake +~~~~~~~~ + +Following sections include sample calibration data measured on server running in +one of the Intel Xeon Ice Lake testbeds. + +Linux cmdline +^^^^^^^^^^^^^ + +:: + + $ cat /proc/cmdline + BOOT_IMAGE=/boot/vmlinuz-5.15.0-46-generic root=UUID=6ff26c8a-8c65-4025-a6e7-d97dee6025d0 ro audit=0 default_hugepagesz=2M hugepagesz=1G hugepages=32 hugepagesz=2M hugepages=32768 hpet=disable intel_idle.max_cstate=1 intel_iommu=on intel_pstate=disable iommu=pt isolcpus=1-31,33-63,65-95,97-127 mce=off nmi_watchdog=0 nohz_full=1-31,33-63,65-95,97-127 nosoftlockup numa_balancing=disable processor.max_cstate=1 rcu_nocbs=1-31,33-63,65-95,97-127 tsc=reliable console=ttyS0,115200n8 quiet + +Linux uname +^^^^^^^^^^^ + +:: + + $ uname -a + Linux 5.15.0-46-generic #49-Ubuntu SMP Thu Aug 4 18:03:25 UTC 2022 x86_64 x86_64 x86_64 GNU/Linux + +System-level Core Jitter +^^^^^^^^^^^^^^^^^^^^^^^^ + +:: + + $ sudo taskset -c 3 /home/testuser/pma_tools/jitter/jitter -i 30 + Linux Jitter testing program version 1.9 + Iterations=20 + The pragram will execute a dummy function 80000 times + Display is updated every 20000 displayUpdate intervals + Thread affinity will be set to core_id:7 + Timings are in CPU Core cycles + Inst_Min: Minimum Excution time during the display update interval(default is ~1 second) + Inst_Max: Maximum Excution time during the display update interval(default is ~1 second) + Inst_jitter: Jitter in the Excution time during rhe display update interval. This is the value of interest + last_Exec: The Excution time of last iteration just before the display update + Abs_Min: Absolute Minimum Excution time since the program started or statistics were reset + Abs_Max: Absolute Maximum Excution time since the program started or statistics were reset + tmp: Cumulative value calcualted by the dummy function + Interval: Time interval between the display updates in Core Cycles + Sample No: Sample number + + Inst_Min,Inst_Max,Inst_jitter,last_Exec,Abs_min,Abs_max,tmp,Interval,Sample No + 160022,167912,7890,160034,160022,167912,854327296,3203987030,1 + 160022,168114,8092,160042,160022,168114,4234936320,3204004240,2 + 160022,168386,8364,160040,160022,168386,3320578048,3204007496,3 + 160022,169432,9410,160028,160022,169432,2406219776,3204213462,4 + 160022,168050,8028,160040,160022,169432,1491861504,3203982428,5 + 160022,166384,6362,160040,160022,169432,577503232,3203969006,6 + 160022,168962,8940,160042,160022,169432,3958112256,3204002514,7 + 160020,169248,9228,160038,160020,169432,3043753984,3204208318,8 + 160022,168854,8832,160038,160020,169432,2129395712,3203987894,9 + 160022,166754,6732,160042,160020,169432,1215037440,3203984104,10 + 160022,168208,8186,160040,160020,169432,300679168,3203980640,11 + 160022,172450,12428,160040,160020,172450,3681288192,3204208216,12 + 160022,168244,8222,160042,160020,172450,2766929920,3204037074,13 + 160022,166894,6872,160040,160020,172450,1852571648,3203979376,14 + 160022,169068,9046,160038,160020,172450,938213376,3204009714,15 + 160020,168528,8508,160036,160020,172450,23855104,3204028382,16 + 160022,169458,9436,160042,160020,172450,3404464128,3204179220,17 + 160020,167056,7036,160040,160020,172450,2490105856,3203990218,18 + 160022,167038,7016,160038,160020,172450,1575747584,3203976712,19 + 160022,168610,8588,160040,160020,172450,661389312,3204025230,20 diff --git a/docs/report/introduction/environment/sut_calib_snr.rst b/docs/report/introduction/environment/sut_calib_snr.rst new file mode 100644 index 0000000000..fd4d17812a --- /dev/null +++ b/docs/report/introduction/environment/sut_calib_snr.rst @@ -0,0 +1,65 @@ +Snowridge +~~~~~~~~~ + +Following sections include sample calibration data measured on server running in +one of the Intel Atom Snowridge testbeds. + +Linux cmdline +^^^^^^^^^^^^^ + +:: + + $ cat /proc/cmdline + BOOT_IMAGE=/vmlinuz-5.15.0-46-generic root=/dev/mapper/ubuntu--vg-ubuntu--lv ro audit=0 default_hugepagesz=2M hugepagesz=1G hugepages=2 hugepagesz=2M hugepages=4096 hpet=disable intel_idle.max_cstate=1 intel_iommu=on intel_pstate=disable iommu=pt isolcpus=1-23 mce=off nmi_watchdog=0 nohz_full=1-23 nosoftlockup numa_balancing=disable processor.max_cstate=1 rcu_nocbs=1-23 tsc=reliable console=ttyS0,115200n8 quiet + +Linux uname +^^^^^^^^^^^ + +:: + + $ uname -a + Linux 5.15.0-46-generic #49-Ubuntu SMP Thu Aug 4 18:03:25 UTC 2022 x86_64 x86_64 x86_64 GNU/Linux + +System-level Core Jitter +^^^^^^^^^^^^^^^^^^^^^^^^ + +:: + + $ sudo taskset -c 2 /home/testuser/pma_tools/jitter/jitter -c 2 -i 20 + Linux Jitter testing program version 1.9 + Iterations=20 + The pragram will execute a dummy function 80000 times + Display is updated every 20000 displayUpdate intervals + Thread affinity will be set to core_id:7 + Timings are in CPU Core cycles + Inst_Min: Minimum Excution time during the display update interval(default is ~1 second) + Inst_Max: Maximum Excution time during the display update interval(default is ~1 second) + Inst_jitter: Jitter in the Excution time during rhe display update interval. This is the value of interest + last_Exec: The Excution time of last iteration just before the display update + Abs_Min: Absolute Minimum Excution time since the program started or statistics were reset + Abs_Max: Absolute Maximum Excution time since the program started or statistics were reset + tmp: Cumulative value calcualted by the dummy function + Interval: Time interval between the display updates in Core Cycles + Sample No: Sample number + + Inst_Min,Inst_Max,Inst_jitter,last_Exec,Abs_min,Abs_max,tmp,Interval,Sample No + 160370,165364,4994,160380,160370,165364,1042874368,3211228620,1 + 160370,165308,4938,160430,160370,165364,1279852544,3211283594,2 + 160370,169968,9598,160394,160370,169968,1516830720,3211446352,3 + 160370,166026,5656,160430,160370,169968,1753808896,3211263720,4 + 160370,165516,5146,160414,160370,169968,1990787072,3211249674,5 + 160370,165594,5224,160448,160370,169968,2227765248,3211267504,6 + 160370,169988,9618,160374,160370,169988,2464743424,3211426160,7 + 160370,165384,5014,160382,160370,169988,2701721600,3211243706,8 + 160370,165514,5144,160444,160370,169988,2938699776,3211233152,9 + 160370,168954,8584,160392,160370,169988,3175677952,3211338334,10 + 160370,167270,6900,160374,160370,169988,3412656128,3211329846,11 + 160370,165430,5060,160408,160370,169988,3649634304,3211240244,12 + 160370,166196,5826,160398,160370,169988,3886612480,3211256920,13 + 160370,169678,9308,160398,160370,169988,4123590656,3211415892,14 + 160370,165718,5348,160418,160370,169988,65601536,3211259448,15 + 160370,165256,4886,160372,160370,169988,302579712,3211236834,16 + 160370,167840,7470,160382,160370,169988,539557888,3211260000,17 + 160370,169332,8962,160400,160370,169988,776536064,3211432972,18 + 160370,165272,4902,160428,160370,169988,1013514240,3211246698,19 + 160370,165906,5536,160398,160370,169988,1250492416,3211262146,20 diff --git a/docs/report/introduction/environment/sut_calib_tsh.rst b/docs/report/introduction/environment/sut_calib_tsh.rst new file mode 100644 index 0000000000..8e3c6f6b42 --- /dev/null +++ b/docs/report/introduction/environment/sut_calib_tsh.rst @@ -0,0 +1,22 @@ +TaiShan +~~~~~~~ + +Following sections include sample calibration data measured on +s17-t33-sut1 server running in one of the Cortex-A72 testbeds. + + +Linux cmdline +^^^^^^^^^^^^^ + +:: + + $ cat /proc/cmdline + BOOT_IMAGE=/boot/vmlinuz-5.4.0-65-generic root=UUID=7d1d0e77-4df0-43df-9619-a99db29ffb83 ro audit=0 intel_iommu=on isolcpus=1-27,29-55 nmi_watchdog=0 nohz_full=1-27,29-55 nosoftlockup processor.max_cstate=1 rcu_nocbs=1-27,29-55 console=ttyAMA0,115200n8 quiet + +Linux uname +^^^^^^^^^^^ + +:: + + $ uname -a + Linux 5.4.0-65-generic #73-Ubuntu SMP Mon Jan 18 17:25:17 UTC 2021 x86_64 x86_64 x86_64 GNU/Linux diff --git a/docs/report/introduction/test_environment_sut_calib_tx2.rst b/docs/report/introduction/environment/sut_calib_tx2.rst index 05b7d8c16a..17f98c0d01 100644 --- a/docs/report/introduction/test_environment_sut_calib_tx2.rst +++ b/docs/report/introduction/environment/sut_calib_tx2.rst @@ -20,6 +20,3 @@ Linux uname $ uname -a Linux 5.4.0-65-generic #73-Ubuntu SMP Mon Jan 18 17:25:17 UTC 2021 x86_64 x86_64 x86_64 GNU/Linux - - -.. include:: ../introduction/test_environment_sut_meltspec_tx2.rst diff --git a/docs/report/introduction/environment/sut_calib_zn2.rst b/docs/report/introduction/environment/sut_calib_zn2.rst new file mode 100644 index 0000000000..19223cbf92 --- /dev/null +++ b/docs/report/introduction/environment/sut_calib_zn2.rst @@ -0,0 +1,65 @@ +EPYC Zen2 +~~~~~~~~~ + +Following sections include sample calibration data measured on server running in +one of the AMD EPYC testbeds. + +Linux cmdline +^^^^^^^^^^^^^ + +:: + + $ cat /proc/cmdline + BOOT_IMAGE=/boot/vmlinuz-5.15.0-46-generic root=UUID=cac1254f-9426-4ea6-a8db-2554f075db99 ro amd_iommu=on audit=0 default_hugepagesz=2M hugepagesz=1G hugepages=32 hugepagesz=2M hugepages=32768 hpet=disable iommu=pt isolcpus=1-15,17-31,33-47,49-63 nmi_watchdog=0 nohz_full=off nosoftlockup numa_balancing=disable processor.max_cstate=0 rcu_nocbs=1-15,17-31,33-47,49-63 tsc=reliable console=ttyS0,115200n8 quiet + +Linux uname +^^^^^^^^^^^ + +:: + + $ uname -a + Linux s60-t210-sut1 5.15.0-46-generic #49-Ubuntu SMP Thu Aug 4 18:03:25 UTC 2022 x86_64 x86_64 x86_64 GNU/Linux + +System-level Core Jitter +^^^^^^^^^^^^^^^^^^^^^^^^ + +:: + + $ sudo taskset -c 3 /home/testuser/pma_tools/jitter/jitter -i 30 + Linux Jitter testing program version 1.9 + Iterations=20 + The pragram will execute a dummy function 80000 times + Display is updated every 20000 displayUpdate intervals + Thread affinity will be set to core_id:7 + Timings are in CPU Core cycles + Inst_Min: Minimum Excution time during the display update interval(default is ~1 second) + Inst_Max: Maximum Excution time during the display update interval(default is ~1 second) + Inst_jitter: Jitter in the Excution time during rhe display update interval. This is the value of interest + last_Exec: The Excution time of last iteration just before the display update + Abs_Min: Absolute Minimum Excution time since the program started or statistics were reset + Abs_Max: Absolute Maximum Excution time since the program started or statistics were reset + tmp: Cumulative value calcualted by the dummy function + Interval: Time interval between the display updates in Core Cycles + Sample No: Sample number + + Inst_Min,Inst_Max,Inst_jitter,last_Exec,Abs_min,Abs_max,tmp,Interval,Sample No + 116400,145848,29448,116400,116400,145848,2076377088,2375383296,1 + 116400,145848,29448,116400,116400,145848,388169728,2363555544,2 + 116400,145848,29448,116400,116400,145848,2994929664,2359881480,3 + 116400,145848,29448,116400,116400,145848,1306722304,2367487104,4 + 116400,145848,29448,116400,116400,145848,3913482240,2357721768,5 + 116400,145848,29448,116400,116400,145848,2225274880,2381723112,6 + 116400,145848,29448,116424,116400,145848,537067520,2373138432,7 + 116400,145848,29448,116424,116400,145848,3143827456,2372221464,8 + 116400,145848,29448,116400,116400,145848,1455620096,2365450272,9 + 116400,145848,29448,116400,116400,145848,4062380032,2364814440,10 + 116400,145848,29448,116400,116400,145848,2374172672,2375992608,11 + 116400,145848,29448,116400,116400,145848,685965312,2362608552,12 + 116400,145848,29448,116400,116400,145848,3292725248,2362597944,13 + 116400,145848,29448,145512,116400,145848,1604517888,2370049344,14 + 116400,145848,29448,116400,116400,145848,4211277824,2366291784,15 + 116400,145848,29448,116400,116400,145848,2523070464,2349077352,16 + 116400,145848,29448,116400,116400,145848,834863104,2375406360,17 + 116400,145848,29448,116400,116400,145848,3441623040,2373272976,18 + 116400,145848,29448,116400,116400,145848,1753415680,2382267192,19 + 116400,145848,29448,116400,116400,145848,65208320,2359406040,20 diff --git a/docs/report/introduction/test_environment_sut_conf_1.rst b/docs/report/introduction/environment/sut_conf_1.rst index 7f724dd6ea..7f724dd6ea 100644 --- a/docs/report/introduction/test_environment_sut_conf_1.rst +++ b/docs/report/introduction/environment/sut_conf_1.rst diff --git a/docs/report/introduction/test_environment_sut_meltspec_alt.rst b/docs/report/introduction/environment/sut_meltspec_alt.rst index b087a93900..a92bfa2792 100644 --- a/docs/report/introduction/test_environment_sut_meltspec_alt.rst +++ b/docs/report/introduction/environment/sut_meltspec_alt.rst @@ -11,7 +11,7 @@ made public in 2018. Script is available on `Spectre & Meltdown Checker Github Spectre and Meltdown mitigation detection tool v0.45 Checking for vulnerabilities on current system - Kernel is Linux 5.4.0-65-generic #73-Ubuntu SMP Mon Jan 18 17:27:25 UTC 2021 aarch64 + Kernel is Linux 5.15.0-46-generic #49-Ubuntu SMP Thu Aug 4 18:08:11 UTC 2022 aarch64 CPU is ARM v8 model 0xd0c Hardware check @@ -34,10 +34,10 @@ made public in 2018. Script is available on `Spectre & Meltdown Checker Github CVE-2017-5753 aka Spectre Variant 1, bounds check bypass * Mitigated according to the /sys interface: YES (Mitigation: __user pointer sanitization) - > STATUS: UNKNOWN (/sys vulnerability interface use forced, but it's not available!) + > STATUS: UNKNOWN (/sys vulnerability interface use forced, but its not available!) CVE-2017-5715 aka Spectre Variant 2, branch target injection - * Mitigated according to the /sys interface: YES (Not affected) + * Mitigated according to the /sys interface: YES (Mitigation: CSV2, BHB) > STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not affected) CVE-2017-5754 aka Variant 3, Meltdown, rogue data cache load diff --git a/docs/report/introduction/environment/sut_meltspec_clx.rst b/docs/report/introduction/environment/sut_meltspec_clx.rst new file mode 100644 index 0000000000..19fb831e8f --- /dev/null +++ b/docs/report/introduction/environment/sut_meltspec_clx.rst @@ -0,0 +1,133 @@ +Spectre and Meltdown Checks +^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +Following section displays the output of a running shell script to tell if +system is vulnerable against the several speculative execution CVEs that were +made public in 2018. Script is available on `Spectre & Meltdown Checker Github +<https://github.com/speed47/spectre-meltdown-checker>`_. + +:: + + Spectre and Meltdown mitigation detection tool v0.45 + + Checking for vulnerabilities on current system + Kernel is Linux 5.15.0-46-generic #49-Ubuntu SMP Thu Aug 4 18:03:25 UTC 2022 x86_64 + CPU is Intel(R) Xeon(R) Gold 6252N CPU @ 2.30GHz + + Hardware check + * Hardware support (CPU microcode) for mitigation techniques + * Indirect Branch Restricted Speculation (IBRS) + * SPEC_CTRL MSR is available: YES + * CPU indicates IBRS capability: YES (SPEC_CTRL feature bit) + * Indirect Branch Prediction Barrier (IBPB) + * CPU indicates IBPB capability: YES (SPEC_CTRL feature bit) + * Single Thread Indirect Branch Predictors (STIBP) + * SPEC_CTRL MSR is available: YES + * CPU indicates STIBP capability: YES (Intel STIBP feature bit) + * Speculative Store Bypass Disable (SSBD) + * CPU indicates SSBD capability: YES (Intel SSBD) + * L1 data cache invalidation + * CPU indicates L1D flush capability: YES (L1D flush feature bit) + * Microarchitectural Data Sampling + * VERW instruction is available: YES (MD_CLEAR feature bit) + * Indirect Branch Predictor Controls + * Indirect Predictor Disable feature is available: NO + * Bottomless RSB Disable feature is available: NO + * BHB-Focused Indirect Predictor Disable feature is available: NO + * Enhanced IBRS (IBRS_ALL) + * CPU indicates ARCH_CAPABILITIES MSR availability: YES + * ARCH_CAPABILITIES MSR advertises IBRS_ALL capability: YES + * CPU explicitly indicates not being affected by Meltdown/L1TF (RDCL_NO): YES + * CPU explicitly indicates not being affected by Variant 4 (SSB_NO): NO + * CPU/Hypervisor indicates L1D flushing is not necessary on this system: YES + * Hypervisor indicates host CPU might be affected by RSB underflow (RSBA): NO + * CPU explicitly indicates not being affected by Microarchitectural Data Sampling (MDS_NO): YES + * CPU explicitly indicates not being affected by TSX Asynchronous Abort (TAA_NO): NO + * CPU explicitly indicates not being affected by iTLB Multihit (PSCHANGE_MSC_NO): NO + * CPU explicitly indicates having MSR for TSX control (TSX_CTRL_MSR): YES + * TSX_CTRL MSR indicates TSX RTM is disabled: YES + * TSX_CTRL MSR indicates TSX CPUID bit is cleared: YES + * CPU supports Transactional Synchronization Extensions (TSX): NO + * CPU supports Software Guard Extensions (SGX): NO + * CPU supports Special Register Buffer Data Sampling (SRBDS): NO + * CPU microcode is known to cause stability problems: NO (family 0x6 model 0x55 stepping 0x7 ucode 0x500002c cpuid 0x50657) + * CPU microcode is the latest known available version: NO (latest version is 0x500320a dated 2021/08/13 according to builtin firmwares DB v222+i20220208) + * CPU vulnerability to the speculative execution attack variants + * Affected by CVE-2017-5753 (Spectre Variant 1, bounds check bypass): YES + * Affected by CVE-2017-5715 (Spectre Variant 2, branch target injection): YES + * Affected by CVE-2017-5754 (Variant 3, Meltdown, rogue data cache load): NO + * Affected by CVE-2018-3640 (Variant 3a, rogue system register read): YES + * Affected by CVE-2018-3639 (Variant 4, speculative store bypass): YES + * Affected by CVE-2018-3615 (Foreshadow (SGX), L1 terminal fault): NO + * Affected by CVE-2018-3620 (Foreshadow-NG (OS), L1 terminal fault): YES + * Affected by CVE-2018-3646 (Foreshadow-NG (VMM), L1 terminal fault): YES + * Affected by CVE-2018-12126 (Fallout, microarchitectural store buffer data sampling (MSBDS)): NO + * Affected by CVE-2018-12130 (ZombieLoad, microarchitectural fill buffer data sampling (MFBDS)): NO + * Affected by CVE-2018-12127 (RIDL, microarchitectural load port data sampling (MLPDS)): NO + * Affected by CVE-2019-11091 (RIDL, microarchitectural data sampling uncacheable memory (MDSUM)): NO + * Affected by CVE-2019-11135 (ZombieLoad V2, TSX Asynchronous Abort (TAA)): NO + * Affected by CVE-2018-12207 (No eXcuses, iTLB Multihit, machine check exception on page size changes (MCEPSC)): YES + * Affected by CVE-2020-0543 (Special Register Buffer Data Sampling (SRBDS)): NO + + CVE-2017-5753 aka Spectre Variant 1, bounds check bypass + * Mitigated according to the /sys interface: YES (Mitigation: usercopy/swapgs barriers and __user pointer sanitization) + > STATUS: UNKNOWN (/sys vulnerability interface use forced, but its not available!) + + CVE-2017-5715 aka Spectre Variant 2, branch target injection + * Mitigated according to the /sys interface: YES (Mitigation: Enhanced IBRS, IBPB: conditional, RSB filling) + > STATUS: VULNERABLE (IBRS+IBPB or retpoline+IBPB+RSB filling, is needed to mitigate the vulnerability) + + CVE-2017-5754 aka Variant 3, Meltdown, rogue data cache load + * Mitigated according to the /sys interface: YES (Not affected) + * Running as a Xen PV DomU: NO + > STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not affected) + + CVE-2018-3640 aka Variant 3a, rogue system register read + * CPU microcode mitigates the vulnerability: YES + > STATUS: NOT VULNERABLE (your CPU microcode mitigates the vulnerability) + + CVE-2018-3639 aka Variant 4, speculative store bypass + * Mitigated according to the /sys interface: YES (Mitigation: Speculative Store Bypass disabled via prctl and seccomp) + > STATUS: NOT VULNERABLE (Mitigation: Speculative Store Bypass disabled via prctl and seccomp) + + CVE-2018-3615 aka Foreshadow (SGX), L1 terminal fault + * CPU microcode mitigates the vulnerability: N/A + > STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not affected) + + CVE-2018-3620 aka Foreshadow-NG (OS), L1 terminal fault + * Mitigated according to the /sys interface: YES (Not affected) + > STATUS: NOT VULNERABLE (Not affected) + + CVE-2018-3646 aka Foreshadow-NG (VMM), L1 terminal fault + * Information from the /sys interface: Not affected + > STATUS: NOT VULNERABLE (your kernel reported your CPU model as not affected) + + CVE-2018-12126 aka Fallout, microarchitectural store buffer data sampling (MSBDS) + * Mitigated according to the /sys interface: YES (Not affected) + > STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not affected) + + CVE-2018-12130 aka ZombieLoad, microarchitectural fill buffer data sampling (MFBDS) + * Mitigated according to the /sys interface: YES (Not affected) + > STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not affected) + + CVE-2018-12127 aka RIDL, microarchitectural load port data sampling (MLPDS) + * Mitigated according to the /sys interface: YES (Not affected) + > STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not affected) + + CVE-2019-11091 aka RIDL, microarchitectural data sampling uncacheable memory (MDSUM) + * Mitigated according to the /sys interface: YES (Not affected) + > STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not affected) + + CVE-2019-11135 aka ZombieLoad V2, TSX Asynchronous Abort (TAA) + * Mitigated according to the /sys interface: YES (Mitigation: TSX disabled) + > STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not affected) + + CVE-2018-12207 aka No eXcuses, iTLB Multihit, machine check exception on page size changes (MCEPSC) + * Mitigated according to the /sys interface: YES (KVM: Mitigation: VMX disabled) + > STATUS: NOT VULNERABLE (KVM: Mitigation: VMX disabled) + + CVE-2020-0543 aka Special Register Buffer Data Sampling (SRBDS) + * Mitigated according to the /sys interface: YES (Not affected) + > STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not affected) + + > SUMMARY: CVE-2017-5753:?? CVE-2017-5715:KO CVE-2017-5754:OK CVE-2018-3640:OK CVE-2018-3639:OK CVE-2018-3615:OK CVE-2018-3620:OK CVE-2018-3646:OK CVE-2018-12126:OK CVE-2018-12130:OK CVE-2018-12127:OK CVE-2019-11091:OK CVE-2019-11135:OK CVE-2018-12207:OK CVE-2020-0543:OK diff --git a/docs/report/introduction/environment/sut_meltspec_dnv.rst b/docs/report/introduction/environment/sut_meltspec_dnv.rst new file mode 100644 index 0000000000..a3c9284758 --- /dev/null +++ b/docs/report/introduction/environment/sut_meltspec_dnv.rst @@ -0,0 +1,131 @@ +Spectre and Meltdown Checks +^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +Following section displays the output of a running shell script to tell if +system is vulnerable against the several "speculative execution" CVEs that were +made public in 2018. Script is available on `Spectre & Meltdown Checker Github +<https://github.com/speed47/spectre-meltdown-checker>`_. + +:: + + Spectre and Meltdown mitigation detection tool v0.45 + + Checking for vulnerabilities on current system + Kernel is Linux 5.4.0-65-generic #73-Ubuntu SMP Mon Jan 18 17:25:17 UTC 2021 x86_64 + CPU is Intel(R) Atom(TM) CPU C3858 @ 2.00GHz + + Hardware check + * Hardware support (CPU microcode) for mitigation techniques + * Indirect Branch Restricted Speculation (IBRS) + * SPEC_CTRL MSR is available: YES + * CPU indicates IBRS capability: YES (SPEC_CTRL feature bit) + * Indirect Branch Prediction Barrier (IBPB) + * CPU indicates IBPB capability: YES (SPEC_CTRL feature bit) + * Single Thread Indirect Branch Predictors (STIBP) + * SPEC_CTRL MSR is available: YES + * CPU indicates STIBP capability: YES (Intel STIBP feature bit) + * Speculative Store Bypass Disable (SSBD) + * CPU indicates SSBD capability: NO + * L1 data cache invalidation + * CPU indicates L1D flush capability: NO + * Microarchitectural Data Sampling + * VERW instruction is available: NO + * Indirect Branch Predictor Controls + * Indirect Predictor Disable feature is available: NO + * Bottomless RSB Disable feature is available: NO + * BHB-Focused Indirect Predictor Disable feature is available: NO + * Enhanced IBRS (IBRS_ALL) + * CPU indicates ARCH_CAPABILITIES MSR availability: YES + * ARCH_CAPABILITIES MSR advertises IBRS_ALL capability: NO + * CPU explicitly indicates not being affected by Meltdown/L1TF (RDCL_NO): YES + * CPU explicitly indicates not being affected by Variant 4 (SSB_NO): NO + * CPU/Hypervisor indicates L1D flushing is not necessary on this system: NO + * Hypervisor indicates host CPU might be affected by RSB underflow (RSBA): NO + * CPU explicitly indicates not being affected by Microarchitectural Data Sampling (MDS_NO): NO + * CPU explicitly indicates not being affected by TSX Asynchronous Abort (TAA_NO): NO + * CPU explicitly indicates not being affected by iTLB Multihit (PSCHANGE_MSC_NO): NO + * CPU explicitly indicates having MSR for TSX control (TSX_CTRL_MSR): NO + * CPU supports Transactional Synchronization Extensions (TSX): NO + * CPU supports Software Guard Extensions (SGX): NO + * CPU supports Special Register Buffer Data Sampling (SRBDS): NO + * CPU microcode is known to cause stability problems: NO (family 0x6 model 0x5f stepping 0x1 ucode 0x20 cpuid 0x506f1) + * CPU microcode is the latest known available version: NO (latest version is 0x36 dated 2021/05/10 according to builtin firmwares DB v222+i20220208) + * CPU vulnerability to the speculative execution attack variants + * Affected by CVE-2017-5753 (Spectre Variant 1, bounds check bypass): YES + * Affected by CVE-2017-5715 (Spectre Variant 2, branch target injection): YES + * Affected by CVE-2017-5754 (Variant 3, Meltdown, rogue data cache load): NO + * Affected by CVE-2018-3640 (Variant 3a, rogue system register read): YES + * Affected by CVE-2018-3639 (Variant 4, speculative store bypass): YES + * Affected by CVE-2018-3615 (Foreshadow (SGX), L1 terminal fault): NO + * Affected by CVE-2018-3620 (Foreshadow-NG (OS), L1 terminal fault): NO + * Affected by CVE-2018-3646 (Foreshadow-NG (VMM), L1 terminal fault): NO + * Affected by CVE-2018-12126 (Fallout, microarchitectural store buffer data sampling (MSBDS)): NO + * Affected by CVE-2018-12130 (ZombieLoad, microarchitectural fill buffer data sampling (MFBDS)): NO + * Affected by CVE-2018-12127 (RIDL, microarchitectural load port data sampling (MLPDS)): NO + * Affected by CVE-2019-11091 (RIDL, microarchitectural data sampling uncacheable memory (MDSUM)): NO + * Affected by CVE-2019-11135 (ZombieLoad V2, TSX Asynchronous Abort (TAA)): NO + * Affected by CVE-2018-12207 (No eXcuses, iTLB Multihit, machine check exception on page size changes (MCEPSC)): NO + * Affected by CVE-2020-0543 (Special Register Buffer Data Sampling (SRBDS)): NO + + CVE-2017-5753 aka Spectre Variant 1, bounds check bypass + * Mitigated according to the /sys interface: YES (Mitigation: usercopy/swapgs barriers and __user pointer sanitization) + > STATUS: UNKNOWN (/sys vulnerability interface use forced, but its not available!) + + CVE-2017-5715 aka Spectre Variant 2, branch target injection + * Mitigated according to the /sys interface: YES (Mitigation: Full generic retpoline, IBPB: conditional, IBRS_FW, STIBP: disabled, RSB filling) + > STATUS: VULNERABLE (IBRS+IBPB or retpoline+IBPB is needed to mitigate the vulnerability) + + CVE-2017-5754 aka Variant 3, Meltdown, rogue data cache load + * Mitigated according to the /sys interface: YES (Not affected) + * Running as a Xen PV DomU: NO + > STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not affected) + + CVE-2018-3640 aka Variant 3a, rogue system register read + * CPU microcode mitigates the vulnerability: NO + > STATUS: VULNERABLE (an up-to-date CPU microcode is needed to mitigate this vulnerability) + + CVE-2018-3639 aka Variant 4, speculative store bypass + * Mitigated according to the /sys interface: NO (Vulnerable) + > STATUS: VULNERABLE (Neither your CPU nor your kernel support SSBD) + + CVE-2018-3615 aka Foreshadow (SGX), L1 terminal fault + * CPU microcode mitigates the vulnerability: N/A + > STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not affected) + + CVE-2018-3620 aka Foreshadow-NG (OS), L1 terminal fault + * Mitigated according to the /sys interface: YES (Not affected) + > STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not affected) + + CVE-2018-3646 aka Foreshadow-NG (VMM), L1 terminal fault + * Information from the /sys interface: Not affected + > STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not affected) + + CVE-2018-12126 aka Fallout, microarchitectural store buffer data sampling (MSBDS) + * Mitigated according to the /sys interface: YES (Not affected) + > STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not affected) + + CVE-2018-12130 aka ZombieLoad, microarchitectural fill buffer data sampling (MFBDS) + * Mitigated according to the /sys interface: YES (Not affected) + > STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not affected) + + CVE-2018-12127 aka RIDL, microarchitectural load port data sampling (MLPDS) + * Mitigated according to the /sys interface: YES (Not affected) + > STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not affected) + + CVE-2019-11091 aka RIDL, microarchitectural data sampling uncacheable memory (MDSUM) + * Mitigated according to the /sys interface: YES (Not affected) + > STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not affected) + + CVE-2019-11135 aka ZombieLoad V2, TSX Asynchronous Abort (TAA) + * Mitigated according to the /sys interface: YES (Not affected) + > STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not affected) + + CVE-2018-12207 aka No eXcuses, iTLB Multihit, machine check exception on page size changes (MCEPSC) + * Mitigated according to the /sys interface: YES (Not affected) + > STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not affected) + + CVE-2020-0543 aka Special Register Buffer Data Sampling (SRBDS) + * Mitigated according to the /sys interface: YES (Not affected) + > STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not affected) + + > SUMMARY: CVE-2017-5753:?? CVE-2017-5715:KO CVE-2017-5754:OK CVE-2018-3640:KO CVE-2018-3639:KO CVE-2018-3615:OK CVE-2018-3620:OK CVE-2018-3646:OK CVE-2018-12126:OK CVE-2018-12130:OK CVE-2018-12127:OK CVE-2019-11091:OK CVE-2019-11135:OK CVE-2018-12207:OK CVE-2020-0543:OK diff --git a/docs/report/introduction/environment/sut_meltspec_icx.rst b/docs/report/introduction/environment/sut_meltspec_icx.rst new file mode 100644 index 0000000000..89d82b7e1c --- /dev/null +++ b/docs/report/introduction/environment/sut_meltspec_icx.rst @@ -0,0 +1,133 @@ +Spectre and Meltdown Checks +^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +Following section displays the output of a running shell script to tell if +system is vulnerable against the several speculative execution CVEs that were +made public in 2018. Script is available on `Spectre & Meltdown Checker Github +<https://github.com/speed47/spectre-meltdown-checker>`_. + +:: + + Spectre and Meltdown mitigation detection tool v0.45 + + Checking for vulnerabilities on current system + Kernel is Linux 5.15.0-46-generic #49-Ubuntu SMP Thu Aug 4 18:03:25 UTC 2022 x86_64 + CPU is Intel(R) Xeon(R) Platinum 8358 CPU @ 2.60GHz + + Hardware check + * Hardware support (CPU microcode) for mitigation techniques + * Indirect Branch Restricted Speculation (IBRS) + * SPEC_CTRL MSR is available: YES + * CPU indicates IBRS capability: YES (SPEC_CTRL feature bit) + * Indirect Branch Prediction Barrier (IBPB) + * CPU indicates IBPB capability: YES (SPEC_CTRL feature bit) + * Single Thread Indirect Branch Predictors (STIBP) + * SPEC_CTRL MSR is available: YES + * CPU indicates STIBP capability: YES (Intel STIBP feature bit) + * Speculative Store Bypass Disable (SSBD) + * CPU indicates SSBD capability: YES (Intel SSBD) + * L1 data cache invalidation + * CPU indicates L1D flush capability: YES (L1D flush feature bit) + * Microarchitectural Data Sampling + * VERW instruction is available: YES (MD_CLEAR feature bit) + * Indirect Branch Predictor Controls + * Indirect Predictor Disable feature is available: NO + * Bottomless RSB Disable feature is available: NO + * BHB-Focused Indirect Predictor Disable feature is available: NO + * Enhanced IBRS (IBRS_ALL) + * CPU indicates ARCH_CAPABILITIES MSR availability: YES + * ARCH_CAPABILITIES MSR advertises IBRS_ALL capability: YES + * CPU explicitly indicates not being affected by Meltdown/L1TF (RDCL_NO): YES + * CPU explicitly indicates not being affected by Variant 4 (SSB_NO): NO + * CPU/Hypervisor indicates L1D flushing is not necessary on this system: YES + * Hypervisor indicates host CPU might be affected by RSB underflow (RSBA): NO + * CPU explicitly indicates not being affected by Microarchitectural Data Sampling (MDS_NO): YES + * CPU explicitly indicates not being affected by TSX Asynchronous Abort (TAA_NO): YES + * CPU explicitly indicates not being affected by iTLB Multihit (PSCHANGE_MSC_NO): YES + * CPU explicitly indicates having MSR for TSX control (TSX_CTRL_MSR): YES + * TSX_CTRL MSR indicates TSX RTM is disabled: YES + * TSX_CTRL MSR indicates TSX CPUID bit is cleared: YES + * CPU supports Transactional Synchronization Extensions (TSX): NO + * CPU supports Software Guard Extensions (SGX): YES + * CPU supports Special Register Buffer Data Sampling (SRBDS): NO + * CPU microcode is known to cause stability problems: NO (family 0x6 model 0x6a stepping 0x6 ucode 0xd000280 cpuid 0x606a6) + * CPU microcode is the latest known available version: NO (latest version is 0xd000331 dated 2021/12/03 according to builtin firmwares DB v222+i20220208) + * CPU vulnerability to the speculative execution attack variants + * Affected by CVE-2017-5753 (Spectre Variant 1, bounds check bypass): YES + * Affected by CVE-2017-5715 (Spectre Variant 2, branch target injection): YES + * Affected by CVE-2017-5754 (Variant 3, Meltdown, rogue data cache load): NO + * Affected by CVE-2018-3640 (Variant 3a, rogue system register read): YES + * Affected by CVE-2018-3639 (Variant 4, speculative store bypass): YES + * Affected by CVE-2018-3615 (Foreshadow (SGX), L1 terminal fault): YES + * Affected by CVE-2018-3620 (Foreshadow-NG (OS), L1 terminal fault): YES + * Affected by CVE-2018-3646 (Foreshadow-NG (VMM), L1 terminal fault): YES + * Affected by CVE-2018-12126 (Fallout, microarchitectural store buffer data sampling (MSBDS)): NO + * Affected by CVE-2018-12130 (ZombieLoad, microarchitectural fill buffer data sampling (MFBDS)): NO + * Affected by CVE-2018-12127 (RIDL, microarchitectural load port data sampling (MLPDS)): NO + * Affected by CVE-2019-11091 (RIDL, microarchitectural data sampling uncacheable memory (MDSUM)): NO + * Affected by CVE-2019-11135 (ZombieLoad V2, TSX Asynchronous Abort (TAA)): NO + * Affected by CVE-2018-12207 (No eXcuses, iTLB Multihit, machine check exception on page size changes (MCEPSC)): YES + * Affected by CVE-2020-0543 (Special Register Buffer Data Sampling (SRBDS)): NO + + CVE-2017-5753 aka Spectre Variant 1, bounds check bypass + * Mitigated according to the /sys interface: YES (Mitigation: usercopy/swapgs barriers and __user pointer sanitization) + > STATUS: UNKNOWN (/sys vulnerability interface use forced, but its not available!) + + CVE-2017-5715 aka Spectre Variant 2, branch target injection + * Mitigated according to the /sys interface: YES (Mitigation: Enhanced IBRS, IBPB: conditional, RSB filling) + > STATUS: VULNERABLE (IBRS+IBPB or retpoline+IBPB is needed to mitigate the vulnerability) + + CVE-2017-5754 aka Variant 3, Meltdown, rogue data cache load + * Mitigated according to the /sys interface: YES (Not affected) + * Running as a Xen PV DomU: NO + > STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not affected) + + CVE-2018-3640 aka Variant 3a, rogue system register read + * CPU microcode mitigates the vulnerability: YES + > STATUS: NOT VULNERABLE (your CPU microcode mitigates the vulnerability) + + CVE-2018-3639 aka Variant 4, speculative store bypass + * Mitigated according to the /sys interface: YES (Mitigation: Speculative Store Bypass disabled via prctl and seccomp) + > STATUS: NOT VULNERABLE (Mitigation: Speculative Store Bypass disabled via prctl and seccomp) + + CVE-2018-3615 aka Foreshadow (SGX), L1 terminal fault + * CPU microcode mitigates the vulnerability: YES + > STATUS: NOT VULNERABLE (your CPU microcode mitigates the vulnerability) + + CVE-2018-3620 aka Foreshadow-NG (OS), L1 terminal fault + * Mitigated according to the /sys interface: YES (Not affected) + > STATUS: NOT VULNERABLE (Not affected) + + CVE-2018-3646 aka Foreshadow-NG (VMM), L1 terminal fault + * Information from the /sys interface: Not affected + > STATUS: NOT VULNERABLE (your kernel reported your CPU model as not affected) + + CVE-2018-12126 aka Fallout, microarchitectural store buffer data sampling (MSBDS) + * Mitigated according to the /sys interface: YES (Not affected) + > STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not affected) + + CVE-2018-12130 aka ZombieLoad, microarchitectural fill buffer data sampling (MFBDS) + * Mitigated according to the /sys interface: YES (Not affected) + > STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not affected) + + CVE-2018-12127 aka RIDL, microarchitectural load port data sampling (MLPDS) + * Mitigated according to the /sys interface: YES (Not affected) + > STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not affected) + + CVE-2019-11091 aka RIDL, microarchitectural data sampling uncacheable memory (MDSUM) + * Mitigated according to the /sys interface: YES (Not affected) + > STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not affected) + + CVE-2019-11135 aka ZombieLoad V2, TSX Asynchronous Abort (TAA) + * Mitigated according to the /sys interface: YES (Not affected) + > STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not affected) + + CVE-2018-12207 aka No eXcuses, iTLB Multihit, machine check exception on page size changes (MCEPSC) + * Mitigated according to the /sys interface: YES (Not affected) + > STATUS: NOT VULNERABLE (Not affected) + + CVE-2020-0543 aka Special Register Buffer Data Sampling (SRBDS) + * Mitigated according to the /sys interface: YES (Not affected) + > STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not affected) + + > SUMMARY: CVE-2017-5753:?? CVE-2017-5715:KO CVE-2017-5754:OK CVE-2018-3640:OK CVE-2018-3639:OK CVE-2018-3615:OK CVE-2018-3620:OK CVE-2018-3646:OK CVE-2018-12126:OK CVE-2018-12130:OK CVE-2018-12127:OK CVE-2019-11091:OK CVE-2019-11135:OK CVE-2018-12207:OK CVE-2020-0543:OK
\ No newline at end of file diff --git a/docs/report/introduction/environment/sut_meltspec_snr.rst b/docs/report/introduction/environment/sut_meltspec_snr.rst new file mode 100644 index 0000000000..0697b27c03 --- /dev/null +++ b/docs/report/introduction/environment/sut_meltspec_snr.rst @@ -0,0 +1,131 @@ +Spectre and Meltdown Checks +^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +Following section displays the output of a running shell script to tell if +system is vulnerable against the several "speculative execution" CVEs that were +made public in 2018. Script is available on `Spectre & Meltdown Checker Github +<https://github.com/speed47/spectre-meltdown-checker>`_. + +:: + + Spectre and Meltdown mitigation detection tool v0.45 + + Checking for vulnerabilities on current system + Kernel is Linux 5.15.0-46-generic #49-Ubuntu SMP Thu Aug 4 18:03:25 UTC 2022 x86_64 + CPU is Intel Atom(R) P5362 processor + + Hardware check + * Hardware support (CPU microcode) for mitigation techniques + * Indirect Branch Restricted Speculation (IBRS) + * SPEC_CTRL MSR is available: YES + * CPU indicates IBRS capability: YES (SPEC_CTRL feature bit) + * Indirect Branch Prediction Barrier (IBPB) + * CPU indicates IBPB capability: YES (SPEC_CTRL feature bit) + * Single Thread Indirect Branch Predictors (STIBP) + * SPEC_CTRL MSR is available: YES + * CPU indicates STIBP capability: YES (Intel STIBP feature bit) + * Speculative Store Bypass Disable (SSBD) + * CPU indicates SSBD capability: YES (Intel SSBD) + * L1 data cache invalidation + * CPU indicates L1D flush capability: YES (L1D flush feature bit) + * Microarchitectural Data Sampling + * VERW instruction is available: YES (MD_CLEAR feature bit) + * Indirect Branch Predictor Controls + * Indirect Predictor Disable feature is available: NO + * Bottomless RSB Disable feature is available: NO + * BHB-Focused Indirect Predictor Disable feature is available: NO + * Enhanced IBRS (IBRS_ALL) + * CPU indicates ARCH_CAPABILITIES MSR availability: YES + * ARCH_CAPABILITIES MSR advertises IBRS_ALL capability: YES + * CPU explicitly indicates not being affected by Meltdown/L1TF (RDCL_NO): YES + * CPU explicitly indicates not being affected by Variant 4 (SSB_NO): NO + * CPU/Hypervisor indicates L1D flushing is not necessary on this system: YES + * Hypervisor indicates host CPU might be affected by RSB underflow (RSBA): NO + * CPU explicitly indicates not being affected by Microarchitectural Data Sampling (MDS_NO): YES + * CPU explicitly indicates not being affected by TSX Asynchronous Abort (TAA_NO): NO + * CPU explicitly indicates not being affected by iTLB Multihit (PSCHANGE_MSC_NO): YES + * CPU explicitly indicates having MSR for TSX control (TSX_CTRL_MSR): NO + * CPU supports Transactional Synchronization Extensions (TSX): NO + * CPU supports Software Guard Extensions (SGX): NO + * CPU supports Special Register Buffer Data Sampling (SRBDS): NO + * CPU microcode is known to cause stability problems: NO (family 0x6 model 0x86 stepping 0x7 ucode 0x4c000019 cpuid 0x80667) + * CPU microcode is the latest known available version: UNKNOWN (latest microcode version for your CPU model is unknown) + * CPU vulnerability to the speculative execution attack variants + * Affected by CVE-2017-5753 (Spectre Variant 1, bounds check bypass): YES + * Affected by CVE-2017-5715 (Spectre Variant 2, branch target injection): YES + * Affected by CVE-2017-5754 (Variant 3, Meltdown, rogue data cache load): NO + * Affected by CVE-2018-3640 (Variant 3a, rogue system register read): YES + * Affected by CVE-2018-3639 (Variant 4, speculative store bypass): YES + * Affected by CVE-2018-3615 (Foreshadow (SGX), L1 terminal fault): NO + * Affected by CVE-2018-3620 (Foreshadow-NG (OS), L1 terminal fault): NO + * Affected by CVE-2018-3646 (Foreshadow-NG (VMM), L1 terminal fault): NO + * Affected by CVE-2018-12126 (Fallout, microarchitectural store buffer data sampling (MSBDS)): NO + * Affected by CVE-2018-12130 (ZombieLoad, microarchitectural fill buffer data sampling (MFBDS)): NO + * Affected by CVE-2018-12127 (RIDL, microarchitectural load port data sampling (MLPDS)): NO + * Affected by CVE-2019-11091 (RIDL, microarchitectural data sampling uncacheable memory (MDSUM)): NO + * Affected by CVE-2019-11135 (ZombieLoad V2, TSX Asynchronous Abort (TAA)): NO + * Affected by CVE-2018-12207 (No eXcuses, iTLB Multihit, machine check exception on page size changes (MCEPSC)): YES + * Affected by CVE-2020-0543 (Special Register Buffer Data Sampling (SRBDS)): NO + + CVE-2017-5753 aka Spectre Variant 1, bounds check bypass + * Mitigated according to the /sys interface: YES (Mitigation: usercopy/swapgs barriers and __user pointer sanitization) + > STATUS: UNKNOWN (/sys vulnerability interface use forced, but its not available!) + + CVE-2017-5715 aka Spectre Variant 2, branch target injection + * Mitigated according to the /sys interface: YES (Mitigation: Enhanced IBRS, IBPB: conditional, RSB filling) + > STATUS: VULNERABLE (IBRS+IBPB or retpoline+IBPB is needed to mitigate the vulnerability) + + CVE-2017-5754 aka Variant 3, Meltdown, rogue data cache load + * Mitigated according to the /sys interface: YES (Not affected) + * Running as a Xen PV DomU: NO + > STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not affected) + + CVE-2018-3640 aka Variant 3a, rogue system register read + * CPU microcode mitigates the vulnerability: YES + > STATUS: NOT VULNERABLE (your CPU microcode mitigates the vulnerability) + + CVE-2018-3639 aka Variant 4, speculative store bypass + * Mitigated according to the /sys interface: YES (Mitigation: Speculative Store Bypass disabled via prctl and seccomp) + > STATUS: NOT VULNERABLE (Mitigation: Speculative Store Bypass disabled via prctl and seccomp) + + CVE-2018-3615 aka Foreshadow (SGX), L1 terminal fault + * CPU microcode mitigates the vulnerability: N/A + > STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not affected) + + CVE-2018-3620 aka Foreshadow-NG (OS), L1 terminal fault + * Mitigated according to the /sys interface: YES (Not affected) + > STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not affected) + + CVE-2018-3646 aka Foreshadow-NG (VMM), L1 terminal fault + * Information from the /sys interface: Not affected + > STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not affected) + + CVE-2018-12126 aka Fallout, microarchitectural store buffer data sampling (MSBDS) + * Mitigated according to the /sys interface: YES (Not affected) + > STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not affected) + + CVE-2018-12130 aka ZombieLoad, microarchitectural fill buffer data sampling (MFBDS) + * Mitigated according to the /sys interface: YES (Not affected) + > STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not affected) + + CVE-2018-12127 aka RIDL, microarchitectural load port data sampling (MLPDS) + * Mitigated according to the /sys interface: YES (Not affected) + > STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not affected) + + CVE-2019-11091 aka RIDL, microarchitectural data sampling uncacheable memory (MDSUM) + * Mitigated according to the /sys interface: YES (Not affected) + > STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not affected) + + CVE-2019-11135 aka ZombieLoad V2, TSX Asynchronous Abort (TAA) + * Mitigated according to the /sys interface: YES (Not affected) + > STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not affected) + + CVE-2018-12207 aka No eXcuses, iTLB Multihit, machine check exception on page size changes (MCEPSC) + * Mitigated according to the /sys interface: YES (Not affected) + > STATUS: NOT VULNERABLE (Not affected) + + CVE-2020-0543 aka Special Register Buffer Data Sampling (SRBDS) + * Mitigated according to the /sys interface: YES (Not affected) + > STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not affected) + + > SUMMARY: CVE-2017-5753:?? CVE-2017-5715:KO CVE-2017-5754:OK CVE-2018-3640:OK CVE-2018-3639:OK CVE-2018-3615:OK CVE-2018-3620:OK CVE-2018-3646:OK CVE-2018-12126:OK CVE-2018-12130:OK CVE-2018-12127:OK CVE-2019-11091:OK CVE-2019-11135:OK CVE-2018-12207:OK CVE-2020-0543:OK
\ No newline at end of file diff --git a/docs/report/introduction/environment/sut_meltspec_tsh.rst b/docs/report/introduction/environment/sut_meltspec_tsh.rst new file mode 100644 index 0000000000..bfa27fb34b --- /dev/null +++ b/docs/report/introduction/environment/sut_meltspec_tsh.rst @@ -0,0 +1,96 @@ +Spectre and Meltdown Checks +^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +Following section displays the output of a running shell script to tell if +system is vulnerable against the several "speculative execution" CVEs that were +made public in 2018. Script is available on `Spectre & Meltdown Checker Github +<https://github.com/speed47/spectre-meltdown-checker>`_. + +:: + + Spectre and Meltdown mitigation detection tool v0.45 + + Checking for vulnerabilities on current system + Kernel is Linux 5.15.0-46-generic #49-Ubuntu SMP Thu Aug 4 18:08:11 UTC 2022 aarch64 + CPU is ARM v8 model 0xd08 + + Hardware check + * CPU vulnerability to the speculative execution attack variants + * Affected by CVE-2017-5753 (Spectre Variant 1, bounds check bypass): YES + * Affected by CVE-2017-5715 (Spectre Variant 2, branch target injection): YES + * Affected by CVE-2017-5754 (Variant 3, Meltdown, rogue data cache load): NO + * Affected by CVE-2018-3640 (Variant 3a, rogue system register read): YES + * Affected by CVE-2018-3639 (Variant 4, speculative store bypass): YES + * Affected by CVE-2018-3615 (Foreshadow (SGX), L1 terminal fault): NO + * Affected by CVE-2018-3620 (Foreshadow-NG (OS), L1 terminal fault): NO + * Affected by CVE-2018-3646 (Foreshadow-NG (VMM), L1 terminal fault): NO + * Affected by CVE-2018-12126 (Fallout, microarchitectural store buffer data sampling (MSBDS)): NO + * Affected by CVE-2018-12130 (ZombieLoad, microarchitectural fill buffer data sampling (MFBDS)): NO + * Affected by CVE-2018-12127 (RIDL, microarchitectural load port data sampling (MLPDS)): NO + * Affected by CVE-2019-11091 (RIDL, microarchitectural data sampling uncacheable memory (MDSUM)): NO + * Affected by CVE-2019-11135 (ZombieLoad V2, TSX Asynchronous Abort (TAA)): NO + * Affected by CVE-2018-12207 (No eXcuses, iTLB Multihit, machine check exception on page size changes (MCEPSC)): NO + * Affected by CVE-2020-0543 (Special Register Buffer Data Sampling (SRBDS)): NO + + CVE-2017-5753 aka Spectre Variant 1, bounds check bypass + * Mitigated according to the /sys interface: YES (Mitigation: __user pointer sanitization) + > STATUS: UNKNOWN (/sys vulnerability interface use forced, but its not available!) + + CVE-2017-5715 aka Spectre Variant 2, branch target injection + * Mitigated according to the /sys interface: NO (Vulnerable) + > STATUS: VULNERABLE (Branch predictor hardening is needed to mitigate the vulnerability) + + CVE-2017-5754 aka Variant 3, Meltdown, rogue data cache load + * Mitigated according to the /sys interface: YES (Not affected) + * Running as a Xen PV DomU: NO + > STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not affected) + + CVE-2018-3640 aka Variant 3a, rogue system register read + * CPU microcode mitigates the vulnerability: NO + > STATUS: VULNERABLE (an up-to-date CPU microcode is needed to mitigate this vulnerability) + + CVE-2018-3639 aka Variant 4, speculative store bypass + * Mitigated according to the /sys interface: NO (Vulnerable) + > STATUS: VULNERABLE (Neither your CPU nor your kernel support SSBD) + + CVE-2018-3615 aka Foreshadow (SGX), L1 terminal fault + * CPU microcode mitigates the vulnerability: N/A + > STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not affected) + + CVE-2018-3620 aka Foreshadow-NG (OS), L1 terminal fault + * Mitigated according to the /sys interface: YES (Not affected) + > STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not affected) + + CVE-2018-3646 aka Foreshadow-NG (VMM), L1 terminal fault + * Information from the /sys interface: Not affected + > STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not affected) + + CVE-2018-12126 aka Fallout, microarchitectural store buffer data sampling (MSBDS) + * Mitigated according to the /sys interface: YES (Not affected) + > STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not affected) + + CVE-2018-12130 aka ZombieLoad, microarchitectural fill buffer data sampling (MFBDS) + * Mitigated according to the /sys interface: YES (Not affected) + > STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not affected) + + CVE-2018-12127 aka RIDL, microarchitectural load port data sampling (MLPDS) + * Mitigated according to the /sys interface: YES (Not affected) + > STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not affected) + + CVE-2019-11091 aka RIDL, microarchitectural data sampling uncacheable memory (MDSUM) + * Mitigated according to the /sys interface: YES (Not affected) + > STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not affected) + + CVE-2019-11135 aka ZombieLoad V2, TSX Asynchronous Abort (TAA) + * Mitigated according to the /sys interface: YES (Not affected) + > STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not affected) + + CVE-2018-12207 aka No eXcuses, iTLB Multihit, machine check exception on page size changes (MCEPSC) + * Mitigated according to the /sys interface: YES (Not affected) + > STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not affected) + + CVE-2020-0543 aka Special Register Buffer Data Sampling (SRBDS) + * Mitigated according to the /sys interface: YES (Not affected) + > STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not affected) + + > SUMMARY: CVE-2017-5753:?? CVE-2017-5715:KO CVE-2017-5754:OK CVE-2018-3640:KO CVE-2018-3639:KO CVE-2018-3615:OK CVE-2018-3620:OK CVE-2018-3646:OK CVE-2018-12126:OK CVE-2018-12130:OK CVE-2018-12127:OK CVE-2019-11091:OK CVE-2019-11135:OK CVE-2018-12207:OK CVE-2020-0543:OK diff --git a/docs/report/introduction/test_environment_sut_meltspec_tx2.rst b/docs/report/introduction/environment/sut_meltspec_tx2.rst index f12113a8bf..f12113a8bf 100644 --- a/docs/report/introduction/test_environment_sut_meltspec_tx2.rst +++ b/docs/report/introduction/environment/sut_meltspec_tx2.rst diff --git a/docs/report/introduction/environment/sut_meltspec_zn2.rst b/docs/report/introduction/environment/sut_meltspec_zn2.rst new file mode 100644 index 0000000000..160585dac1 --- /dev/null +++ b/docs/report/introduction/environment/sut_meltspec_zn2.rst @@ -0,0 +1,117 @@ +Spectre and Meltdown Checks +^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +Following section displays the output of a running shell script to tell if +system is vulnerable against the several speculative execution CVEs that were +made public in 2018. Script is available on `Spectre & Meltdown Checker Github +<https://github.com/speed47/spectre-meltdown-checker>`_. + +:: + + Spectre and Meltdown mitigation detection tool v0.45 + + Checking for vulnerabilities on current system + Kernel is Linux 5.15.0-46-generic #49-Ubuntu SMP Thu Aug 4 18:03:25 UTC 2022 x86_64 + CPU is AMD EPYC 7532 32-Core Processor + + Hardware check + * Hardware support (CPU microcode) for mitigation techniques + * Indirect Branch Restricted Speculation (IBRS) + * SPEC_CTRL MSR is available: YES + * CPU indicates IBRS capability: YES (IBRS_SUPPORT feature bit) + * CPU indicates preferring IBRS always-on: NO + * CPU indicates preferring IBRS over retpoline: YES + * Indirect Branch Prediction Barrier (IBPB) + * CPU indicates IBPB capability: YES (IBPB_SUPPORT feature bit) + * Single Thread Indirect Branch Predictors (STIBP) + * SPEC_CTRL MSR is available: YES + * CPU indicates STIBP capability: YES (AMD STIBP feature bit) + * CPU indicates preferring STIBP always-on: NO + * Speculative Store Bypass Disable (SSBD) + * CPU indicates SSBD capability: YES (AMD SSBD in SPEC_CTRL) + * L1 data cache invalidation + * CPU indicates L1D flush capability: NO + * CPU supports Transactional Synchronization Extensions (TSX): NO + * CPU supports Software Guard Extensions (SGX): NO + * CPU supports Special Register Buffer Data Sampling (SRBDS): NO + * CPU microcode is known to cause stability problems: NO (family 0x17 model 0x31 stepping 0x0 ucode 0x8301038 cpuid 0x830f10) + * CPU microcode is the latest known available version: NO (latest version is 0x8301052 dated 2021/11/11 according to builtin firmwares DB v222+i20220208) + * CPU vulnerability to the speculative execution attack variants + * Affected by CVE-2017-5753 (Spectre Variant 1, bounds check bypass): YES + * Affected by CVE-2017-5715 (Spectre Variant 2, branch target injection): YES + * Affected by CVE-2017-5754 (Variant 3, Meltdown, rogue data cache load): NO + * Affected by CVE-2018-3640 (Variant 3a, rogue system register read): NO + * Affected by CVE-2018-3639 (Variant 4, speculative store bypass): YES + * Affected by CVE-2018-3615 (Foreshadow (SGX), L1 terminal fault): NO + * Affected by CVE-2018-3620 (Foreshadow-NG (OS), L1 terminal fault): NO + * Affected by CVE-2018-3646 (Foreshadow-NG (VMM), L1 terminal fault): NO + * Affected by CVE-2018-12126 (Fallout, microarchitectural store buffer data sampling (MSBDS)): NO + * Affected by CVE-2018-12130 (ZombieLoad, microarchitectural fill buffer data sampling (MFBDS)): NO + * Affected by CVE-2018-12127 (RIDL, microarchitectural load port data sampling (MLPDS)): NO + * Affected by CVE-2019-11091 (RIDL, microarchitectural data sampling uncacheable memory (MDSUM)): NO + * Affected by CVE-2019-11135 (ZombieLoad V2, TSX Asynchronous Abort (TAA)): NO + * Affected by CVE-2018-12207 (No eXcuses, iTLB Multihit, machine check exception on page size changes (MCEPSC)): NO + * Affected by CVE-2020-0543 (Special Register Buffer Data Sampling (SRBDS)): NO + + CVE-2017-5753 aka Spectre Variant 1, bounds check bypass + * Mitigated according to the /sys interface: YES (Mitigation: usercopy/swapgs barriers and __user pointer sanitization) + > STATUS: UNKNOWN (/sys vulnerability interface use forced, but its not available!) + + CVE-2017-5715 aka Spectre Variant 2, branch target injection + * Mitigated according to the /sys interface: YES (Mitigation: Retpolines, IBPB: conditional, IBRS_FW, STIBP: always-on, RSB filling) + > STATUS: VULNERABLE (retpoline+IBPB is needed to mitigate the vulnerability) + + CVE-2017-5754 aka Variant 3, Meltdown, rogue data cache load + * Mitigated according to the /sys interface: YES (Not affected) + * Running as a Xen PV DomU: NO + > STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not affected) + + CVE-2018-3640 aka Variant 3a, rogue system register read + * CPU microcode mitigates the vulnerability: YES + > STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not affected) + + CVE-2018-3639 aka Variant 4, speculative store bypass + * Mitigated according to the /sys interface: YES (Mitigation: Speculative Store Bypass disabled via prctl and seccomp) + > STATUS: NOT VULNERABLE (Mitigation: Speculative Store Bypass disabled via prctl and seccomp) + + CVE-2018-3615 aka Foreshadow (SGX), L1 terminal fault + * CPU microcode mitigates the vulnerability: N/A + > STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not affected) + + CVE-2018-3620 aka Foreshadow-NG (OS), L1 terminal fault + * Mitigated according to the /sys interface: YES (Not affected) + > STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not affected) + + CVE-2018-3646 aka Foreshadow-NG (VMM), L1 terminal fault + * Information from the /sys interface: Not affected + > STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not affected) + + CVE-2018-12126 aka Fallout, microarchitectural store buffer data sampling (MSBDS) + * Mitigated according to the /sys interface: YES (Not affected) + > STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not affected) + + CVE-2018-12130 aka ZombieLoad, microarchitectural fill buffer data sampling (MFBDS) + * Mitigated according to the /sys interface: YES (Not affected) + > STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not affected) + + CVE-2018-12127 aka RIDL, microarchitectural load port data sampling (MLPDS) + * Mitigated according to the /sys interface: YES (Not affected) + > STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not affected) + + CVE-2019-11091 aka RIDL, microarchitectural data sampling uncacheable memory (MDSUM) + * Mitigated according to the /sys interface: YES (Not affected) + > STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not affected) + + CVE-2019-11135 aka ZombieLoad V2, TSX Asynchronous Abort (TAA) + * Mitigated according to the /sys interface: YES (Not affected) + > STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not affected) + + CVE-2018-12207 aka No eXcuses, iTLB Multihit, machine check exception on page size changes (MCEPSC) + * Mitigated according to the /sys interface: YES (Not affected) + > STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not affected) + + CVE-2020-0543 aka Special Register Buffer Data Sampling (SRBDS) + * Mitigated according to the /sys interface: YES (Not affected) + > STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not affected) + + > SUMMARY: CVE-2017-5753:?? CVE-2017-5715:KO CVE-2017-5754:OK CVE-2018-3640:OK CVE-2018-3639:OK CVE-2018-3615:OK CVE-2018-3620:OK CVE-2018-3646:OK CVE-2018-12126:OK CVE-2018-12130:OK CVE-2018-12127:OK CVE-2019-11091:OK CVE-2019-11135:OK CVE-2018-12207:OK CVE-2020-0543:OK
\ No newline at end of file diff --git a/docs/report/introduction/test_environment_tg.rst b/docs/report/introduction/environment/tg.rst index 411af83eb5..411af83eb5 100644 --- a/docs/report/introduction/test_environment_tg.rst +++ b/docs/report/introduction/environment/tg.rst diff --git a/docs/report/introduction/index.rst b/docs/report/introduction/index.rst index a15a18fd9d..4a80a148fb 100644 --- a/docs/report/introduction/index.rst +++ b/docs/report/introduction/index.rst @@ -8,4 +8,4 @@ Introduction test_scenarios_overview physical_testbeds methodology - documentation/index + documentation diff --git a/docs/report/introduction/introduction.rst b/docs/report/introduction/introduction.rst index 35b819d9e5..88e11665b0 100644 --- a/docs/report/introduction/introduction.rst +++ b/docs/report/introduction/introduction.rst @@ -113,7 +113,5 @@ available for download. - **Design**: Framework modular design hierarchy. - **Test naming**: Test naming convention. - - **Presentation and Analytics Layer**: Description of PAL CSIT - analytics module. - **CSIT RF Tags Descriptions**: CSIT RF Tags used for test suite and test case grouping and selection. diff --git a/docs/report/introduction/methodology_aws/aws_terraform.rst b/docs/report/introduction/methodology_aws/aws_terraform.rst index 4b063d5ee4..4d47b1e6d8 100644 --- a/docs/report/introduction/methodology_aws/aws_terraform.rst +++ b/docs/report/introduction/methodology_aws/aws_terraform.rst @@ -4,9 +4,7 @@ AWS Deployments CSIT performance testbed deployments in AWS rely on Infrastructure-as-a-C (IaaC) Terraform AWS providers. Terraform providers specified in CSIT interact with resources provided by AWS to -orchestrate virtual environment for running CSIT performance tests. For -more information, see -`Terraform Registry aws <https://registry.terraform.io/providers/hashicorp/aws/latest/>`_. +orchestrate virtual environment for running CSIT performance tests. Compatibility ~~~~~~~~~~~~~ diff --git a/docs/report/introduction/methodology_data_plane_throughput/methodology_mlrsearch_tests.rst b/docs/report/introduction/methodology_data_plane_throughput/methodology_mlrsearch_tests.rst index 5457daa555..6789dc073b 100644 --- a/docs/report/introduction/methodology_data_plane_throughput/methodology_mlrsearch_tests.rst +++ b/docs/report/introduction/methodology_data_plane_throughput/methodology_mlrsearch_tests.rst @@ -16,7 +16,7 @@ with zero packet loss, PLR=0) and Partial Drop Rate (PDR, with packet loss rate not greater than the configured non-zero PLR, currently 0.5%). MLRsearch discovers all the rates in a single pass, reducing required time -duration compared to separate `binary search`_es for each rate. Overall +duration compared to separate `binary search`_ for each rate. Overall search time is reduced even further by relying on shorter trial durations of intermediate steps, with only the final measurements conducted at the specified final trial duration. This results in the diff --git a/docs/report/introduction/methodology_data_plane_throughput/methodology_plrsearch.rst b/docs/report/introduction/methodology_data_plane_throughput/methodology_plrsearch.rst index 68f30bc562..d60e9203ff 100644 --- a/docs/report/introduction/methodology_data_plane_throughput/methodology_plrsearch.rst +++ b/docs/report/introduction/methodology_data_plane_throughput/methodology_plrsearch.rst @@ -1,7 +1,7 @@ .. _plrsearch: PLRsearch -^^^^^^^^^ +--------- Motivation for PLRsearch ~~~~~~~~~~~~~~~~~~~~~~~~ diff --git a/docs/report/introduction/methodology_telemetry.rst b/docs/report/introduction/methodology_telemetry.rst index dcd2d06541..c10f99affe 100644 --- a/docs/report/introduction/methodology_telemetry.rst +++ b/docs/report/introduction/methodology_telemetry.rst @@ -37,7 +37,8 @@ Telemetry module in CSIT currently support only Gauge, Counter and Info. Example metric file ~~~~~~~~~~~~~~~~~~~ -``` +:: + # HELP calls_total Number of calls total # TYPE calls_total counter calls_total{name="api-rx-from-ring",state="active",thread_id="0",thread_lcore="1",thread_name="vpp_main"} 0.0 @@ -60,7 +61,7 @@ Example metric file calls_total{name="ip4-lookup",state="active",thread_id="2",thread_lcore="0",thread_name="vpp_wk_1"} 91.0 calls_total{name="ip4-rewrite",state="active",thread_id="2",thread_lcore="0",thread_name="vpp_wk_1"} 91.0 calls_total{name="unix-epoll-input",state="polling",thread_id="2",thread_lcore="0",thread_name="vpp_wk_1"} 1.0 -``` + Anatomy of existing CSIT telemetry implementation ------------------------------------------------- @@ -81,7 +82,8 @@ them. MRR measurement ~~~~~~~~~~~~~~~ -``` +:: + traffic_start(r=mrr) traffic_stop |< measure >| | | | (r=mrr) | | pre_run_stat post_run_stat | pre_stat | | post_stat @@ -89,23 +91,23 @@ MRR measurement --o--------o---------------o---------o-------o--------+-------------------+------o------------> t -Legend: - - pre_run_stat - - vpp-clear-runtime - - post_run_stat - - vpp-show-runtime - - bash-perf-stat // if extended_debug == True - - pre_stat - - vpp-clear-stats - - vpp-enable-packettrace // if extended_debug == True - - vpp-enable-elog - - post_stat - - vpp-show-stats - - vpp-show-packettrace // if extended_debug == True - - vpp-show-elog -``` - -``` + Legend: + - pre_run_stat + - vpp-clear-runtime + - post_run_stat + - vpp-show-runtime + - bash-perf-stat // if extended_debug == True + - pre_stat + - vpp-clear-stats + - vpp-enable-packettrace // if extended_debug == True + - vpp-enable-elog + - post_stat + - vpp-show-stats + - vpp-show-packettrace // if extended_debug == True + - vpp-show-elog + +:: + |< measure >| | (r=mrr) | | | @@ -114,12 +116,13 @@ Legend: | | | | --o------------------------o------------------------o------------------------o---> t -``` + MLR measurement ~~~~~~~~~~~~~~~ -``` +:: + |< measure >| traffic_start(r=pdr) traffic_stop traffic_start(r=ndr) traffic_stop |< [ latency ] >| | (r=mlr) | | | | | | .9/.5/.1/.0 | | | | pre_run_stat post_run_stat | | pre_run_stat post_run_stat | | | @@ -127,21 +130,20 @@ MLR measurement --+-------------------+----o--------o---------------o---------o--------------o--------o---------------o---------o------------[---------------------]---> t -Legend: - - pre_run_stat - - vpp-clear-runtime - - post_run_stat - - vpp-show-runtime - - bash-perf-stat // if extended_debug == True - - pre_stat - - vpp-clear-stats - - vpp-enable-packettrace // if extended_debug == True - - vpp-enable-elog - - post_stat - - vpp-show-stats - - vpp-show-packettrace // if extended_debug == True - - vpp-show-elog -``` + Legend: + - pre_run_stat + - vpp-clear-runtime + - post_run_stat + - vpp-show-runtime + - bash-perf-stat // if extended_debug == True + - pre_stat + - vpp-clear-stats + - vpp-enable-packettrace // if extended_debug == True + - vpp-enable-elog + - post_stat + - vpp-show-stats + - vpp-show-packettrace // if extended_debug == True + - vpp-show-elog Improving existing solution @@ -171,7 +173,8 @@ integration with post processing module. MRR measurement ~~~~~~~~~~~~~~~ -``` +:: + traffic_start(r=mrr) traffic_stop |< measure >| | | | (r=mrr) | | |< stat_runtime >| | stat_pre_trial | | stat_post_trial @@ -179,18 +182,19 @@ MRR measurement ----o---+--------------------------+---o-------------o------------+-------------------+-----o-------------> t -Legend: - - stat_runtime - - vpp-runtime - - stat_pre_trial - - vpp-clear-stats - - vpp-enable-packettrace // if extended_debug == True - - stat_post_trial - - vpp-show-stats - - vpp-show-packettrace // if extended_debug == True -``` - -``` + Legend: + - stat_runtime + - vpp-runtime + - stat_pre_trial + - vpp-clear-stats + - vpp-enable-packettrace // if extended_debug == True + - stat_post_trial + - vpp-show-stats + - vpp-show-packettrace // if extended_debug == True + + +:: + |< measure >| | (r=mrr) | | | @@ -199,9 +203,9 @@ Legend: | | | | --o------------------------o------------------------o------------------------o---> t -``` -``` +:: + |< stat_runtime >| | | |< program0 >|< program1 >|< programN >| @@ -209,13 +213,13 @@ Legend: | | | | --o------------------------o------------------------o------------------------o---> t -``` MLR measurement ~~~~~~~~~~~~~~~ -``` +:: + |< measure >| traffic_start(r=pdr) traffic_stop traffic_start(r=ndr) traffic_stop |< [ latency ] >| | (r=mlr) | | | | | | .9/.5/.1/.0 | | | | |< stat_runtime >| | | |< stat_runtime >| | | | @@ -223,281 +227,12 @@ MLR measurement --+-------------------+-----o---+--------------------------+---o--------------o---+--------------------------+---o-----------[---------------------]---> t -Legend: - - stat_runtime - - vpp-runtime - - stat_pre_trial - - vpp-clear-stats - - vpp-enable-packettrace // if extended_debug == True - - stat_post_trial - - vpp-show-stats - - vpp-show-packettrace // if extended_debug == True -``` - - -Tooling -------- - -Prereqisities: -- bpfcc-tools -- python-bpfcc -- libbpfcc -- libbpfcc-dev -- libclang1-9 libllvm9 - -```bash - $ sudo apt install bpfcc-tools python3-bpfcc libbpfcc libbpfcc-dev libclang1-9 libllvm9 -``` - - -Configuration -------------- - -```yaml - logging: - version: 1 - formatters: - console: - format: '%(asctime)s - %(name)s - %(levelname)s - %(message)s' - prom: - format: '%(message)s' - handlers: - console: - class: logging.StreamHandler - level: INFO - formatter: console - stream: ext://sys.stdout - prom: - class: logging.handlers.RotatingFileHandler - level: INFO - formatter: prom - filename: /tmp/metric.prom - mode: w - loggers: - prom: - handlers: [prom] - level: INFO - propagate: False - root: - level: INFO - handlers: [console] - scheduler: - duration: 1 - programs: - - name: bundle_bpf - metrics: - counter: - - name: cpu_cycle - documentation: Cycles processed by CPUs - namespace: bpf - labelnames: - - name - - cpu - - pid - - name: cpu_instruction - documentation: Instructions retired by CPUs - namespace: bpf - labelnames: - - name - - cpu - - pid - - name: llc_reference - documentation: Last level cache operations by type - namespace: bpf - labelnames: - - name - - cpu - - pid - - name: llc_miss - documentation: Last level cache operations by type - namespace: bpf - labelnames: - - name - - cpu - - pid - events: - - type: 0x0 # HARDWARE - name: 0x0 # PERF_COUNT_HW_CPU_CYCLES - target: on_cpu_cycle - table: cpu_cycle - - type: 0x0 # HARDWARE - name: 0x1 # PERF_COUNT_HW_INSTRUCTIONS - target: on_cpu_instruction - table: cpu_instruction - - type: 0x0 # HARDWARE - name: 0x2 # PERF_COUNT_HW_CACHE_REFERENCES - target: on_cache_reference - table: llc_reference - - type: 0x0 # HARDWARE - name: 0x3 # PERF_COUNT_HW_CACHE_MISSES - target: on_cache_miss - table: llc_miss - code: | - #include <linux/ptrace.h> - #include <uapi/linux/bpf_perf_event.h> - - const int max_cpus = 256; - - struct key_t { - int cpu; - int pid; - char name[TASK_COMM_LEN]; - }; - - BPF_HASH(llc_miss, struct key_t); - BPF_HASH(llc_reference, struct key_t); - BPF_HASH(cpu_instruction, struct key_t); - BPF_HASH(cpu_cycle, struct key_t); - - static inline __attribute__((always_inline)) void get_key(struct key_t* key) { - key->cpu = bpf_get_smp_processor_id(); - key->pid = bpf_get_current_pid_tgid(); - bpf_get_current_comm(&(key->name), sizeof(key->name)); - } - - int on_cpu_cycle(struct bpf_perf_event_data *ctx) { - struct key_t key = {}; - get_key(&key); - - cpu_cycle.increment(key, ctx->sample_period); - return 0; - } - int on_cpu_instruction(struct bpf_perf_event_data *ctx) { - struct key_t key = {}; - get_key(&key); - - cpu_instruction.increment(key, ctx->sample_period); - return 0; - } - int on_cache_reference(struct bpf_perf_event_data *ctx) { - struct key_t key = {}; - get_key(&key); - - llc_reference.increment(key, ctx->sample_period); - return 0; - } - int on_cache_miss(struct bpf_perf_event_data *ctx) { - struct key_t key = {}; - get_key(&key); - - llc_miss.increment(key, ctx->sample_period); - return 0; - } -``` - -CSIT captured metrics ---------------------- - -SUT -~~~ - -Compute resource -________________ - -- BPF /process - - BPF_HASH(llc_miss, struct key_t); - - BPF_HASH(llc_reference, struct key_t); - - BPF_HASH(cpu_instruction, struct key_t); - - BPF_HASH(cpu_cycle, struct key_t); - -Memory resource -_______________ - -- BPF /process - - tbd - -Network resource -________________ - -- BPF /process - - tbd - -DUT VPP metrics -~~~~~~~~~~~~~~~ - -Compute resource -________________ - -- runtime /node `show runtime` - - calls - - vectors - - suspends - - clocks - - vectors_calls -- perfmon /bundle - - inst-and-clock node intel-core instructions/packet, cycles/packet and IPC - - cache-hierarchy node intel-core cache hits and misses - - context-switches thread linux per-thread context switches - - branch-mispred node intel-core Branches, branches taken and mis-predictions - - page-faults thread linux per-thread page faults - - load-blocks node intel-core load operations blocked due to various uarch reasons - - power-licensing node intel-core Thread power licensing - - memory-bandwidth system intel-uncore memory reads and writes per memory controller channel - -Memory resource - tbd -_____________________ - -- memory /segment `show memory verbose api-segment stats-segment main-heap` - - total - - used - - free - - trimmable - - free-chunks - - free-fastbin-blks - - max-total-allocated -- physmem `show physmem` - - pages - - subpage-size - -Network resource -________________ - -- counters /node `show node counters` - - count - - severity -- hardware /interface `show interface` - - rx_stats - - tx_stats -- packets /interface `show hardware` - - rx_packets - - rx_bytes - - rx_errors - - tx_packets - - tx_bytes - - tx_errors - - drops - - punt - - ip4 - - ip6 - - rx_no_buf - - rx_miss - - -DUT DPDK metrics - tbd -~~~~~~~~~~~~~~~~~~~~~~ - -Compute resource -________________ - -- BPF /process - - BPF_HASH(llc_miss, struct key_t); - - BPF_HASH(llc_reference, struct key_t); - - BPF_HASH(cpu_instruction, struct key_t); - - BPF_HASH(cpu_cycle, struct key_t); - -Memory resource -_______________ - -- BPF /process - - tbd - -Network resource -________________ - -- packets /interface - - inPackets - - outPackets - - inBytes - - outBytes - - outErrorPackets - - dropPackets + Legend: + - stat_runtime + - vpp-runtime + - stat_pre_trial + - vpp-clear-stats + - vpp-enable-packettrace // if extended_debug == True + - stat_post_trial + - vpp-show-stats + - vpp-show-packettrace // if extended_debug == True diff --git a/docs/report/introduction/physical_testbeds.rst b/docs/report/introduction/physical_testbeds.rst index 343e4b3010..2497de88b9 100644 --- a/docs/report/introduction/physical_testbeds.rst +++ b/docs/report/introduction/physical_testbeds.rst @@ -26,9 +26,9 @@ Two physical server topology types are used: Current FD.io production testbeds are built with SUT servers based on the following processor architectures: -- Intel Xeon: Skylake Platinum 8180, Cascadelake 6252N, Icelake 8358. -- Intel Atom: Denverton C3858. -- Arm: TaiShan 2280, hip07-d05. +- Intel Xeon: Cascadelake 6252N, Icelake 8358. +- Intel Atom: Denverton C3858, Snowridge P5362. +- Arm: TaiShan 2280, hip07-d05, Neoverse N1. - AMD EPYC: Zen2 7532. Server SUT performance depends on server and processor type, hence @@ -56,6 +56,13 @@ VPP is performance tested on SUTs with the following NICs and drivers: - DPDK PMD. - AVF in PMD mode. - AF_XDP in PMD mode. +#. 4p25GE: xxv710-DA4 Intel (codename Fortville, FVL) + - DPDK PMD. + - AVF in PMD mode. + - AF_XDP in PMD mode. +#. 4p25GE: E822-CQDA4 Intel (codename Columbiaville, CVL) + - DPDK PMD. + - AVF in PMD mode. #. 2p100GE: cx556a-edat Mellanox ConnectX5 - RDMA_core in PMD mode. #. 2p100GE: E810-2CQDA2 Intel (codename Columbiaville, CVL) @@ -73,6 +80,8 @@ running on TGs and using Linux drivers for all NICs. For more information see :ref:`vpp_test_environment` and :ref:`dpdk_test_environment`. +.. _physical_testbeds_2n_zn2: + 2-Node AMD EPYC Zen2 (2n-zn2) ----------------------------- @@ -113,6 +122,8 @@ TG NICs: All AMD EPYC Zen2 7532 servers run with AMD SMT enabled, doubling the number of logical cores exposed to Linux. +.. _physical_testbeds_2n_clx: + 2-Node Xeon Cascadelake (2n-clx) -------------------------------- @@ -230,6 +241,8 @@ SUT and TG NICs: All Intel Xeon Icelake servers run with Intel Hyper-Threading enabled, doubling the number of logical cores exposed to Linux. +.. _physical_testbeds_2n_dnv: + 2-Node Atom Denverton (2n-dnv) ------------------------------ @@ -272,6 +285,8 @@ TG NICs: The 2n-dnv testbed is in operation in Intel SH labs. +.. _physical_testbeds_3n_dnv: + 3-Node Atom Denverton (3n-dnv) ------------------------------ @@ -347,6 +362,8 @@ TG NICs: #. NIC-3: e810-XXVDA4-4p25GE Intel. #. NIC-4: e810-2CQDA2-2p100GE Intel. +.. _physical_testbeds_3n_tsh: + 3-Node ARM TaiShan (3n-tsh) --------------------------- @@ -384,6 +401,8 @@ TG NICs: #. NIC-2: xxv710-DA2 2p25GE Intel. #. NIC-3: xl710-QDA2 2p40GE Intel. +.. _physical_testbeds_2n_tx2: + 2-Node ARM ThunderX2 (2n-tx2) ----------------------------- @@ -418,3 +437,39 @@ SUT NICs: TG NICs: #. NIC-1: xl710-QDA2 2p40GE Intel. + +.. _physical_testbeds_3n_snr: + +3-Node Atom Snowridge (3n-snr) +------------------------------ + +One 3n-snr testbed is built with: i) one SuperMicro SYS-740GP-TNRT +server acting as TG and equipped with two Intel Xeon Icelake Platinum +8358 processors (48 MB Cache, 2.60 GHz, 32 cores), and ii) SUT equipped with +one Intel Atom P5362 processor (27 MB Cache, 2.20 GHz, 24 cores). 3n-snr +physical topology is shown below. + +.. only:: latex + + .. raw:: latex + + \begin{figure}[H] + \centering + \graphicspath{{../_tmp/src/introduction/}} + \includegraphics[width=0.90\textwidth]{testbed-3n-snr} + \label{fig:testbed-3n-snr} + \end{figure} + +.. only:: html + + .. figure:: testbed-3n-snr.svg + :alt: testbed-3n-snr + :align: center + +SUT1 and SUT2 NICs: + +#. NIC-1: e822cq-DA4 4p25GE fiber Intel. + +TG NICs: + +#. NIC-1: e810xxv-DA4 4p25GE Intel. diff --git a/docs/report/introduction/test_environment_sut_calib_alt.rst b/docs/report/introduction/test_environment_sut_calib_alt.rst deleted file mode 100644 index dae1d1bf14..0000000000 --- a/docs/report/introduction/test_environment_sut_calib_alt.rst +++ /dev/null @@ -1,25 +0,0 @@ -Altra -~~~~~ - -Following sections include sample calibration data measured on -s62-t34-sut1 server running in one of the Altra testbeds. - - -Linux cmdline -^^^^^^^^^^^^^ - -:: - - $ cat /proc/cmdline - BOOT_IMAGE=/vmlinuz-5.4.0-65-generic root=/dev/mapper/ubuntu--vg-ubuntu--lv ro audit=0 default_hugepagesz=2M hugepagesz=1G hugepages=32 hugepagesz=2M hugepages=32768 iommu.passthrough=1 isolcpus=1-40,81-120 nmi_watchdog=0 nohz_full=1-40,81-120 nosoftlockup processor.max_cstate=1 rcu_nocbs=1-40,81-120 - -Linux uname -^^^^^^^^^^^ - -:: - - $ uname -a - Linux s62-t34-sut1 5.4.0-65-generic #73-Ubuntu SMP Mon Jan 18 17:27:25 UTC 2021 aarch64 aarch64 aarch64 GNU/Linux - - -.. include:: ../introduction/test_environment_sut_meltspec_alt.rst diff --git a/docs/report/introduction/test_environment_sut_calib_clx.rst b/docs/report/introduction/test_environment_sut_calib_clx.rst deleted file mode 100644 index ef4812d2e1..0000000000 --- a/docs/report/introduction/test_environment_sut_calib_clx.rst +++ /dev/null @@ -1,224 +0,0 @@ -Cascade Lake -~~~~~~~~~~~~ - -Following sections include sample calibration data measured on -s32-t27-sut1 server running in one of the Intel Xeon Skylake testbeds as -specified in `FD.io CSIT testbeds - Xeon Cascade Lake`_. - -Calibration data obtained from all other servers in Cascade Lake testbeds -shows the same or similar values. - - -Linux cmdline -^^^^^^^^^^^^^ - -:: - - $ cat /proc/cmdline - BOOT_IMAGE=/boot/vmlinuz-5.4.0-65-generic root=UUID=b1f0dc29-1d4f-4777-b37d-a5e26e233d55 ro audit=0 hpet=disable intel_idle.max_cstate=1 intel_iommu=on intel_pstate=disable iommu=pt isolcpus=1-27,29-55,57-83,85-111 mce=off nmi_watchdog=0 nohz_full=1-27,29-55,57-83,85-111 nosoftlockup numa_balancing=disable processor.max_cstate=1 rcu_nocbs=1-27,29-55,57-83,85-111 tsc=reliable console=ttyS0,115200n8 quiet - -Linux uname -^^^^^^^^^^^ - -:: - - $ uname -a - Linux 5.4.0-65-generic #73-Ubuntu SMP Mon Jan 18 17:25:17 UTC 2021 x86_64 x86_64 x86_64 GNU/Linux - - -System-level Core Jitter -^^^^^^^^^^^^^^^^^^^^^^^^ - -:: - - $ sudo taskset -c 3 /home/testuser/pma_tools/jitter/jitter -i 30 - Linux Jitter testing program version 1.9 - Iterations=30 - The pragram will execute a dummy function 80000 times - Display is updated every 20000 displayUpdate intervals - Thread affinity will be set to core_id:7 - Timings are in CPU Core cycles - Inst_Min: Minimum Excution time during the display update interval(default is ~1 second) - Inst_Max: Maximum Excution time during the display update interval(default is ~1 second) - Inst_jitter: Jitter in the Excution time during rhe display update interval. This is the value of interest - last_Exec: The Excution time of last iteration just before the display update - Abs_Min: Absolute Minimum Excution time since the program started or statistics were reset - Abs_Max: Absolute Maximum Excution time since the program started or statistics were reset - tmp: Cumulative value calcualted by the dummy function - Interval: Time interval between the display updates in Core Cycles - Sample No: Sample number - - Inst_Min,Inst_Max,Inst_jitter,last_Exec,Abs_min,Abs_max,tmp,Interval,Sample No - 160022,167590,7568,160026,160022,167590,2057568256,3203711852,1 - 160022,170628,10606,160024,160022,170628,4079222784,3204010824,2 - 160022,169824,9802,160024,160022,170628,1805910016,3203812064,3 - 160022,168832,8810,160030,160022,170628,3827564544,3203792594,4 - 160022,168248,8226,160026,160022,170628,1554251776,3203765920,5 - 160022,167834,7812,160028,160022,170628,3575906304,3203761114,6 - 160022,167442,7420,160024,160022,170628,1302593536,3203769250,7 - 160022,169120,9098,160028,160022,170628,3324248064,3203853340,8 - 160022,170710,10688,160024,160022,170710,1050935296,3203985878,9 - 160022,167952,7930,160024,160022,170710,3072589824,3203733756,10 - 160022,168314,8292,160030,160022,170710,799277056,3203741152,11 - 160022,169672,9650,160024,160022,170710,2820931584,3203739910,12 - 160022,168684,8662,160024,160022,170710,547618816,3203727336,13 - 160022,168246,8224,160024,160022,170710,2569273344,3203739052,14 - 160022,168134,8112,160030,160022,170710,295960576,3203735874,15 - 160022,170230,10208,160024,160022,170710,2317615104,3203996356,16 - 160022,167190,7168,160024,160022,170710,44302336,3203713628,17 - 160022,167304,7282,160024,160022,170710,2065956864,3203717954,18 - 160022,167500,7478,160024,160022,170710,4087611392,3203706674,19 - 160022,167302,7280,160024,160022,170710,1814298624,3203726452,20 - 160022,167266,7244,160024,160022,170710,3835953152,3203702804,21 - 160022,167820,7798,160022,160022,170710,1562640384,3203719138,22 - 160022,168100,8078,160024,160022,170710,3584294912,3203716636,23 - 160022,170408,10386,160024,160022,170710,1310982144,3203946958,24 - 160022,167276,7254,160024,160022,170710,3332636672,3203706236,25 - 160022,167052,7030,160024,160022,170710,1059323904,3203696444,26 - 160022,170322,10300,160024,160022,170710,3080978432,3203747514,27 - 160022,167332,7310,160024,160022,170710,807665664,3203716210,28 - 160022,167426,7404,160026,160022,170710,2829320192,3203700630,29 - 160022,168840,8818,160024,160022,170710,556007424,3203727658,30 - - -Memory Bandwidth -^^^^^^^^^^^^^^^^ - -:: - - $ sudo /home/testuser/mlc --bandwidth_matrix - Intel(R) Memory Latency Checker - v3.7 - Command line parameters: --bandwidth_matrix - - Using buffer size of 100.000MiB/thread for reads and an additional 100.000MiB/thread for writes - Measuring Memory Bandwidths between nodes within system - Bandwidths are in MB/sec (1 MB/sec = 1,000,000 Bytes/sec) - Using all the threads from each core if Hyper-threading is enabled - Using Read-only traffic type - Numa node - Numa node 0 1 - 0 122097.7 51327.9 - 1 51309.2 122005.5 - -:: - - $ sudo /home/testuser/mlc --peak_injection_bandwidth - Intel(R) Memory Latency Checker - v3.7 - Command line parameters: --peak_injection_bandwidth - - Using buffer size of 100.000MiB/thread for reads and an additional 100.000MiB/thread for writes - - Measuring Peak Injection Memory Bandwidths for the system - Bandwidths are in MB/sec (1 MB/sec = 1,000,000 Bytes/sec) - Using all the threads from each core if Hyper-threading is enabled - Using traffic with the following read-write ratios - ALL Reads : 243159.4 - 3:1 Reads-Writes : 219132.5 - 2:1 Reads-Writes : 216603.1 - 1:1 Reads-Writes : 203713.0 - Stream-triad like: 193790.8 - -:: - - $ sudo /home/testuser/mlc --max_bandwidth - Intel(R) Memory Latency Checker - v3.7 - Command line parameters: --max_bandwidth - - Using buffer size of 100.000MiB/thread for reads and an additional 100.000MiB/thread for writes - - Measuring Maximum Memory Bandwidths for the system - Will take several minutes to complete as multiple injection rates will be tried to get the best bandwidth - Bandwidths are in MB/sec (1 MB/sec = 1,000,000 Bytes/sec) - Using all the threads from each core if Hyper-threading is enabled - Using traffic with the following read-write ratios - ALL Reads : 244114.27 - 3:1 Reads-Writes : 219441.97 - 2:1 Reads-Writes : 216603.72 - 1:1 Reads-Writes : 203679.09 - Stream-triad like: 214902.80 - - -Memory Latency -^^^^^^^^^^^^^^ - -:: - - $ sudo /home/testuser/mlc --latency_matrix - Intel(R) Memory Latency Checker - v3.7 - Command line parameters: --latency_matrix - - Using buffer size of 2000.000MiB - Measuring idle latencies (in ns)... - Numa node - Numa node 0 1 - 0 81.2 130.2 - 1 130.2 81.1 - -:: - - $ sudo /home/testuser/mlc --idle_latency - Intel(R) Memory Latency Checker - v3.7 - Command line parameters: --idle_latency - - Using buffer size of 2000.000MiB - Each iteration took 186.1 core clocks ( 80.9 ns) - -:: - - $ sudo /home/testuser/mlc --loaded_latency - Intel(R) Memory Latency Checker - v3.7 - Command line parameters: --loaded_latency - - Using buffer size of 100.000MiB/thread for reads and an additional 100.000MiB/thread for writes - - Measuring Loaded Latencies for the system - Using all the threads from each core if Hyper-threading is enabled - Using Read-only traffic type - Inject Latency Bandwidth - Delay (ns) MB/sec - ========================== - 00000 233.86 243421.9 - 00002 230.61 243544.1 - 00008 232.56 243394.5 - 00015 229.52 244076.6 - 00050 225.82 244290.6 - 00100 161.65 236744.8 - 00200 100.63 133844.0 - 00300 96.84 90548.2 - 00400 95.71 68504.3 - 00500 95.68 55139.0 - 00700 88.77 39798.4 - 01000 84.74 28200.1 - 01300 83.08 21915.5 - 01700 82.27 16969.3 - 02500 81.66 11810.6 - 03500 81.98 8662.9 - 05000 81.48 6306.8 - 09000 81.17 3857.8 - 20000 80.19 2179.9 - - -L1/L2/LLC Latency -^^^^^^^^^^^^^^^^^ - -:: - - $ sudo /home/testuser/mlc --c2c_latency - Intel(R) Memory Latency Checker - v3.7 - Command line parameters: --c2c_latency - - Measuring cache-to-cache transfer latency (in ns)... - Local Socket L2->L2 HIT latency 55.5 - Local Socket L2->L2 HITM latency 55.6 - Remote Socket L2->L2 HITM latency (data address homed in writer socket) - Reader Numa Node - Writer Numa Node 0 1 - 0 - 115.6 - 1 115.6 - - Remote Socket L2->L2 HITM latency (data address homed in reader socket) - Reader Numa Node - Writer Numa Node 0 1 - 0 - 178.2 - 1 178.4 - - -.. include:: ../introduction/test_environment_sut_meltspec_clx.rst diff --git a/docs/report/introduction/test_environment_sut_calib_dnv.rst b/docs/report/introduction/test_environment_sut_calib_dnv.rst deleted file mode 100644 index d38ba2fb8b..0000000000 --- a/docs/report/introduction/test_environment_sut_calib_dnv.rst +++ /dev/null @@ -1,203 +0,0 @@ -Denverton -~~~~~~~~~ - -Following sections include sample calibration data measured on -Denverton server at Intel SH labs. - -A 2-Node Atom Denverton testing took place at Intel Corporation carefully -adhering to FD.io CSIT best practices. - - -Linux cmdline -^^^^^^^^^^^^^ - -:: - - $ cat /proc/cmdline - BOOT_IMAGE=/boot/vmlinuz-5.4.0-65-generic root=UUID=26ca7b0f-904a-462d-a1c6-98c420c29515 ro audit=0 hpet=disable intel_idle.max_cstate=1 intel_iommu=on intel_pstate=disable iommu=pt isolcpus=1-5 mce=off nmi_watchdog=0 nohz_full=1-5 nosoftlockup numa_balancing=disable processor.max_cstate=1 rcu_nocbs=1-5 tsc=reliable console=tty0 console=ttyS0,115200n8 - - -Linux uname -^^^^^^^^^^^ - -:: - - $ uname -a - Linux 5.4.0-65-generic #73-Ubuntu SMP Mon Jan 18 17:25:17 UTC 2021 x86_64 x86_64 x86_64 GNU/Linux - - -System-level Core Jitter -^^^^^^^^^^^^^^^^^^^^^^^^ - -:: - - $ sudo taskset -c 2 /home/testuser/pma_tools/jitter/jitter -c 2 -i 20 - Linux Jitter testing program version 1.9 - Iterations=20 - The pragram will execute a dummy function 80000 times - Display is updated every 20000 displayUpdate intervals - Thread affinity will be set to core_id:2 - Timings are in CPU Core cycles - Inst_Min: Minimum Excution time during the display update interval(default is ~1 second) - Inst_Max: Maximum Excution time during the display update interval(default is ~1 second) - Inst_jitter: Jitter in the Excution time during rhe display update interval. This is the value of interest - last_Exec: The Excution time of last iteration just before the display update - Abs_Min: Absolute Minimum Excution time since the program started or statistics were reset - Abs_Max: Absolute Maximum Excution time since the program started or statistics were reset - tmp: Cumulative value calcualted by the dummy function - Interval: Time interval between the display updates in Core Cycles - Sample No: Sample number - - Inst_Min Inst_Max Inst_jitter last_Exec Abs_min Abs_max tmp Interval Sample No - 177530 196100 18570 177530 177530 196100 4156751872 3556820054 1 - 177530 200784 23254 177530 177530 200784 321060864 3556897644 2 - 177530 196346 18816 177530 177530 200784 780337152 3556918674 3 - 177530 195962 18432 177530 177530 200784 1239613440 3556847928 4 - 177530 195960 18430 177530 177530 200784 1698889728 3556860214 5 - 177530 198824 21294 177530 177530 200784 2158166016 3556854934 6 - 177530 198522 20992 177530 177530 200784 2617442304 3556862410 7 - 177530 196362 18832 177530 177530 200784 3076718592 3556851636 8 - 177530 199114 21584 177530 177530 200784 3535994880 3556870846 9 - 177530 197194 19664 177530 177530 200784 3995271168 3556933584 10 - 177530 198272 20742 177536 177530 200784 159580160 3556869044 11 - 177530 197586 20056 177530 177530 200784 618856448 3556903482 12 - 177530 196072 18542 177530 177530 200784 1078132736 3556825540 13 - 177530 196354 18824 177530 177530 200784 1537409024 3556881664 14 - 177530 195906 18376 177530 177530 200784 1996685312 3556839924 15 - 177530 199066 21536 177530 177530 200784 2455961600 3556860220 16 - 177530 196968 19438 177530 177530 200784 2915237888 3556871890 17 - 177530 195896 18366 177530 177530 200784 3374514176 3556855338 18 - 177530 196020 18490 177530 177530 200784 3833790464 3556839820 19 - 177530 196030 18500 177530 177530 200784 4293066752 3556889196 20 - - -Memory Bandwidth -^^^^^^^^^^^^^^^^ - -:: - - $ sudo /home/testuser/mlc --bandwidth_matrix - Intel(R) Memory Latency Checker - v3.5 - Command line parameters: --bandwidth_matrix - - Using buffer size of 100.000MB/thread for reads and an additional 100.000MB/thread for writes - Measuring Memory Bandwidths between nodes within system - Bandwidths are in MB/sec (1 MB/sec = 1,000,000 Bytes/sec) - Using all the threads from each core if Hyper-threading is enabled - Using Read-only traffic type - Memory node - Socket 0 - 0 28157.2 - -:: - - $ sudo /home/testuser/mlc --peak_injection_bandwidth - Intel(R) Memory Latency Checker - v3.5 - Command line parameters: --peak_injection_bandwidth - - Using buffer size of 100.000MB/thread for reads and an additional 100.000MB/thread for writes - - Measuring Peak Injection Memory Bandwidths for the system - Bandwidths are in MB/sec (1 MB/sec = 1,000,000 Bytes/sec) - Using all the threads from each core if Hyper-threading is enabled - Using traffic with the following read-write ratios - ALL Reads : 28150.0 - 3:1 Reads-Writes : 27425.0 - 2:1 Reads-Writes : 27565.4 - 1:1 Reads-Writes : 27489.3 - Stream-triad like: 26878.2 - -:: - - $ sudo /home/testuser/mlc --max_bandwidth - Intel(R) Memory Latency Checker - v3.5 - Command line parameters: --max_bandwidth - - Using buffer size of 100.000MB/thread for reads and an additional 100.000MB/thread for writes - - Measuring Maximum Memory Bandwidths for the system - Will take several minutes to complete as multiple injection rates will be tried to get the best bandwidth - Bandwidths are in MB/sec (1 MB/sec = 1,000,000 Bytes/sec) - Using all the threads from each core if Hyper-threading is enabled - Using traffic with the following read-write ratios - ALL Reads : 30032.40 - 3:1 Reads-Writes : 27450.88 - 2:1 Reads-Writes : 27567.46 - 1:1 Reads-Writes : 27501.90 - Stream-triad like: 27124.82 - - -Memory Latency -^^^^^^^^^^^^^^ - -:: - - $ sudo /home/testuser/mlc --latency_matrix - Intel(R) Memory Latency Checker - v3.5 - Command line parameters: --latency_matrix - - Using buffer size of 2000.000MB - Intel(R) Memory Latency Checker - v3.5 - Measuring idle latencies (in ns)... - Memory node - Socket 0 - 0 93.1 - -:: - - $ sudo /home/testuser/mlc --idle_latency - Intel(R) Memory Latency Checker - v3.5 - Command line parameters: --idle_latency - - Using buffer size of 200.000MB - Each iteration took 186.7 core clocks ( 93.4 ns) - -:: - - $ sudo /home/testuser/mlc --loaded_latency - Intel(R) Memory Latency Checker - v3.5 - Command line parameters: --loaded_latency - - Using buffer size of 100.000MB/thread for reads and an additional 100.000MB/thread for writes - - Measuring Loaded Latencies for the system - Using all the threads from each core if Hyper-threading is enabled - Using Read-only traffic type - Inject Latency Bandwidth - Delay (ns) MB/sec - ========================== - 00000 135.35 27186.0 - 00002 135.47 27176.9 - 00008 134.97 27063.3 - 00015 134.41 26825.6 - 00050 139.83 28419.1 - 00100 124.28 22616.4 - 00200 109.40 14139.8 - 00300 104.56 10275.1 - 00400 102.02 8120.0 - 00500 100.38 6751.4 - 00700 98.30 5124.9 - 01000 96.56 3852.7 - 01300 95.65 3149.0 - 01700 95.06 2585.4 - 02500 94.43 1988.8 - 03500 94.16 1621.1 - 05000 93.95 1343.1 - 09000 93.65 1052.6 - 20000 93.43 851.7 - - -L1/L2/LLC Latency -^^^^^^^^^^^^^^^^^ - -:: - - $ sudo /home/testuser/mlc --c2c_latency - Intel(R) Memory Latency Checker - v3.5 - Command line parameters: --c2c_latency - - Measuring cache-to-cache transfer latency (in ns)... - Local Socket L2->L2 HIT latency 8.8 - Local Socket L2->L2 HITM latency 8.8 - -.. include:: ../introduction/test_environment_sut_meltspec_dnv.rst diff --git a/docs/report/introduction/test_environment_sut_calib_icx.rst b/docs/report/introduction/test_environment_sut_calib_icx.rst deleted file mode 100644 index 39245ff8ae..0000000000 --- a/docs/report/introduction/test_environment_sut_calib_icx.rst +++ /dev/null @@ -1,73 +0,0 @@ -Ice Lake -~~~~~~~~ - -Following sections include sample calibration data measured on -s71-t212-sut1 server running in one of the Intel Xeon Ice Lake testbeds as -specified in `FD.io CSIT testbeds - Xeon Ice Lake`_. - -Calibration data obtained from all other servers in Ice Lake testbeds -shows the same or similar values. - - -Linux cmdline -^^^^^^^^^^^^^ - -:: - - $ cat /proc/cmdline - BOOT_IMAGE=/boot/vmlinuz-5.4.0-65-generic root=UUID=3250758a-9bb6-48c8-9c36-ecb6a269223f ro audit=0 default_hugepagesz=2M hugepagesz=1G hugepages=32 hugepagesz=2M hugepages=32768 hpet=disable intel_idle.max_cstate=1 intel_iommu=on intel_pstate=disable iommu=pt isolcpus=1-31,33-63,65-95,97-127 mce=off nmi_watchdog=0 nohz_full=1-31,33-63,65-95,97-127 nosoftlockup numa_balancing=disable processor.max_cstate=1 rcu_nocbs=1-31,33-63,65-95,97-127 tsc=reliable console=ttyS0,115200n8 quiet - -Linux uname -^^^^^^^^^^^ - -:: - - $ uname -a - Linux 5.4.0-65-generic #73-Ubuntu SMP Mon Jan 18 17:25:17 UTC 2021 x86_64 x86_64 x86_64 GNU/Linux - - -System-level Core Jitter -^^^^^^^^^^^^^^^^^^^^^^^^ - -:: - - $ sudo taskset -c 3 /home/testuser/pma_tools/jitter/jitter -i 30 - Linux Jitter testing program version 1.9 - Iterations=20 - The pragram will execute a dummy function 80000 times - Display is updated every 20000 displayUpdate intervals - Thread affinity will be set to core_id:7 - Timings are in CPU Core cycles - Inst_Min: Minimum Excution time during the display update interval(default is ~1 second) - Inst_Max: Maximum Excution time during the display update interval(default is ~1 second) - Inst_jitter: Jitter in the Excution time during rhe display update interval. This is the value of interest - last_Exec: The Excution time of last iteration just before the display update - Abs_Min: Absolute Minimum Excution time since the program started or statistics were reset - Abs_Max: Absolute Maximum Excution time since the program started or statistics were reset - tmp: Cumulative value calcualted by the dummy function - Interval: Time interval between the display updates in Core Cycles - Sample No: Sample number - - Inst_Min,Inst_Max,Inst_jitter,last_Exec,Abs_min,Abs_max,tmp,Interval,Sample No - 126082,133950,7868,126094,126082,133950,3829268480,2524167454,1 - 126082,134696,8614,126094,126082,134696,1778253824,2524273022,2 - 126082,136092,10010,126094,126082,136092,4022206464,2524203296,3 - 126082,135094,9012,126094,126082,136092,1971191808,2524274302,4 - 126082,136482,10400,126094,126082,136482,4215144448,2524318496,5 - 126082,134990,8908,126094,126082,136482,2164129792,2524155038,6 - 126082,134710,8628,126092,126082,136482,113115136,2524215228,7 - 126082,135080,8998,126092,126082,136482,2357067776,2524168906,8 - 126082,134470,8388,126094,126082,136482,306053120,2524163312,9 - 126082,135246,9164,126092,126082,136482,2550005760,2524394986,10 - 126082,132662,6580,126094,126082,136482,498991104,2524163156,11 - 126082,132954,6872,126094,126082,136482,2742943744,2524154386,12 - 126082,135340,9258,126092,126082,136482,691929088,2524222386,13 - 126082,133036,6954,126094,126082,136482,2935881728,2524150132,14 - 126082,137776,11694,126094,126082,137776,884867072,2524239346,15 - 126082,137850,11768,126094,126082,137850,3128819712,2524342944,16 - 126082,133000,6918,126094,126082,137850,1077805056,2524160062,17 - 126082,133332,7250,126094,126082,137850,3321757696,2524158804,18 - 126082,133234,7152,126092,126082,137850,1270743040,2524174400,19 - 126082,152552,26470,126094,126082,152552,3514695680,2524857280,20 - -.. include:: ../introduction/test_environment_sut_meltspec_icx.rst diff --git a/docs/report/introduction/test_environment_sut_calib_skx.rst b/docs/report/introduction/test_environment_sut_calib_skx.rst deleted file mode 100644 index cbb8011fe0..0000000000 --- a/docs/report/introduction/test_environment_sut_calib_skx.rst +++ /dev/null @@ -1,214 +0,0 @@ -Skylake -~~~~~~~ - -Following sections include sample calibration data measured on -s11-t31-sut1 server running in one of the Intel Xeon Skylake testbeds as -specified in `FD.io CSIT testbeds - Xeon Skylake, Arm, Atom`_. - -Calibration data obtained from all other servers in Skylake testbeds -shows the same or similar values. - - -Linux cmdline -^^^^^^^^^^^^^ - -:: - - $ cat /proc/cmdline - BOOT_IMAGE=/boot/vmlinuz-5.4.0-65-generic root=UUID=55d44abd-94d6-4b26-9d93-5877a8658016 ro audit=0 hpet=disable intel_idle.max_cstate=1 intel_iommu=on intel_pstate=disable iommu=pt isolcpus=1-27,29-55,57-83,85-111 mce=off nmi_watchdog=0 nohz_full=1-27,29-55,57-83,85-111 nosoftlockup numa_balancing=disable processor.max_cstate=1 rcu_nocbs=1-27,29-55,57-83,85-111 tsc=reliable console=ttyS0,115200n8 quiet - - -Linux uname -^^^^^^^^^^^ - -:: - - $ uname -a - Linux 5.4.0-65-generic #73-Ubuntu SMP Mon Jan 18 17:25:17 UTC 2021 x86_64 x86_64 x86_64 GNU/Linux - - -System-level Core Jitter -^^^^^^^^^^^^^^^^^^^^^^^^ - -:: - - $ sudo taskset -c 3 /home/testuser/pma_tools/jitter/jitter -i 20 - Linux Jitter testing program version 1.8 - Iterations=20 - The pragram will execute a dummy function 80000 times - Display is updated every 20000 displayUpdate intervals - Timings are in CPU Core cycles - Inst_Min: Minimum Excution time during the display update interval(default is ~1 second) - Inst_Max: Maximum Excution time during the display update interval(default is ~1 second) - Inst_jitter: Jitter in the Excution time during rhe display update interval. This is the value of interest - last_Exec: The Excution time of last iteration just before the display update - Abs_Min: Absolute Minimum Excution time since the program started or statistics were reset - Abs_Max: Absolute Maximum Excution time since the program started or statistics were reset - tmp: Cumulative value calcualted by the dummy function - Interval: Time interval between the display updates in Core Cycles - Sample No: Sample number - - Inst_Min Inst_Max Inst_jitter last_Exec Abs_min Abs_max tmp Interval Sample No - 160022 171330 11308 160022 160022 171330 2538733568 3204142750 1 - 160022 167294 7272 160026 160022 171330 328335360 3203873548 2 - 160022 167560 7538 160026 160022 171330 2412904448 3203878736 3 - 160022 169000 8978 160024 160022 171330 202506240 3203864588 4 - 160022 166572 6550 160026 160022 171330 2287075328 3203866224 5 - 160022 167460 7438 160026 160022 171330 76677120 3203854632 6 - 160022 168134 8112 160024 160022 171330 2161246208 3203874674 7 - 160022 169094 9072 160022 160022 171330 4245815296 3203878798 8 - 160022 172460 12438 160024 160022 172460 2035417088 3204112010 9 - 160022 167862 7840 160030 160022 172460 4119986176 3203856800 10 - 160022 168398 8376 160024 160022 172460 1909587968 3203854192 11 - 160022 167548 7526 160024 160022 172460 3994157056 3203847442 12 - 160022 167562 7540 160026 160022 172460 1783758848 3203862936 13 - 160022 167604 7582 160024 160022 172460 3868327936 3203859346 14 - 160022 168262 8240 160024 160022 172460 1657929728 3203851120 15 - 160022 169700 9678 160024 160022 172460 3742498816 3203877690 16 - 160022 170476 10454 160026 160022 172460 1532100608 3204088480 17 - 160022 167798 7776 160024 160022 172460 3616669696 3203862072 18 - 160022 166540 6518 160024 160022 172460 1406271488 3203836904 19 - 160022 167516 7494 160024 160022 172460 3490840576 3203848120 20 - - -Memory Bandwidth -^^^^^^^^^^^^^^^^ - -:: - - $ sudo /home/testuser/mlc --bandwidth_matrix - Intel(R) Memory Latency Checker - v3.5 - Command line parameters: --bandwidth_matrix - - Using buffer size of 100.000MB/thread for reads and an additional 100.000MB/thread for writes - Measuring Memory Bandwidths between nodes within system - Bandwidths are in MB/sec (1 MB/sec = 1,000,000 Bytes/sec) - Using all the threads from each core if Hyper-threading is enabled - Using Read-only traffic type - Numa node - Numa node 0 1 - 0 107947.7 50951.5 - 1 50834.6 108183.4 - -:: - - $ sudo /home/testuser/mlc --peak_injection_bandwidth - Intel(R) Memory Latency Checker - v3.5 - Command line parameters: --peak_injection_bandwidth - - Using buffer size of 100.000MB/thread for reads and an additional 100.000MB/thread for writes - - Measuring Peak Injection Memory Bandwidths for the system - Bandwidths are in MB/sec (1 MB/sec = 1,000,000 Bytes/sec) - Using all the threads from each core if Hyper-threading is enabled - Using traffic with the following read-write ratios - ALL Reads : 215733.9 - 3:1 Reads-Writes : 182141.9 - 2:1 Reads-Writes : 178615.7 - 1:1 Reads-Writes : 149911.3 - Stream-triad like: 159533.6 - -:: - - $ sudo /home/testuser/mlc --max_bandwidth - Intel(R) Memory Latency Checker - v3.5 - Command line parameters: --max_bandwidth - - Using buffer size of 100.000MB/thread for reads and an additional 100.000MB/thread for writes - - Measuring Maximum Memory Bandwidths for the system - Will take several minutes to complete as multiple injection rates will be tried to get the best bandwidth - Bandwidths are in MB/sec (1 MB/sec = 1,000,000 Bytes/sec) - Using all the threads from each core if Hyper-threading is enabled - Using traffic with the following read-write ratios - ALL Reads : 216875.73 - 3:1 Reads-Writes : 182615.14 - 2:1 Reads-Writes : 178745.67 - 1:1 Reads-Writes : 149485.27 - Stream-triad like: 180057.87 - - -Memory Latency -^^^^^^^^^^^^^^ - -:: - - $ sudo /home/testuser/mlc --latency_matrix - Intel(R) Memory Latency Checker - v3.5 - Command line parameters: --latency_matrix - - Using buffer size of 2000.000MB - Measuring idle latencies (in ns)... - Numa node - Numa node 0 1 - 0 81.4 131.1 - 1 131.1 81.3 - -:: - - $ sudo /home/testuser/mlc --idle_latency - Intel(R) Memory Latency Checker - v3.5 - Command line parameters: --idle_latency - - Using buffer size of 2000.000MB - Each iteration took 202.0 core clocks ( 80.8 ns) - -:: - - $ sudo /home/testuser/mlc --loaded_latency - Intel(R) Memory Latency Checker - v3.5 - Command line parameters: --loaded_latency - - Using buffer size of 100.000MB/thread for reads and an additional 100.000MB/thread for writes - - Measuring Loaded Latencies for the system - Using all the threads from each core if Hyper-threading is enabled - Using Read-only traffic type - Inject Latency Bandwidth - Delay (ns) MB/sec - ========================== - 00000 282.66 215712.8 - 00002 282.14 215757.4 - 00008 280.21 215868.1 - 00015 279.20 216313.2 - 00050 275.25 216643.0 - 00100 227.05 215075.0 - 00200 121.92 160242.9 - 00300 101.21 111587.4 - 00400 95.48 85019.7 - 00500 94.46 68717.3 - 00700 92.27 49742.2 - 01000 91.03 35264.8 - 01300 90.11 27396.3 - 01700 89.34 21178.7 - 02500 90.15 14672.8 - 03500 89.00 10715.7 - 05000 82.00 7788.2 - 09000 81.46 4684.0 - 20000 81.40 2541.9 - - -L1/L2/LLC Latency -^^^^^^^^^^^^^^^^^ - -:: - - $ sudo /home/testuser/mlc --c2c_latency - Intel(R) Memory Latency Checker - v3.5 - Command line parameters: --c2c_latency - - Measuring cache-to-cache transfer latency (in ns)... - Local Socket L2->L2 HIT latency 53.7 - Local Socket L2->L2 HITM latency 53.7 - Remote Socket L2->L2 HITM latency (data address homed in writer socket) - Reader Numa Node - Writer Numa Node 0 1 - 0 - 113.9 - 1 113.9 - - Remote Socket L2->L2 HITM latency (data address homed in reader socket) - Reader Numa Node - Writer Numa Node 0 1 - 0 - 177.9 - 1 177.6 - - -.. include:: ../introduction/test_environment_sut_meltspec_skx.rst diff --git a/docs/report/introduction/test_environment_sut_calib_tsh.rst b/docs/report/introduction/test_environment_sut_calib_tsh.rst deleted file mode 100644 index 36284f3e60..0000000000 --- a/docs/report/introduction/test_environment_sut_calib_tsh.rst +++ /dev/null @@ -1,82 +0,0 @@ -TaiShan -~~~~~~~ - -Following sections include sample calibration data measured on -s17-t33-sut1 server running in one of the Cortex-A72 testbeds. - -Calibration data obtained from all other servers in TaiShan testbeds shows the -same or similar values. - - -Linux cmdline -^^^^^^^^^^^^^ - -:: - - $ cat /proc/cmdline - BOOT_IMAGE=/boot/vmlinuz-5.4.0-65-generic root=UUID=7d1d0e77-4df0-43df-9619-a99db29ffb83 ro audit=0 intel_iommu=on isolcpus=1-27,29-55 nmi_watchdog=0 nohz_full=1-27,29-55 nosoftlockup processor.max_cstate=1 rcu_nocbs=1-27,29-55 console=ttyAMA0,115200n8 quiet - -Linux uname -^^^^^^^^^^^ - -:: - - $ uname -a - Linux 5.4.0-65-generic #73-Ubuntu SMP Mon Jan 18 17:25:17 UTC 2021 x86_64 x86_64 x86_64 GNU/Linux - - -System-level Core Jitter -^^^^^^^^^^^^^^^^^^^^^^^^ - -:: - - $ sudo taskset -c 3 /home/testuser/pma_tools/jitter/jitter -i 20 - Linux Jitter testing program version 1.9 - Iterations=30 - The pragram will execute a dummy function 80000 times - Display is updated every 20000 displayUpdate intervals - Thread affinity will be set to core_id:7 - Timings are in CPU Core cycles - Inst_Min: Minimum Excution time during the display update interval(default is ~1 second) - Inst_Max: Maximum Excution time during the display update interval(default is ~1 second) - Inst_jitter: Jitter in the Excution time during rhe display update interval. This is the value of interest - last_Exec: The Excution time of last iteration just before the display update - Abs_Min: Absolute Minimum Excution time since the program started or statistics were reset - Abs_Max: Absolute Maximum Excution time since the program started or statistics were reset - tmp: Cumulative value calcualted by the dummy function - Interval: Time interval between the display updates in Core Cycles - Sample No: Sample number - - Inst_Min Inst_Max Inst_jitter last_Exec Abs_min Abs_max tmp Interval Sample No - 160022 172254 12232 160042 160022 172254 1903230976 3204401362 1 - 160022 173148 13126 160044 160022 173148 814809088 3204619316 2 - 160022 169460 9438 160044 160022 173148 4021354496 3204391306 3 - 160024 170270 10246 160044 160022 173148 2932932608 3204385830 4 - 160022 169660 9638 160044 160022 173148 1844510720 3204387290 5 - 160022 169410 9388 160040 160022 173148 756088832 3204375832 6 - 160022 169012 8990 160042 160022 173148 3962634240 3204378924 7 - 160022 169556 9534 160044 160022 173148 2874212352 3204374882 8 - 160022 171684 11662 160042 160022 173148 1785790464 3204394596 9 - 160022 171546 11524 160024 160022 173148 697368576 3204602774 10 - 160022 169248 9226 160042 160022 173148 3903913984 3204401676 11 - 160022 168458 8436 160042 160022 173148 2815492096 3204256350 12 - 160022 169574 9552 160044 160022 173148 1727070208 3204278116 13 - 160022 169352 9330 160044 160022 173148 638648320 3204327234 14 - 160022 169100 9078 160044 160022 173148 3845193728 3204388132 15 - 160022 169338 9316 160042 160022 173148 2756771840 3204380724 16 - 160022 170828 10806 160046 160022 173148 1668349952 3204430452 17 - 160022 173162 13140 160026 160022 173162 579928064 3204611318 18 - 160022 170482 10460 160042 160022 173162 3786473472 3204389896 19 - 160024 170704 10680 160044 160022 173162 2698051584 3204422126 20 - 160024 169302 9278 160044 160022 173162 1609629696 3204397334 21 - 160022 171848 11826 160044 160022 173162 521207808 3204389818 22 - 160022 169438 9416 160042 160022 173162 3727753216 3204395382 23 - 160022 169312 9290 160042 160022 173162 2639331328 3204371202 24 - 160022 171368 11346 160044 160022 173162 1550909440 3204440464 25 - 160022 171998 11976 160042 160022 173162 462487552 3204609440 26 - 160022 169740 9718 160046 160022 173162 3669032960 3204405826 27 - 160022 169610 9588 160044 160022 173162 2580611072 3204390608 28 - 160022 169254 9232 160044 160022 173162 1492189184 3204399760 29 - 160022 169386 9364 160046 160022 173162 403767296 3204417762 30 - -.. include:: ../introduction/test_environment_sut_meltspec_tsh.rst diff --git a/docs/report/introduction/test_environment_sut_calib_zn2.rst b/docs/report/introduction/test_environment_sut_calib_zn2.rst deleted file mode 100644 index 9454edd2a6..0000000000 --- a/docs/report/introduction/test_environment_sut_calib_zn2.rst +++ /dev/null @@ -1,118 +0,0 @@ -EPYC Zen2 -~~~~~~~~~ - -Following sections include sample calibration data measured on -s60-t210-sut1 server running in one of the AMD EPYC testbeds as -specified in `FD.io CSIT testbeds - EPYC Zen2`_. - - -Linux cmdline -^^^^^^^^^^^^^ - -:: - - $ cat /proc/cmdline - BOOT_IMAGE=/boot/vmlinuz-5.4.0-65-generic root=UUID=3c4b56e3-1f01-4211-a652-ea77468f58b7 ro amd_iommu=on audit=0 hpet=disable iommu=pt isolcpus=1-15,17-31,33-47,49-63 nmi_watchdog=0 nohz_full=off nosoftlockup numa_balancing=disable processor.max_cstate=0 rcu_nocbs=1-15,17-31,33-47,49-63 tsc=reliable console=ttyS0,115200n8 quiet - - -Linux uname -^^^^^^^^^^^ - -:: - - $ uname -a - Linux 5.4.0-65-generic #73-Ubuntu SMP Mon Jan 18 17:25:17 UTC 2021 x86_64 x86_64 x86_64 GNU/Linux - - -System-level Core Jitter -^^^^^^^^^^^^^^^^^^^^^^^^ - -:: - - $ sudo taskset -c 3 /home/testuser/pma_tools/jitter/jitter -i 30 - Linux Jitter testing program version 1.9 - Iterations=20 - The pragram will execute a dummy function 80000 times - Display is updated every 20000 displayUpdate intervals - Thread affinity will be set to core_id:7 - Timings are in CPU Core cycles - Inst_Min: Minimum Excution time during the display update interval(default is ~1 second) - Inst_Max: Maximum Excution time during the display update interval(default is ~1 second) - Inst_jitter: Jitter in the Excution time during rhe display update interval. This is the value of interest - last_Exec: The Excution time of last iteration just before the display update - Abs_Min: Absolute Minimum Excution time since the program started or statistics were reset - Abs_Max: Absolute Maximum Excution time since the program started or statistics were reset - tmp: Cumulative value calcualted by the dummy function - Interval: Time interval between the display updates in Core Cycles - Sample No: Sample number - - Inst_Min,Inst_Max,Inst_jitter,last_Exec,Abs_min,Abs_max,tmp,Interval,Sample No - 116376,145848,29472,116376,116376,145848,3399090176,2350958712,1 - 116376,145848,29472,116400,116376,145848,4158259200,2355136968,2 - 116376,145848,29472,116376,116376,145848,622460928,2343355128,3 - 116376,145848,29472,116376,116376,145848,1381629952,2362905912,4 - 116376,145848,29472,116400,116376,145848,2140798976,2344101768,5 - 116376,145848,29472,116376,116376,145848,2899968000,2341791912,6 - 116376,145848,29472,116400,116376,145848,3659137024,2340794664,7 - 116376,145848,29472,116400,116376,145848,123338752,2336863896,8 - 116376,145752,29376,116400,116376,145848,882507776,2335339584,9 - 116376,145512,29136,116376,116376,145848,1641676800,2335619160,10 - 116376,145512,29136,116400,116376,145848,2400845824,2335646280,11 - 116376,145848,29472,116400,116376,145848,3160014848,2350534872,12 - 116376,145848,29472,116400,116376,145848,3919183872,2348972352,13 - 116376,145848,29472,116400,116376,145848,383385600,2363157840,14 - 116376,145848,29472,116400,116376,145848,1142554624,2349686904,15 - 116376,145848,29472,116400,116376,145848,1901723648,2356550976,16 - 116376,145848,29472,119304,116376,145848,2660892672,2365225944,17 - 116376,145848,29472,116400,116376,145848,3420061696,2365215576,18 - 116376,145848,29472,116400,116376,145848,4179230720,2349971088,19 - 116376,145848,29472,116400,116376,145848,643432448,2339421384,20" - - -Memory Bandwidth -^^^^^^^^^^^^^^^^ - -:: - - $ sudo /home/testuser/mlc --bandwidth_matrix - TBC - -:: - - $ sudo /home/testuser/mlc --peak_injection_bandwidth - TBC - -:: - - $ sudo /home/testuser/mlc --max_bandwidth - TBC - - -Memory Latency -^^^^^^^^^^^^^^ - -:: - - $ sudo /home/testuser/mlc --latency_matrix - TBC - -:: - - $ sudo /home/testuser/mlc --idle_latency - TBC - -:: - - $ sudo /home/testuser/mlc --loaded_latency - TBC - - -L1/L2/LLC Latency -^^^^^^^^^^^^^^^^^ - -:: - - $ sudo /home/testuser/mlc --c2c_latency - TBC - -.. include:: ../introduction/test_environment_sut_meltspec_zn2.rst diff --git a/docs/report/introduction/test_environment_sut_meltspec_clx.rst b/docs/report/introduction/test_environment_sut_meltspec_clx.rst deleted file mode 100644 index 6261c5653c..0000000000 --- a/docs/report/introduction/test_environment_sut_meltspec_clx.rst +++ /dev/null @@ -1,251 +0,0 @@ -Spectre and Meltdown Checks -^^^^^^^^^^^^^^^^^^^^^^^^^^^ - -Following section displays the output of a running shell script to tell if -system is vulnerable against the several speculative execution CVEs that were -made public in 2018. Script is available on `Spectre & Meltdown Checker Github -<https://github.com/speed47/spectre-meltdown-checker>`_. - -:: - - Spectre and Meltdown mitigation detection tool v0.44+ - - Hardware check - * Hardware support (CPU microcode) for mitigation techniques - * Indirect Branch Restricted Speculation (IBRS) - * SPEC_CTRL MSR is available: YES - * CPU indicates IBRS capability: YES (SPEC_CTRL feature bit) - * Indirect Branch Prediction Barrier (IBPB) - * PRED_CMD MSR is available: YES - * CPU indicates IBPB capability: YES (SPEC_CTRL feature bit) - * Single Thread Indirect Branch Predictors (STIBP) - * SPEC_CTRL MSR is available: YES - * CPU indicates STIBP capability: YES (Intel STIBP feature bit) - * Speculative Store Bypass Disable (SSBD) - * CPU indicates SSBD capability: YES (Intel SSBD) - * L1 data cache invalidation - * FLUSH_CMD MSR is available: YES - * CPU indicates L1D flush capability: YES (L1D flush feature bit) - * Microarchitectural Data Sampling - * VERW instruction is available: YES (MD_CLEAR feature bit) - * Enhanced IBRS (IBRS_ALL) - * CPU indicates ARCH_CAPABILITIES MSR availability: YES - * ARCH_CAPABILITIES MSR advertises IBRS_ALL capability: YES - * CPU explicitly indicates not being vulnerable to Meltdown/L1TF (RDCL_NO): YES - * CPU explicitly indicates not being vulnerable to Variant 4 (SSB_NO): NO - * CPU/Hypervisor indicates L1D flushing is not necessary on this system: YES - * Hypervisor indicates host CPU might be vulnerable to RSB underflow (RSBA): NO - * CPU explicitly indicates not being vulnerable to Microarchitectural Data Sampling (MDS_NO): YES - * CPU explicitly indicates not being vulnerable to TSX Asynchronous Abort (TAA_NO): NO - * CPU explicitly indicates not being vulnerable to iTLB Multihit (PSCHANGE_MSC_NO): NO - * CPU explicitly indicates having MSR for TSX control (TSX_CTRL_MSR): YES - * TSX_CTRL MSR indicates TSX RTM is disabled: YES - * TSX_CTRL MSR indicates TSX CPUID bit is cleared: YES - * CPU supports Transactional Synchronization Extensions (TSX): NO - * CPU supports Software Guard Extensions (SGX): NO - * CPU supports Special Register Buffer Data Sampling (SRBDS): NO - * CPU microcode is known to cause stability problems: NO (family 0x6 model 0x55 stepping 0x7 ucode 0x500002c cpuid 0x50657) - * CPU microcode is the latest known available version: NO (latest version is 0x5003102 dated 2021/03/08 according to builtin firmwares DB v191+i20210217) - * CPU vulnerability to the speculative execution attack variants - * Affected by CVE-2017-5753 (Spectre Variant 1, bounds check bypass): YES - * Affected by CVE-2017-5715 (Spectre Variant 2, branch target injection): YES - * Affected by CVE-2017-5754 (Variant 3, Meltdown, rogue data cache load): NO - * Affected by CVE-2018-3640 (Variant 3a, rogue system register read): YES - * Affected by CVE-2018-3639 (Variant 4, speculative store bypass): YES - * Affected by CVE-2018-3615 (Foreshadow (SGX), L1 terminal fault): NO - * Affected by CVE-2018-3620 (Foreshadow-NG (OS), L1 terminal fault): YES - * Affected by CVE-2018-3646 (Foreshadow-NG (VMM), L1 terminal fault): YES - * Affected by CVE-2018-12126 (Fallout, microarchitectural store buffer data sampling (MSBDS)): NO - * Affected by CVE-2018-12130 (ZombieLoad, microarchitectural fill buffer data sampling (MFBDS)): NO - * Affected by CVE-2018-12127 (RIDL, microarchitectural load port data sampling (MLPDS)): NO - * Affected by CVE-2019-11091 (RIDL, microarchitectural data sampling uncacheable memory (MDSUM)): NO - * Affected by CVE-2019-11135 (ZombieLoad V2, TSX Asynchronous Abort (TAA)): NO - * Affected by CVE-2018-12207 (No eXcuses, iTLB Multihit, machine check exception on page size changes (MCEPSC)): YES - * Affected by CVE-2020-0543 (Special Register Buffer Data Sampling (SRBDS)): NO - - CVE-2017-5753 aka Spectre Variant 1, bounds check bypass - * Mitigated according to the /sys interface: YES (Mitigation: usercopy/swapgs barriers and __user pointer sanitization) - > STATUS: UNKNOWN (/sys vulnerability interface use forced, but it s not available!) - - CVE-2017-5715 aka Spectre Variant 2, branch target injection - * Mitigated according to the /sys interface: YES (Mitigation: Enhanced IBRS, IBPB: conditional, RSB filling) - > STATUS: VULNERABLE (IBRS+IBPB or retpoline+IBPB+RSB filling, is needed to mitigate the vulnerability) - - CVE-2017-5754 aka Variant 3, Meltdown, rogue data cache load - * Mitigated according to the /sys interface: YES (Not affected) - * Running as a Xen PV DomU: NO - > STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not vulnerable) - - CVE-2018-3640 aka Variant 3a, rogue system register read - * CPU microcode mitigates the vulnerability: YES - > STATUS: NOT VULNERABLE (your CPU microcode mitigates the vulnerability) - - CVE-2018-3639 aka Variant 4, speculative store bypass - * Mitigated according to the /sys interface: YES (Mitigation: Speculative Store Bypass disabled via prctl and seccomp) - > STATUS: NOT VULNERABLE (Mitigation: Speculative Store Bypass disabled via prctl and seccomp) - - CVE-2018-3615 aka Foreshadow (SGX), L1 terminal fault - * CPU microcode mitigates the vulnerability: N/A - > STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not vulnerable) - - CVE-2018-3620 aka Foreshadow-NG (OS), L1 terminal fault - * Mitigated according to the /sys interface: YES (Not affected) - > STATUS: NOT VULNERABLE (Not affected) - - CVE-2018-3646 aka Foreshadow-NG (VMM), L1 terminal fault - * Information from the /sys interface: Not affected - > STATUS: NOT VULNERABLE (your kernel reported your CPU model as not vulnerable) - - CVE-2018-12126 aka Fallout, microarchitectural store buffer data sampling (MSBDS) - * Mitigated according to the /sys interface: YES (Not affected) - > STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not vulnerable) - - CVE-2018-12130 aka ZombieLoad, microarchitectural fill buffer data sampling (MFBDS) - * Mitigated according to the /sys interface: YES (Not affected) - > STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not vulnerable) - - CVE-2018-12127 aka RIDL, microarchitectural load port data sampling (MLPDS) - * Mitigated according to the /sys interface: YES (Not affected) - > STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not vulnerable) - - CVE-2019-11091 aka RIDL, microarchitectural data sampling uncacheable memory (MDSUM) - * Mitigated according to the /sys interface: YES (Not affected) - > STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not vulnerable) - - CVE-2019-11135 aka ZombieLoad V2, TSX Asynchronous Abort (TAA) - * Mitigated according to the /sys interface: YES (Mitigation: TSX disabled) - > STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not vulnerable) - - CVE-2018-12207 aka No eXcuses, iTLB Multihit, machine check exception on page size changes (MCEPSC) - * Mitigated according to the /sys interface: YES (KVM: Mitigation: Split huge pages) - > STATUS: NOT VULNERABLE (KVM: Mitigation: Split huge pages) - - CVE-2020-0543 aka Special Register Buffer Data Sampling (SRBDS) - * Mitigated according to the /sys interface: YES (Not affected) - > STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not vulnerable) - - > SUMMARY: CVE-2017-5753:?? CVE-2017-5715:KO CVE-2017-5754:OK CVE-2018-3640:OK CVE-2018-3639:OK CVE-2018-3615:OK CVE-2018-3620:OK CVE-2018-3646:OK CVE-2018-12126:OK CVE-2018-12130:OK CVE-2018-12127:OK CVE-2019-11091:OK CVE-2019-11135:OK CVE-2018-12207:OK CVE-2020-0543:OK - -:: - - Spectre and Meltdown mitigation detection tool v0.44+ - - Checking for vulnerabilities on current system - Kernel is Linux 5.4.0-65-generic #73-Ubuntu SMP Mon Jan 18 17:25:17 UTC 2021 x86_64 - CPU is Intel(R) Xeon(R) Gold 6252N CPU @ 2.30GHz - - Hardware check - * Hardware support (CPU microcode) for mitigation techniques - * Indirect Branch Restricted Speculation (IBRS) - * SPEC_CTRL MSR is available: YES - * CPU indicates IBRS capability: YES (SPEC_CTRL feature bit) - * Indirect Branch Prediction Barrier (IBPB) - * PRED_CMD MSR is available: YES - * CPU indicates IBPB capability: YES (SPEC_CTRL feature bit) - * Single Thread Indirect Branch Predictors (STIBP) - * SPEC_CTRL MSR is available: YES - * CPU indicates STIBP capability: YES (Intel STIBP feature bit) - * Speculative Store Bypass Disable (SSBD) - * CPU indicates SSBD capability: YES (Intel SSBD) - * L1 data cache invalidation - * FLUSH_CMD MSR is available: YES - * CPU indicates L1D flush capability: YES (L1D flush feature bit) - * Microarchitectural Data Sampling - * VERW instruction is available: YES (MD_CLEAR feature bit) - * Enhanced IBRS (IBRS_ALL) - * CPU indicates ARCH_CAPABILITIES MSR availability: YES - * ARCH_CAPABILITIES MSR advertises IBRS_ALL capability: YES - * CPU explicitly indicates not being vulnerable to Meltdown/L1TF (RDCL_NO): YES - * CPU explicitly indicates not being vulnerable to Variant 4 (SSB_NO): NO - * CPU/Hypervisor indicates L1D flushing is not necessary on this system: YES - * Hypervisor indicates host CPU might be vulnerable to RSB underflow (RSBA): NO - * CPU explicitly indicates not being vulnerable to Microarchitectural Data Sampling (MDS_NO): YES - * CPU explicitly indicates not being vulnerable to TSX Asynchronous Abort (TAA_NO): NO - * CPU explicitly indicates not being vulnerable to iTLB Multihit (PSCHANGE_MSC_NO): NO - * CPU explicitly indicates having MSR for TSX control (TSX_CTRL_MSR): YES - * TSX_CTRL MSR indicates TSX RTM is disabled: YES - * TSX_CTRL MSR indicates TSX CPUID bit is cleared: YES - * CPU supports Transactional Synchronization Extensions (TSX): NO - * CPU supports Software Guard Extensions (SGX): NO - * CPU supports Special Register Buffer Data Sampling (SRBDS): NO - * CPU microcode is known to cause stability problems: NO (family 0x6 model 0x55 stepping 0x7 ucode 0x500002c cpuid 0x50657) - * CPU microcode is the latest known available version: NO (latest version is 0x5003102 dated 2021/03/08 according to builtin firmwares DB v191+i20210217) - * CPU vulnerability to the speculative execution attack variants - * Affected by CVE-2017-5753 (Spectre Variant 1, bounds check bypass): YES - * Affected by CVE-2017-5715 (Spectre Variant 2, branch target injection): YES - * Affected by CVE-2017-5754 (Variant 3, Meltdown, rogue data cache load): NO - * Affected by CVE-2018-3640 (Variant 3a, rogue system register read): YES - * Affected by CVE-2018-3639 (Variant 4, speculative store bypass): YES - * Affected by CVE-2018-3615 (Foreshadow (SGX), L1 terminal fault): NO - * Affected by CVE-2018-3620 (Foreshadow-NG (OS), L1 terminal fault): YES - * Affected by CVE-2018-3646 (Foreshadow-NG (VMM), L1 terminal fault): YES - * Affected by CVE-2018-12126 (Fallout, microarchitectural store buffer data sampling (MSBDS)): NO - * Affected by CVE-2018-12130 (ZombieLoad, microarchitectural fill buffer data sampling (MFBDS)): NO - * Affected by CVE-2018-12127 (RIDL, microarchitectural load port data sampling (MLPDS)): NO - * Affected by CVE-2019-11091 (RIDL, microarchitectural data sampling uncacheable memory (MDSUM)): NO - * Affected by CVE-2019-11135 (ZombieLoad V2, TSX Asynchronous Abort (TAA)): NO - * Affected by CVE-2018-12207 (No eXcuses, iTLB Multihit, machine check exception on page size changes (MCEPSC)): YES - * Affected by CVE-2020-0543 (Special Register Buffer Data Sampling (SRBDS)): NO - - CVE-2017-5753 aka Spectre Variant 1, bounds check bypass - * Mitigated according to the /sys interface: YES (Mitigation: usercopy/swapgs barriers and __user pointer sanitization) - > STATUS: UNKNOWN (/sys vulnerability interface use forced, but its not available!) - - CVE-2017-5715 aka Spectre Variant 2, branch target injection - * Mitigated according to the /sys interface: YES (Mitigation: Enhanced IBRS, IBPB: conditional, RSB filling) - > STATUS: VULNERABLE (IBRS+IBPB or retpoline+IBPB+RSB filling, is needed to mitigate the vulnerability) - - CVE-2017-5754 aka Variant 3, Meltdown, rogue data cache load - * Mitigated according to the /sys interface: YES (Not affected) - * Running as a Xen PV DomU: NO - > STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not vulnerable) - - CVE-2018-3640 aka Variant 3a, rogue system register read - * CPU microcode mitigates the vulnerability: YES - > STATUS: NOT VULNERABLE (your CPU microcode mitigates the vulnerability) - - CVE-2018-3639 aka Variant 4, speculative store bypass - * Mitigated according to the /sys interface: YES (Mitigation: Speculative Store Bypass disabled via prctl and seccomp) - > STATUS: NOT VULNERABLE (Mitigation: Speculative Store Bypass disabled via prctl and seccomp) - - CVE-2018-3615 aka Foreshadow (SGX), L1 terminal fault - * CPU microcode mitigates the vulnerability: N/A - > STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not vulnerable) - - CVE-2018-3620 aka Foreshadow-NG (OS), L1 terminal fault - * Mitigated according to the /sys interface: YES (Not affected) - > STATUS: NOT VULNERABLE (Not affected) - - CVE-2018-3646 aka Foreshadow-NG (VMM), L1 terminal fault - * Information from the /sys interface: Not affected - > STATUS: NOT VULNERABLE (your kernel reported your CPU model as not vulnerable) - - CVE-2018-12126 aka Fallout, microarchitectural store buffer data sampling (MSBDS) - * Mitigated according to the /sys interface: YES (Not affected) - > STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not vulnerable) - - CVE-2018-12130 aka ZombieLoad, microarchitectural fill buffer data sampling (MFBDS) - * Mitigated according to the /sys interface: YES (Not affected) - > STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not vulnerable) - - CVE-2018-12127 aka RIDL, microarchitectural load port data sampling (MLPDS) - * Mitigated according to the /sys interface: YES (Not affected) - > STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not vulnerable) - - CVE-2019-11091 aka RIDL, microarchitectural data sampling uncacheable memory (MDSUM) - * Mitigated according to the /sys interface: YES (Not affected) - > STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not vulnerable) - - CVE-2019-11135 aka ZombieLoad V2, TSX Asynchronous Abort (TAA) - * Mitigated according to the /sys interface: YES (Mitigation: TSX disabled) - > STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not vulnerable) - - CVE-2018-12207 aka No eXcuses, iTLB Multihit, machine check exception on page size changes (MCEPSC) - * Mitigated according to the /sys interface: YES (KVM: Mitigation: Split huge pages) - > STATUS: NOT VULNERABLE (KVM: Mitigation: Split huge pages) - - CVE-2020-0543 aka Special Register Buffer Data Sampling (SRBDS) - * Mitigated according to the /sys interface: YES (Not affected) - > STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not vulnerable) - - > SUMMARY: CVE-2017-5753:?? CVE-2017-5715:KO CVE-2017-5754:OK CVE-2018-3640:OK CVE-2018-3639:OK CVE-2018-3615:OK CVE-2018-3620:OK CVE-2018-3646:OK CVE-2018-12126:OK CVE-2018-12130:OK CVE-2018-12127:OK CVE-2019-11091:OK CVE-2019-11135:OK CVE-2018-12207:OK CVE-2020-0543:OK diff --git a/docs/report/introduction/test_environment_sut_meltspec_dnv.rst b/docs/report/introduction/test_environment_sut_meltspec_dnv.rst deleted file mode 100644 index 4b3a8a134d..0000000000 --- a/docs/report/introduction/test_environment_sut_meltspec_dnv.rst +++ /dev/null @@ -1,347 +0,0 @@ -Spectre and Meltdown Checks -^^^^^^^^^^^^^^^^^^^^^^^^^^^ - -Following section displays the output of a running shell script to tell if -system is vulnerable against the several "speculative execution" CVEs that were -made public in 2018. Script is available on `Spectre & Meltdown Checker Github -<https://github.com/speed47/spectre-meltdown-checker>`_. - -:: - - Spectre and Meltdown mitigation detection tool v0.44+ - - Checking for vulnerabilities on current system - Kernel is Linux 5.4.0-65-generic #73-Ubuntu SMP Mon Jan 18 17:25:17 UTC 2021 x86_64 - CPU is Intel(R) Xeon(R) Platinum 8180 CPU @ 2.50GHz - - Hardware check - * Hardware support (CPU microcode) for mitigation techniques - * Indirect Branch Restricted Speculation (IBRS) - * SPEC_CTRL MSR is available: YES - * CPU indicates IBRS capability: YES (SPEC_CTRL feature bit) - * Indirect Branch Prediction Barrier (IBPB) - * PRED_CMD MSR is available: YES - * CPU indicates IBPB capability: YES (SPEC_CTRL feature bit) - * Single Thread Indirect Branch Predictors (STIBP) - * SPEC_CTRL MSR is available: YES - * CPU indicates STIBP capability: YES (Intel STIBP feature bit) - * Speculative Store Bypass Disable (SSBD) - * CPU indicates SSBD capability: YES (Intel SSBD) - * L1 data cache invalidation - * FLUSH_CMD MSR is available: YES - * CPU indicates L1D flush capability: YES (L1D flush feature bit) - * Microarchitectural Data Sampling - * VERW instruction is available: YES (MD_CLEAR feature bit) - * Enhanced IBRS (IBRS_ALL) - * CPU indicates ARCH_CAPABILITIES MSR availability: NO - * ARCH_CAPABILITIES MSR advertises IBRS_ALL capability: NO - * CPU explicitly indicates not being vulnerable to Meltdown/L1TF (RDCL_NO): NO - * CPU explicitly indicates not being vulnerable to Variant 4 (SSB_NO): NO - * CPU/Hypervisor indicates L1D flushing is not necessary on this system: NO - * Hypervisor indicates host CPU might be vulnerable to RSB underflow (RSBA): NO - * CPU explicitly indicates not being vulnerable to Microarchitectural Data Sampling (MDS_NO): NO - * CPU explicitly indicates not being vulnerable to TSX Asynchronous Abort (TAA_NO): NO - * CPU explicitly indicates not being vulnerable to iTLB Multihit (PSCHANGE_MSC_NO): NO - * CPU explicitly indicates having MSR for TSX control (TSX_CTRL_MSR): NO - * CPU supports Transactional Synchronization Extensions (TSX): YES (RTM feature bit) - * CPU supports Software Guard Extensions (SGX): NO - * CPU supports Special Register Buffer Data Sampling (SRBDS): NO - * CPU microcode is known to cause stability problems: NO (family 0x6 model 0x55 stepping 0x4 ucode 0x2000065 cpuid 0x50654) - * CPU microcode is the latest known available version: NO (latest version is 0x2006b06 dated 2021/03/08 according to builtin firmwares DB v191+i20210217) - * CPU vulnerability to the speculative execution attack variants - * Affected by CVE-2017-5753 (Spectre Variant 1, bounds check bypass): YES - * Affected by CVE-2017-5715 (Spectre Variant 2, branch target injection): YES - * Affected by CVE-2017-5754 (Variant 3, Meltdown, rogue data cache load): YES - * Affected by CVE-2018-3640 (Variant 3a, rogue system register read): YES - * Affected by CVE-2018-3639 (Variant 4, speculative store bypass): YES - * Affected by CVE-2018-3615 (Foreshadow (SGX), L1 terminal fault): NO - * Affected by CVE-2018-3620 (Foreshadow-NG (OS), L1 terminal fault): YES - * Affected by CVE-2018-3646 (Foreshadow-NG (VMM), L1 terminal fault): YES - * Affected by CVE-2018-12126 (Fallout, microarchitectural store buffer data sampling (MSBDS)): YES - * Affected by CVE-2018-12130 (ZombieLoad, microarchitectural fill buffer data sampling (MFBDS)): YES - * Affected by CVE-2018-12127 (RIDL, microarchitectural load port data sampling (MLPDS)): YES - * Affected by CVE-2019-11091 (RIDL, microarchitectural data sampling uncacheable memory (MDSUM)): YES - * Affected by CVE-2019-11135 (ZombieLoad V2, TSX Asynchronous Abort (TAA)): YES - * Affected by CVE-2018-12207 (No eXcuses, iTLB Multihit, machine check exception on page size changes (MCEPSC)): YES - * Affected by CVE-2020-0543 (Special Register Buffer Data Sampling (SRBDS)): NO - - CVE-2017-5753 aka Spectre Variant 1, bounds check bypass - * Mitigated according to the /sys interface: YES (Mitigation: usercopy/swapgs barriers and __user pointer sanitization) - * Kernel has array_index_mask_nospec: YES (1 occurrence(s) found of x86 64 bits array_index_mask_nospec()) - * Kernel has the Red Hat/Ubuntu patch: NO - * Kernel has mask_nospec64 (arm64): NO - * Kernel has array_index_nospec (arm64): NO - > STATUS: NOT VULNERABLE (Mitigation: usercopy/swapgs barriers and __user pointer sanitization) - - CVE-2017-5715 aka Spectre Variant 2, branch target injection - * Mitigated according to the /sys interface: YES (Mitigation: Full generic retpoline, IBPB: conditional, IBRS_FW, STIBP: conditional, RSB filling) - * Mitigation 1 - * Kernel is compiled with IBRS support: YES - * IBRS enabled and active: YES (for firmware code only) - * Kernel is compiled with IBPB support: YES - * IBPB enabled and active: YES - * Mitigation 2 - * Kernel has branch predictor hardening (arm): NO - * Kernel compiled with retpoline option: YES - * Kernel compiled with a retpoline-aware compiler: YES (kernel reports full retpoline compilation) - * Kernel supports RSB filling: YES - > STATUS: NOT VULNERABLE (Full retpoline + IBPB are mitigating the vulnerability) - - CVE-2017-5754 aka Variant 3, Meltdown, rogue data cache load - * Mitigated according to the /sys interface: YES (Mitigation: PTI) - * Kernel supports Page Table Isolation (PTI): YES - * PTI enabled and active: YES - * Reduced performance impact of PTI: YES (CPU supports INVPCID, performance impact of PTI will be greatly reduced) - * Running as a Xen PV DomU: NO - > STATUS: NOT VULNERABLE (Mitigation: PTI) - - CVE-2018-3640 aka Variant 3a, rogue system register read - * CPU microcode mitigates the vulnerability: YES - > STATUS: NOT VULNERABLE (your CPU microcode mitigates the vulnerability) - - CVE-2018-3639 aka Variant 4, speculative store bypass - * Mitigated according to the /sys interface: YES (Mitigation: Speculative Store Bypass disabled via prctl and seccomp) - * Kernel supports disabling speculative store bypass (SSB): YES (found in /proc/self/status) - * SSB mitigation is enabled and active: YES (per-thread through prctl) - * SSB mitigation currently active for selected processes: YES (boltd fwupd irqbalance systemd-journald systemd-logind systemd-networkd systemd-resolved systemd-timesyncd systemd-udevd) - > STATUS: NOT VULNERABLE (Mitigation: Speculative Store Bypass disabled via prctl and seccomp) - - CVE-2018-3615 aka Foreshadow (SGX), L1 terminal fault - * CPU microcode mitigates the vulnerability: N/A - > STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not vulnerable) - - CVE-2018-3620 aka Foreshadow-NG (OS), L1 terminal fault - * Mitigated according to the /sys interface: YES (Mitigation: PTE Inversion; VMX: conditional cache flushes, SMT vulnerable) - * Kernel supports PTE inversion: YES (found in kernel image) - * PTE inversion enabled and active: YES - > STATUS: NOT VULNERABLE (Mitigation: PTE Inversion; VMX: conditional cache flushes, SMT vulnerable) - - CVE-2018-3646 aka Foreshadow-NG (VMM), L1 terminal fault - * Information from the /sys interface: Mitigation: PTE Inversion; VMX: conditional cache flushes, SMT vulnerable - * This system is a host running a hypervisor: NO - * Mitigation 1 (KVM) - * EPT is disabled: NO - * Mitigation 2 - * L1D flush is supported by kernel: YES (found flush_l1d in /proc/cpuinfo) - * L1D flush enabled: YES (conditional flushes) - * Hardware-backed L1D flush supported: YES (performance impact of the mitigation will be greatly reduced) - * Hyper-Threading (SMT) is enabled: YES - > STATUS: NOT VULNERABLE (this system is not running a hypervisor) - - CVE-2018-12126 aka Fallout, microarchitectural store buffer data sampling (MSBDS) - * Mitigated according to the /sys interface: YES (Mitigation: Clear CPU buffers; SMT vulnerable) - * Kernel supports using MD_CLEAR mitigation: YES (md_clear found in /proc/cpuinfo) - * Kernel mitigation is enabled and active: YES - * SMT is either mitigated or disabled: NO - > STATUS: NOT VULNERABLE (Your microcode and kernel are both up to date for this mitigation, and mitigation is enabled) - - CVE-2018-12130 aka ZombieLoad, microarchitectural fill buffer data sampling (MFBDS) - * Mitigated according to the /sys interface: YES (Mitigation: Clear CPU buffers; SMT vulnerable) - * Kernel supports using MD_CLEAR mitigation: YES (md_clear found in /proc/cpuinfo) - * Kernel mitigation is enabled and active: YES - * SMT is either mitigated or disabled: NO - > STATUS: NOT VULNERABLE (Your microcode and kernel are both up to date for this mitigation, and mitigation is enabled) - - CVE-2018-12127 aka RIDL, microarchitectural load port data sampling (MLPDS) - * Mitigated according to the /sys interface: YES (Mitigation: Clear CPU buffers; SMT vulnerable) - * Kernel supports using MD_CLEAR mitigation: YES (md_clear found in /proc/cpuinfo) - * Kernel mitigation is enabled and active: YES - * SMT is either mitigated or disabled: NO - > STATUS: NOT VULNERABLE (Your microcode and kernel are both up to date for this mitigation, and mitigation is enabled) - - CVE-2019-11091 aka RIDL, microarchitectural data sampling uncacheable memory (MDSUM) - * Mitigated according to the /sys interface: YES (Mitigation: Clear CPU buffers; SMT vulnerable) - * Kernel supports using MD_CLEAR mitigation: YES (md_clear found in /proc/cpuinfo) - * Kernel mitigation is enabled and active: YES - * SMT is either mitigated or disabled: NO - > STATUS: NOT VULNERABLE (Your microcode and kernel are both up to date for this mitigation, and mitigation is enabled) - - CVE-2019-11135 aka ZombieLoad V2, TSX Asynchronous Abort (TAA) - * Mitigated according to the /sys interface: YES (Mitigation: Clear CPU buffers; SMT vulnerable) - * TAA mitigation is supported by kernel: YES (found tsx_async_abort in kernel image) - * TAA mitigation enabled and active: YES (Mitigation: Clear CPU buffers; SMT vulnerable) - > STATUS: NOT VULNERABLE (Mitigation: Clear CPU buffers; SMT vulnerable) - - CVE-2018-12207 aka No eXcuses, iTLB Multihit, machine check exception on page size changes (MCEPSC) - * Mitigated according to the /sys interface: YES (KVM: Mitigation: Split huge pages) - * This system is a host running a hypervisor: NO - * iTLB Multihit mitigation is supported by kernel: YES (found itlb_multihit in kernel image) - * iTLB Multihit mitigation enabled and active: YES (KVM: Mitigation: Split huge pages) - > STATUS: NOT VULNERABLE (this system is not running a hypervisor) - - CVE-2020-0543 aka Special Register Buffer Data Sampling (SRBDS) - * Mitigated according to the /sys interface: YES (Not affected) - * SRBDS mitigation control is supported by the kernel: YES (found SRBDS implementation evidence in kernel image. Your kernel is up to date for SRBDS mitigation) - * SRBDS mitigation control is enabled and active: NO - > STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not vulnerable) - - > SUMMARY: CVE-2017-5753:OK CVE-2017-5715:OK CVE-2017-5754:OK CVE-2018-3640:OK CVE-2018-3639:OK CVE-2018-3615:OK CVE-2018-3620:OK CVE-2018-3646:OK CVE-2018-12126:OK CVE-2018-12130:OK CVE-2018-12127:OK CVE-2019-11091:OK CVE-2019-11135:OK CVE-2018-12207:OK CVE-2020-0543:OK - -:: - - Spectre and Meltdown mitigation detection tool v0.44+ - - Checking for vulnerabilities on current system - Kernel is Linux 5.4.0-65-generic #73-Ubuntu SMP Mon Jan 18 17:25:17 UTC 2021 x86_64 - CPU is Intel(R) Atom(TM) CPU C3858 @ 2.00GHz - - Hardware check - * Hardware support (CPU microcode) for mitigation techniques - * Indirect Branch Restricted Speculation (IBRS) - * SPEC_CTRL MSR is available: YES - * CPU indicates IBRS capability: YES (SPEC_CTRL feature bit) - * Indirect Branch Prediction Barrier (IBPB) - * PRED_CMD MSR is available: YES - * CPU indicates IBPB capability: YES (SPEC_CTRL feature bit) - * Single Thread Indirect Branch Predictors (STIBP) - * SPEC_CTRL MSR is available: YES - * CPU indicates STIBP capability: YES (Intel STIBP feature bit) - * Speculative Store Bypass Disable (SSBD) - * CPU indicates SSBD capability: NO - * L1 data cache invalidation - * FLUSH_CMD MSR is available: NO - * CPU indicates L1D flush capability: NO - * Microarchitectural Data Sampling - * VERW instruction is available: NO - * Enhanced IBRS (IBRS_ALL) - * CPU indicates ARCH_CAPABILITIES MSR availability: YES - * ARCH_CAPABILITIES MSR advertises IBRS_ALL capability: NO - * CPU explicitly indicates not being vulnerable to Meltdown/L1TF (RDCL_NO): YES - * CPU explicitly indicates not being vulnerable to Variant 4 (SSB_NO): NO - * CPU/Hypervisor indicates L1D flushing is not necessary on this system: NO - * Hypervisor indicates host CPU might be vulnerable to RSB underflow (RSBA): NO - * CPU explicitly indicates not being vulnerable to Microarchitectural Data Sampling (MDS_NO): NO - * CPU explicitly indicates not being vulnerable to TSX Asynchronous Abort (TAA_NO): NO - * CPU explicitly indicates not being vulnerable to iTLB Multihit (PSCHANGE_MSC_NO): NO - * CPU explicitly indicates having MSR for TSX control (TSX_CTRL_MSR): NO - * CPU supports Transactional Synchronization Extensions (TSX): NO - * CPU supports Software Guard Extensions (SGX): NO - * CPU supports Special Register Buffer Data Sampling (SRBDS): NO - * CPU microcode is known to cause stability problems: NO (family 0x6 model 0x5f stepping 0x1 ucode 0x20 cpuid 0x506f1) - * CPU microcode is the latest known available version: NO (latest version is 0x34 dated 2020/10/23 according to builtin firmwares DB v191+i20210217) - * CPU vulnerability to the speculative execution attack variants - * Affected by CVE-2017-5753 (Spectre Variant 1, bounds check bypass): YES - * Affected by CVE-2017-5715 (Spectre Variant 2, branch target injection): YES - * Affected by CVE-2017-5754 (Variant 3, Meltdown, rogue data cache load): NO - * Affected by CVE-2018-3640 (Variant 3a, rogue system register read): YES - * Affected by CVE-2018-3639 (Variant 4, speculative store bypass): YES - * Affected by CVE-2018-3615 (Foreshadow (SGX), L1 terminal fault): NO - * Affected by CVE-2018-3620 (Foreshadow-NG (OS), L1 terminal fault): NO - * Affected by CVE-2018-3646 (Foreshadow-NG (VMM), L1 terminal fault): NO - * Affected by CVE-2018-12126 (Fallout, microarchitectural store buffer data sampling (MSBDS)): NO - * Affected by CVE-2018-12130 (ZombieLoad, microarchitectural fill buffer data sampling (MFBDS)): NO - * Affected by CVE-2018-12127 (RIDL, microarchitectural load port data sampling (MLPDS)): NO - * Affected by CVE-2019-11091 (RIDL, microarchitectural data sampling uncacheable memory (MDSUM)): NO - * Affected by CVE-2019-11135 (ZombieLoad V2, TSX Asynchronous Abort (TAA)): NO - * Affected by CVE-2018-12207 (No eXcuses, iTLB Multihit, machine check exception on page size changes (MCEPSC)): NO - * Affected by CVE-2020-0543 (Special Register Buffer Data Sampling (SRBDS)): NO - - CVE-2017-5753 aka Spectre Variant 1, bounds check bypass - * Mitigated according to the /sys interface: YES (Mitigation: usercopy/swapgs barriers and __user pointer sanitization) - * Kernel has array_index_mask_nospec: YES (1 occurrence(s) found of x86 64 bits array_index_mask_nospec()) - * Kernel has the Red Hat/Ubuntu patch: NO - * Kernel has mask_nospec64 (arm64): NO - * Kernel has array_index_nospec (arm64): NO - > STATUS: NOT VULNERABLE (Mitigation: usercopy/swapgs barriers and __user pointer sanitization) - - CVE-2017-5715 aka Spectre Variant 2, branch target injection - * Mitigated according to the /sys interface: YES (Mitigation: Full generic retpoline, IBPB: conditional, IBRS_FW, STIBP: disabled, RSB filling) - * Mitigation 1 - * Kernel is compiled with IBRS support: YES - * IBRS enabled and active: YES (for firmware code only) - * Kernel is compiled with IBPB support: YES - * IBPB enabled and active: YES - * Mitigation 2 - * Kernel has branch predictor hardening (arm): NO - * Kernel compiled with retpoline option: YES - * Kernel compiled with a retpoline-aware compiler: YES (kernel reports full retpoline compilation) - > STATUS: NOT VULNERABLE (Full retpoline + IBPB are mitigating the vulnerability) - - CVE-2017-5754 aka Variant 3, Meltdown, rogue data cache load - * Mitigated according to the /sys interface: YES (Not affected) - * Kernel supports Page Table Isolation (PTI): YES - * PTI enabled and active: NO - * Reduced performance impact of PTI: NO (PCID/INVPCID not supported, performance impact of PTI will be significant) - * Running as a Xen PV DomU: NO - > STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not vulnerable) - - CVE-2018-3640 aka Variant 3a, rogue system register read - * CPU microcode mitigates the vulnerability: NO - > STATUS: VULNERABLE (an up-to-date CPU microcode is needed to mitigate this vulnerability) - - CVE-2018-3639 aka Variant 4, speculative store bypass - * Mitigated according to the /sys interface: NO (Vulnerable) - * Kernel supports disabling speculative store bypass (SSB): YES (found in /proc/self/status) - * SSB mitigation is enabled and active: NO - > STATUS: VULNERABLE (Your CPU doesnt support SSBD) - - CVE-2018-3615 aka Foreshadow (SGX), L1 terminal fault - * CPU microcode mitigates the vulnerability: N/A - > STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not vulnerable) - - CVE-2018-3620 aka Foreshadow-NG (OS), L1 terminal fault - * Mitigated according to the /sys interface: YES (Not affected) - * Kernel supports PTE inversion: YES (found in kernel image) - * PTE inversion enabled and active: NO - > STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not vulnerable) - - CVE-2018-3646 aka Foreshadow-NG (VMM), L1 terminal fault - * Information from the /sys interface: Not affected - * This system is a host running a hypervisor: NO - * Mitigation 1 (KVM) - * EPT is disabled: NO - * Mitigation 2 - * L1D flush is supported by kernel: YES (found flush_l1d in kernel image) - * L1D flush enabled: NO - * Hardware-backed L1D flush supported: NO (flush will be done in software, this is slower) - * Hyper-Threading (SMT) is enabled: NO - > STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not vulnerable) - - CVE-2018-12126 aka Fallout, microarchitectural store buffer data sampling (MSBDS) - * Mitigated according to the /sys interface: YES (Not affected) - * Kernel supports using MD_CLEAR mitigation: YES (found md_clear implementation evidence in kernel image) - * Kernel mitigation is enabled and active: NO - * SMT is either mitigated or disabled: NO - > STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not vulnerable) - - CVE-2018-12130 aka ZombieLoad, microarchitectural fill buffer data sampling (MFBDS) - * Mitigated according to the /sys interface: YES (Not affected) - * Kernel supports using MD_CLEAR mitigation: YES (found md_clear implementation evidence in kernel image) - * Kernel mitigation is enabled and active: NO - * SMT is either mitigated or disabled: NO - > STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not vulnerable) - - CVE-2018-12127 aka RIDL, microarchitectural load port data sampling (MLPDS) - * Mitigated according to the /sys interface: YES (Not affected) - * Kernel supports using MD_CLEAR mitigation: YES (found md_clear implementation evidence in kernel image) - * Kernel mitigation is enabled and active: NO - * SMT is either mitigated or disabled: NO - > STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not vulnerable) - - CVE-2019-11091 aka RIDL, microarchitectural data sampling uncacheable memory (MDSUM) - * Mitigated according to the /sys interface: YES (Not affected) - * Kernel supports using MD_CLEAR mitigation: YES (found md_clear implementation evidence in kernel image) - * Kernel mitigation is enabled and active: NO - * SMT is either mitigated or disabled: NO - > STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not vulnerable) - - CVE-2019-11135 aka ZombieLoad V2, TSX Asynchronous Abort (TAA) - * Mitigated according to the /sys interface: YES (Not affected) - * TAA mitigation is supported by kernel: YES (found tsx_async_abort in kernel image) - * TAA mitigation enabled and active: NO - > STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not vulnerable) - - CVE-2018-12207 aka No eXcuses, iTLB Multihit, machine check exception on page size changes (MCEPSC) - * Mitigated according to the /sys interface: YES (Not affected) - * This system is a host running a hypervisor: NO - * iTLB Multihit mitigation is supported by kernel: YES (found itlb_multihit in kernel image) - * iTLB Multihit mitigation enabled and active: NO - > STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not vulnerable) - - CVE-2020-0543 aka Special Register Buffer Data Sampling (SRBDS) - * Mitigated according to the /sys interface: YES (Not affected) - * SRBDS mitigation control is supported by the kernel: YES (found SRBDS implementation evidence in kernel image. Your kernel is up to date for SRBDS mitigation) - * SRBDS mitigation control is enabled and active: NO - > STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not vulnerable) - - > SUMMARY: CVE-2017-5753:OK CVE-2017-5715:OK CVE-2017-5754:OK CVE-2018-3640:KO CVE-2018-3639:KO CVE-2018-3615:OK CVE-2018-3620:OK CVE-2018-3646:OK CVE-2018-12126:OK CVE-2018-12130:OK CVE-2018-12127:OK CVE-2019-11091:OK CVE-2019-11135:OK CVE-2018-12207:OK CVE-2020-0543:OK diff --git a/docs/report/introduction/test_environment_sut_meltspec_icx.rst b/docs/report/introduction/test_environment_sut_meltspec_icx.rst deleted file mode 100644 index 256391e13d..0000000000 --- a/docs/report/introduction/test_environment_sut_meltspec_icx.rst +++ /dev/null @@ -1,131 +0,0 @@ -Spectre and Meltdown Checks -^^^^^^^^^^^^^^^^^^^^^^^^^^^ - -Following section displays the output of a running shell script to tell if -system is vulnerable against the several speculative execution CVEs that were -made public in 2018. Script is available on `Spectre & Meltdown Checker Github -<https://github.com/speed47/spectre-meltdown-checker>`_. - -:: - - Spectre and Meltdown mitigation detection tool v0.44+ - - Checking for vulnerabilities on current system - Kernel is Linux 5.4.0-65-generic #73-Ubuntu SMP Mon Jan 18 17:25:17 UTC 2021 x86_64 - CPU is Intel(R) Xeon(R) Platinum 8358 CPU @ 2.60GHz - - Hardware check - * Hardware support (CPU microcode) for mitigation techniques - * Indirect Branch Restricted Speculation (IBRS) - * SPEC_CTRL MSR is available: YES - * CPU indicates IBRS capability: YES (SPEC_CTRL feature bit) - * Indirect Branch Prediction Barrier (IBPB) - * PRED_CMD MSR is available: YES - * CPU indicates IBPB capability: YES (SPEC_CTRL feature bit) - * Single Thread Indirect Branch Predictors (STIBP) - * SPEC_CTRL MSR is available: YES - * CPU indicates STIBP capability: YES (Intel STIBP feature bit) - * Speculative Store Bypass Disable (SSBD) - * CPU indicates SSBD capability: YES (Intel SSBD) - * L1 data cache invalidation - * FLUSH_CMD MSR is available: YES - * CPU indicates L1D flush capability: YES (L1D flush feature bit) - * Microarchitectural Data Sampling - * VERW instruction is available: YES (MD_CLEAR feature bit) - * Enhanced IBRS (IBRS_ALL) - * CPU indicates ARCH_CAPABILITIES MSR availability: YES - * ARCH_CAPABILITIES MSR advertises IBRS_ALL capability: YES - * CPU explicitly indicates not being vulnerable to Meltdown/L1TF (RDCL_NO): YES - * CPU explicitly indicates not being vulnerable to Variant 4 (SSB_NO): NO - * CPU/Hypervisor indicates L1D flushing is not necessary on this system: YES - * Hypervisor indicates host CPU might be vulnerable to RSB underflow (RSBA): NO - * CPU explicitly indicates not being vulnerable to Microarchitectural Data Sampling (MDS_NO): YES - * CPU explicitly indicates not being vulnerable to TSX Asynchronous Abort (TAA_NO): YES - * CPU explicitly indicates not being vulnerable to iTLB Multihit (PSCHANGE_MSC_NO): YES - * CPU explicitly indicates having MSR for TSX control (TSX_CTRL_MSR): YES - * TSX_CTRL MSR indicates TSX RTM is disabled: YES - * TSX_CTRL MSR indicates TSX CPUID bit is cleared: YES - * CPU supports Transactional Synchronization Extensions (TSX): NO - * CPU supports Software Guard Extensions (SGX): YES - * CPU supports Special Register Buffer Data Sampling (SRBDS): NO - * CPU microcode is known to cause stability problems: NO (family 0x6 model 0x6a stepping 0x6 ucode 0xd000280 cpuid 0x606a6) - * CPU microcode is the latest known available version: NO (latest version is 0xd0002a0 dated 2021/04/25 according to builtin firmwares DB v191+i20210217) - * CPU vulnerability to the speculative execution attack variants - * Affected by CVE-2017-5753 (Spectre Variant 1, bounds check bypass): YES - * Affected by CVE-2017-5715 (Spectre Variant 2, branch target injection): YES - * Affected by CVE-2017-5754 (Variant 3, Meltdown, rogue data cache load): NO - * Affected by CVE-2018-3640 (Variant 3a, rogue system register read): YES - * Affected by CVE-2018-3639 (Variant 4, speculative store bypass): YES - * Affected by CVE-2018-3615 (Foreshadow (SGX), L1 terminal fault): YES - * Affected by CVE-2018-3620 (Foreshadow-NG (OS), L1 terminal fault): YES - * Affected by CVE-2018-3646 (Foreshadow-NG (VMM), L1 terminal fault): YES - * Affected by CVE-2018-12126 (Fallout, microarchitectural store buffer data sampling (MSBDS)): NO - * Affected by CVE-2018-12130 (ZombieLoad, microarchitectural fill buffer data sampling (MFBDS)): NO - * Affected by CVE-2018-12127 (RIDL, microarchitectural load port data sampling (MLPDS)): NO - * Affected by CVE-2019-11091 (RIDL, microarchitectural data sampling uncacheable memory (MDSUM)): NO - * Affected by CVE-2019-11135 (ZombieLoad V2, TSX Asynchronous Abort (TAA)): NO - * Affected by CVE-2018-12207 (No eXcuses, iTLB Multihit, machine check exception on page size changes (MCEPSC)): YES - * Affected by CVE-2020-0543 (Special Register Buffer Data Sampling (SRBDS)): NO - - CVE-2017-5753 aka Spectre Variant 1, bounds check bypass - * Mitigated according to the /sys interface: YES (Mitigation: usercopy/swapgs barriers and __user pointer sanitization) - > STATUS: UNKNOWN (/sys vulnerability interface use forced, but its not available!) - - CVE-2017-5715 aka Spectre Variant 2, branch target injection - * Mitigated according to the /sys interface: YES (Mitigation: Enhanced IBRS, IBPB: conditional, RSB filling) - > STATUS: VULNERABLE (IBRS+IBPB or retpoline+IBPB is needed to mitigate the vulnerability) - - CVE-2017-5754 aka Variant 3, Meltdown, rogue data cache load - * Mitigated according to the /sys interface: YES (Not affected) - * Running as a Xen PV DomU: NO - > STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not vulnerable) - - CVE-2018-3640 aka Variant 3a, rogue system register read - * CPU microcode mitigates the vulnerability: YES - > STATUS: NOT VULNERABLE (your CPU microcode mitigates the vulnerability) - - CVE-2018-3639 aka Variant 4, speculative store bypass - * Mitigated according to the /sys interface: YES (Mitigation: Speculative Store Bypass disabled via prctl and seccomp) - > STATUS: NOT VULNERABLE (Mitigation: Speculative Store Bypass disabled via prctl and seccomp) - - CVE-2018-3615 aka Foreshadow (SGX), L1 terminal fault - * CPU microcode mitigates the vulnerability: YES - > STATUS: NOT VULNERABLE (your CPU microcode mitigates the vulnerability) - - CVE-2018-3620 aka Foreshadow-NG (OS), L1 terminal fault - * Mitigated according to the /sys interface: YES (Not affected) - > STATUS: NOT VULNERABLE (Not affected) - - CVE-2018-3646 aka Foreshadow-NG (VMM), L1 terminal fault - * Information from the /sys interface: Not affected - > STATUS: NOT VULNERABLE (your kernel reported your CPU model as not vulnerable) - - CVE-2018-12126 aka Fallout, microarchitectural store buffer data sampling (MSBDS) - * Mitigated according to the /sys interface: YES (Not affected) - > STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not vulnerable) - - CVE-2018-12130 aka ZombieLoad, microarchitectural fill buffer data sampling (MFBDS) - * Mitigated according to the /sys interface: YES (Not affected) - > STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not vulnerable) - - CVE-2018-12127 aka RIDL, microarchitectural load port data sampling (MLPDS) - * Mitigated according to the /sys interface: YES (Not affected) - > STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not vulnerable) - - CVE-2019-11091 aka RIDL, microarchitectural data sampling uncacheable memory (MDSUM) - * Mitigated according to the /sys interface: YES (Not affected) - > STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not vulnerable) - - CVE-2019-11135 aka ZombieLoad V2, TSX Asynchronous Abort (TAA) - * Mitigated according to the /sys interface: YES (Not affected) - > STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not vulnerable) - - CVE-2018-12207 aka No eXcuses, iTLB Multihit, machine check exception on page size changes (MCEPSC) - * Mitigated according to the /sys interface: YES (Not affected) - > STATUS: NOT VULNERABLE (Not affected) - - CVE-2020-0543 aka Special Register Buffer Data Sampling (SRBDS) - * Mitigated according to the /sys interface: YES (Not affected) - > STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not vulnerable) - - > SUMMARY: CVE-2017-5753:?? CVE-2017-5715:KO CVE-2017-5754:OK CVE-2018-3640:OK CVE-2018-3639:OK CVE-2018-3615:OK CVE-2018-3620:OK CVE-2018-3646:OK CVE-2018-12126:OK CVE-2018-12130:OK CVE-2018-12127:OK CVE-2019-11091:OK CVE-2019-11135:OK CVE-2018-12207:OK CVE-2020-0543:OK diff --git a/docs/report/introduction/test_environment_sut_meltspec_skx.rst b/docs/report/introduction/test_environment_sut_meltspec_skx.rst deleted file mode 100644 index 0e2f5b9783..0000000000 --- a/docs/report/introduction/test_environment_sut_meltspec_skx.rst +++ /dev/null @@ -1,178 +0,0 @@ -Spectre and Meltdown Checks -^^^^^^^^^^^^^^^^^^^^^^^^^^^ - -Following section displays the output of a running shell script to tell if -system is vulnerable against the several "speculative execution" CVEs that were -made public in 2018. Script is available on `Spectre & Meltdown Checker Github -<https://github.com/speed47/spectre-meltdown-checker>`_. - -:: - - Spectre and Meltdown mitigation detection tool v0.44+ - - Checking for vulnerabilities on current system - Kernel is Linux 5.4.0-65-generic #73-Ubuntu SMP Mon Jan 18 17:25:17 UTC 2021 x86_64 - CPU is Intel(R) Xeon(R) Platinum 8180 CPU @ 2.50GHz - - Hardware check - * Hardware support (CPU microcode) for mitigation techniques - * Indirect Branch Restricted Speculation (IBRS) - * SPEC_CTRL MSR is available: YES - * CPU indicates IBRS capability: YES (SPEC_CTRL feature bit) - * Indirect Branch Prediction Barrier (IBPB) - * PRED_CMD MSR is available: YES - * CPU indicates IBPB capability: YES (SPEC_CTRL feature bit) - * Single Thread Indirect Branch Predictors (STIBP) - * SPEC_CTRL MSR is available: YES - * CPU indicates STIBP capability: YES (Intel STIBP feature bit) - * Speculative Store Bypass Disable (SSBD) - * CPU indicates SSBD capability: YES (Intel SSBD) - * L1 data cache invalidation - * FLUSH_CMD MSR is available: YES - * CPU indicates L1D flush capability: YES (L1D flush feature bit) - * Microarchitectural Data Sampling - * VERW instruction is available: YES (MD_CLEAR feature bit) - * Enhanced IBRS (IBRS_ALL) - * CPU indicates ARCH_CAPABILITIES MSR availability: NO - * ARCH_CAPABILITIES MSR advertises IBRS_ALL capability: NO - * CPU explicitly indicates not being vulnerable to Meltdown/L1TF (RDCL_NO): NO - * CPU explicitly indicates not being vulnerable to Variant 4 (SSB_NO): NO - * CPU/Hypervisor indicates L1D flushing is not necessary on this system: NO - * Hypervisor indicates host CPU might be vulnerable to RSB underflow (RSBA): NO - * CPU explicitly indicates not being vulnerable to Microarchitectural Data Sampling (MDS_NO): NO - * CPU explicitly indicates not being vulnerable to TSX Asynchronous Abort (TAA_NO): NO - * CPU explicitly indicates not being vulnerable to iTLB Multihit (PSCHANGE_MSC_NO): NO - * CPU explicitly indicates having MSR for TSX control (TSX_CTRL_MSR): NO - * CPU supports Transactional Synchronization Extensions (TSX): YES (RTM feature bit) - * CPU supports Software Guard Extensions (SGX): NO - * CPU supports Special Register Buffer Data Sampling (SRBDS): NO - * CPU microcode is known to cause stability problems: NO (family 0x6 model 0x55 stepping 0x4 ucode 0x2000065 cpuid 0x50654) - * CPU microcode is the latest known available version: NO (latest version is 0x2006b06 dated 2021/03/08 according to builtin firmwares DB v191+i20210217) - * CPU vulnerability to the speculative execution attack variants - * Affected by CVE-2017-5753 (Spectre Variant 1, bounds check bypass): YES - * Affected by CVE-2017-5715 (Spectre Variant 2, branch target injection): YES - * Affected by CVE-2017-5754 (Variant 3, Meltdown, rogue data cache load): YES - * Affected by CVE-2018-3640 (Variant 3a, rogue system register read): YES - * Affected by CVE-2018-3639 (Variant 4, speculative store bypass): YES - * Affected by CVE-2018-3615 (Foreshadow (SGX), L1 terminal fault): NO - * Affected by CVE-2018-3620 (Foreshadow-NG (OS), L1 terminal fault): YES - * Affected by CVE-2018-3646 (Foreshadow-NG (VMM), L1 terminal fault): YES - * Affected by CVE-2018-12126 (Fallout, microarchitectural store buffer data sampling (MSBDS)): YES - * Affected by CVE-2018-12130 (ZombieLoad, microarchitectural fill buffer data sampling (MFBDS)): YES - * Affected by CVE-2018-12127 (RIDL, microarchitectural load port data sampling (MLPDS)): YES - * Affected by CVE-2019-11091 (RIDL, microarchitectural data sampling uncacheable memory (MDSUM)): YES - * Affected by CVE-2019-11135 (ZombieLoad V2, TSX Asynchronous Abort (TAA)): YES - * Affected by CVE-2018-12207 (No eXcuses, iTLB Multihit, machine check exception on page size changes (MCEPSC)): YES - * Affected by CVE-2020-0543 (Special Register Buffer Data Sampling (SRBDS)): NO - - CVE-2017-5753 aka Spectre Variant 1, bounds check bypass - * Mitigated according to the /sys interface: YES (Mitigation: usercopy/swapgs barriers and __user pointer sanitization) - * Kernel has array_index_mask_nospec: YES (1 occurrence(s) found of x86 64 bits array_index_mask_nospec()) - * Kernel has the Red Hat/Ubuntu patch: NO - * Kernel has mask_nospec64 (arm64): NO - * Kernel has array_index_nospec (arm64): NO - > STATUS: NOT VULNERABLE (Mitigation: usercopy/swapgs barriers and __user pointer sanitization) - - CVE-2017-5715 aka Spectre Variant 2, branch target injection - * Mitigated according to the /sys interface: YES (Mitigation: Full generic retpoline, IBPB: conditional, IBRS_FW, STIBP: conditional, RSB filling) - * Mitigation 1 - * Kernel is compiled with IBRS support: YES - * IBRS enabled and active: YES (for firmware code only) - * Kernel is compiled with IBPB support: YES - * IBPB enabled and active: YES - * Mitigation 2 - * Kernel has branch predictor hardening (arm): NO - * Kernel compiled with retpoline option: YES - * Kernel compiled with a retpoline-aware compiler: YES (kernel reports full retpoline compilation) - * Kernel supports RSB filling: YES - > STATUS: NOT VULNERABLE (Full retpoline + IBPB are mitigating the vulnerability) - - CVE-2017-5754 aka Variant 3, Meltdown, rogue data cache load - * Mitigated according to the /sys interface: YES (Mitigation: PTI) - * Kernel supports Page Table Isolation (PTI): YES - * PTI enabled and active: YES - * Reduced performance impact of PTI: YES (CPU supports INVPCID, performance impact of PTI will be greatly reduced) - * Running as a Xen PV DomU: NO - > STATUS: NOT VULNERABLE (Mitigation: PTI) - - CVE-2018-3640 aka Variant 3a, rogue system register read - * CPU microcode mitigates the vulnerability: YES - > STATUS: NOT VULNERABLE (your CPU microcode mitigates the vulnerability) - - CVE-2018-3639 aka Variant 4, speculative store bypass - * Mitigated according to the /sys interface: YES (Mitigation: Speculative Store Bypass disabled via prctl and seccomp) - * Kernel supports disabling speculative store bypass (SSB): YES (found in /proc/self/status) - * SSB mitigation is enabled and active: YES (per-thread through prctl) - * SSB mitigation currently active for selected processes: YES (boltd fwupd irqbalance systemd-journald systemd-logind systemd-networkd systemd-resolved systemd-timesyncd systemd-udevd) - > STATUS: NOT VULNERABLE (Mitigation: Speculative Store Bypass disabled via prctl and seccomp) - - CVE-2018-3615 aka Foreshadow (SGX), L1 terminal fault - * CPU microcode mitigates the vulnerability: N/A - > STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not vulnerable) - - CVE-2018-3620 aka Foreshadow-NG (OS), L1 terminal fault - * Mitigated according to the /sys interface: YES (Mitigation: PTE Inversion; VMX: conditional cache flushes, SMT vulnerable) - * Kernel supports PTE inversion: YES (found in kernel image) - * PTE inversion enabled and active: YES - > STATUS: NOT VULNERABLE (Mitigation: PTE Inversion; VMX: conditional cache flushes, SMT vulnerable) - - CVE-2018-3646 aka Foreshadow-NG (VMM), L1 terminal fault - * Information from the /sys interface: Mitigation: PTE Inversion; VMX: conditional cache flushes, SMT vulnerable - * This system is a host running a hypervisor: NO - * Mitigation 1 (KVM) - * EPT is disabled: NO - * Mitigation 2 - * L1D flush is supported by kernel: YES (found flush_l1d in /proc/cpuinfo) - * L1D flush enabled: YES (conditional flushes) - * Hardware-backed L1D flush supported: YES (performance impact of the mitigation will be greatly reduced) - * Hyper-Threading (SMT) is enabled: YES - > STATUS: NOT VULNERABLE (this system is not running a hypervisor) - - CVE-2018-12126 aka Fallout, microarchitectural store buffer data sampling (MSBDS) - * Mitigated according to the /sys interface: YES (Mitigation: Clear CPU buffers; SMT vulnerable) - * Kernel supports using MD_CLEAR mitigation: YES (md_clear found in /proc/cpuinfo) - * Kernel mitigation is enabled and active: YES - * SMT is either mitigated or disabled: NO - > STATUS: NOT VULNERABLE (Your microcode and kernel are both up to date for this mitigation, and mitigation is enabled) - - CVE-2018-12130 aka ZombieLoad, microarchitectural fill buffer data sampling (MFBDS) - * Mitigated according to the /sys interface: YES (Mitigation: Clear CPU buffers; SMT vulnerable) - * Kernel supports using MD_CLEAR mitigation: YES (md_clear found in /proc/cpuinfo) - * Kernel mitigation is enabled and active: YES - * SMT is either mitigated or disabled: NO - > STATUS: NOT VULNERABLE (Your microcode and kernel are both up to date for this mitigation, and mitigation is enabled) - - CVE-2018-12127 aka RIDL, microarchitectural load port data sampling (MLPDS) - * Mitigated according to the /sys interface: YES (Mitigation: Clear CPU buffers; SMT vulnerable) - * Kernel supports using MD_CLEAR mitigation: YES (md_clear found in /proc/cpuinfo) - * Kernel mitigation is enabled and active: YES - * SMT is either mitigated or disabled: NO - > STATUS: NOT VULNERABLE (Your microcode and kernel are both up to date for this mitigation, and mitigation is enabled) - - CVE-2019-11091 aka RIDL, microarchitectural data sampling uncacheable memory (MDSUM) - * Mitigated according to the /sys interface: YES (Mitigation: Clear CPU buffers; SMT vulnerable) - * Kernel supports using MD_CLEAR mitigation: YES (md_clear found in /proc/cpuinfo) - * Kernel mitigation is enabled and active: YES - * SMT is either mitigated or disabled: NO - > STATUS: NOT VULNERABLE (Your microcode and kernel are both up to date for this mitigation, and mitigation is enabled) - - CVE-2019-11135 aka ZombieLoad V2, TSX Asynchronous Abort (TAA) - * Mitigated according to the /sys interface: YES (Mitigation: Clear CPU buffers; SMT vulnerable) - * TAA mitigation is supported by kernel: YES (found tsx_async_abort in kernel image) - * TAA mitigation enabled and active: YES (Mitigation: Clear CPU buffers; SMT vulnerable) - > STATUS: NOT VULNERABLE (Mitigation: Clear CPU buffers; SMT vulnerable) - - CVE-2018-12207 aka No eXcuses, iTLB Multihit, machine check exception on page size changes (MCEPSC) - * Mitigated according to the /sys interface: YES (KVM: Mitigation: Split huge pages) - * This system is a host running a hypervisor: NO - * iTLB Multihit mitigation is supported by kernel: YES (found itlb_multihit in kernel image) - * iTLB Multihit mitigation enabled and active: YES (KVM: Mitigation: Split huge pages) - > STATUS: NOT VULNERABLE (this system is not running a hypervisor) - - CVE-2020-0543 aka Special Register Buffer Data Sampling (SRBDS) - * Mitigated according to the /sys interface: YES (Not affected) - * SRBDS mitigation control is supported by the kernel: YES (found SRBDS implementation evidence in kernel image. Your kernel is up to date for SRBDS mitigation) - * SRBDS mitigation control is enabled and active: NO - > STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not vulnerable) - - > SUMMARY: CVE-2017-5753:OK CVE-2017-5715:OK CVE-2017-5754:OK CVE-2018-3640:OK CVE-2018-3639:OK CVE-2018-3615:OK CVE-2018-3620:OK CVE-2018-3646:OK CVE-2018-12126:OK CVE-2018-12130:OK CVE-2018-12127:OK CVE-2019-11091:OK CVE-2019-11135:OK CVE-2018-12207:OK CVE-2020-0543:OK diff --git a/docs/report/introduction/test_environment_sut_meltspec_tsh.rst b/docs/report/introduction/test_environment_sut_meltspec_tsh.rst deleted file mode 100644 index c583d5f273..0000000000 --- a/docs/report/introduction/test_environment_sut_meltspec_tsh.rst +++ /dev/null @@ -1,452 +0,0 @@ -Spectre and Meltdown Checks -^^^^^^^^^^^^^^^^^^^^^^^^^^^ - -Following section displays the output of a running shell script to tell if -system is vulnerable against the several "speculative execution" CVEs that were -made public in 2018. Script is available on `Spectre & Meltdown Checker Github -<https://github.com/speed47/spectre-meltdown-checker>`_. - -:: - - Spectre and Meltdown mitigation detection tool v0.44+ - - Checking for vulnerabilities on current system - Kernel is Linux 5.4.0-65-generic #73-Ubuntu SMP Mon Jan 18 17:25:17 UTC 2021 x86_64 - CPU is Intel(R) Xeon(R) Platinum 8180 CPU @ 2.50GHz - - Hardware check - * Hardware support (CPU microcode) for mitigation techniques - * Indirect Branch Restricted Speculation (IBRS) - * SPEC_CTRL MSR is available: YES - * CPU indicates IBRS capability: YES (SPEC_CTRL feature bit) - * Indirect Branch Prediction Barrier (IBPB) - * PRED_CMD MSR is available: YES - * CPU indicates IBPB capability: YES (SPEC_CTRL feature bit) - * Single Thread Indirect Branch Predictors (STIBP) - * SPEC_CTRL MSR is available: YES - * CPU indicates STIBP capability: YES (Intel STIBP feature bit) - * Speculative Store Bypass Disable (SSBD) - * CPU indicates SSBD capability: YES (Intel SSBD) - * L1 data cache invalidation - * FLUSH_CMD MSR is available: YES - * CPU indicates L1D flush capability: YES (L1D flush feature bit) - * Microarchitectural Data Sampling - * VERW instruction is available: YES (MD_CLEAR feature bit) - * Enhanced IBRS (IBRS_ALL) - * CPU indicates ARCH_CAPABILITIES MSR availability: NO - * ARCH_CAPABILITIES MSR advertises IBRS_ALL capability: NO - * CPU explicitly indicates not being vulnerable to Meltdown/L1TF (RDCL_NO): NO - * CPU explicitly indicates not being vulnerable to Variant 4 (SSB_NO): NO - * CPU/Hypervisor indicates L1D flushing is not necessary on this system: NO - * Hypervisor indicates host CPU might be vulnerable to RSB underflow (RSBA): NO - * CPU explicitly indicates not being vulnerable to Microarchitectural Data Sampling (MDS_NO): NO - * CPU explicitly indicates not being vulnerable to TSX Asynchronous Abort (TAA_NO): NO - * CPU explicitly indicates not being vulnerable to iTLB Multihit (PSCHANGE_MSC_NO): NO - * CPU explicitly indicates having MSR for TSX control (TSX_CTRL_MSR): NO - * CPU supports Transactional Synchronization Extensions (TSX): YES (RTM feature bit) - * CPU supports Software Guard Extensions (SGX): NO - * CPU supports Special Register Buffer Data Sampling (SRBDS): NO - * CPU microcode is known to cause stability problems: NO (family 0x6 model 0x55 stepping 0x4 ucode 0x2000065 cpuid 0x50654) - * CPU microcode is the latest known available version: NO (latest version is 0x2006b06 dated 2021/03/08 according to builtin firmwares DB v191+i20210217) - * CPU vulnerability to the speculative execution attack variants - * Affected by CVE-2017-5753 (Spectre Variant 1, bounds check bypass): YES - * Affected by CVE-2017-5715 (Spectre Variant 2, branch target injection): YES - * Affected by CVE-2017-5754 (Variant 3, Meltdown, rogue data cache load): YES - * Affected by CVE-2018-3640 (Variant 3a, rogue system register read): YES - * Affected by CVE-2018-3639 (Variant 4, speculative store bypass): YES - * Affected by CVE-2018-3615 (Foreshadow (SGX), L1 terminal fault): NO - * Affected by CVE-2018-3620 (Foreshadow-NG (OS), L1 terminal fault): YES - * Affected by CVE-2018-3646 (Foreshadow-NG (VMM), L1 terminal fault): YES - * Affected by CVE-2018-12126 (Fallout, microarchitectural store buffer data sampling (MSBDS)): YES - * Affected by CVE-2018-12130 (ZombieLoad, microarchitectural fill buffer data sampling (MFBDS)): YES - * Affected by CVE-2018-12127 (RIDL, microarchitectural load port data sampling (MLPDS)): YES - * Affected by CVE-2019-11091 (RIDL, microarchitectural data sampling uncacheable memory (MDSUM)): YES - * Affected by CVE-2019-11135 (ZombieLoad V2, TSX Asynchronous Abort (TAA)): YES - * Affected by CVE-2018-12207 (No eXcuses, iTLB Multihit, machine check exception on page size changes (MCEPSC)): YES - * Affected by CVE-2020-0543 (Special Register Buffer Data Sampling (SRBDS)): NO - - CVE-2017-5753 aka Spectre Variant 1, bounds check bypass - * Mitigated according to the /sys interface: YES (Mitigation: usercopy/swapgs barriers and __user pointer sanitization) - * Kernel has array_index_mask_nospec: YES (1 occurrence(s) found of x86 64 bits array_index_mask_nospec()) - * Kernel has the Red Hat/Ubuntu patch: NO - * Kernel has mask_nospec64 (arm64): NO - * Kernel has array_index_nospec (arm64): NO - > STATUS: NOT VULNERABLE (Mitigation: usercopy/swapgs barriers and __user pointer sanitization) - - CVE-2017-5715 aka Spectre Variant 2, branch target injection - * Mitigated according to the /sys interface: YES (Mitigation: Full generic retpoline, IBPB: conditional, IBRS_FW, STIBP: conditional, RSB filling) - * Mitigation 1 - * Kernel is compiled with IBRS support: YES - * IBRS enabled and active: YES (for firmware code only) - * Kernel is compiled with IBPB support: YES - * IBPB enabled and active: YES - * Mitigation 2 - * Kernel has branch predictor hardening (arm): NO - * Kernel compiled with retpoline option: YES - * Kernel compiled with a retpoline-aware compiler: YES (kernel reports full retpoline compilation) - * Kernel supports RSB filling: YES - > STATUS: NOT VULNERABLE (Full retpoline + IBPB are mitigating the vulnerability) - - CVE-2017-5754 aka Variant 3, Meltdown, rogue data cache load - * Mitigated according to the /sys interface: YES (Mitigation: PTI) - * Kernel supports Page Table Isolation (PTI): YES - * PTI enabled and active: YES - * Reduced performance impact of PTI: YES (CPU supports INVPCID, performance impact of PTI will be greatly reduced) - * Running as a Xen PV DomU: NO - > STATUS: NOT VULNERABLE (Mitigation: PTI) - - CVE-2018-3640 aka Variant 3a, rogue system register read - * CPU microcode mitigates the vulnerability: YES - > STATUS: NOT VULNERABLE (your CPU microcode mitigates the vulnerability) - - CVE-2018-3639 aka Variant 4, speculative store bypass - * Mitigated according to the /sys interface: YES (Mitigation: Speculative Store Bypass disabled via prctl and seccomp) - * Kernel supports disabling speculative store bypass (SSB): YES (found in /proc/self/status) - * SSB mitigation is enabled and active: YES (per-thread through prctl) - * SSB mitigation currently active for selected processes: YES (boltd fwupd irqbalance systemd-journald systemd-logind systemd-networkd systemd-resolved systemd-timesyncd systemd-udevd) - > STATUS: NOT VULNERABLE (Mitigation: Speculative Store Bypass disabled via prctl and seccomp) - - CVE-2018-3615 aka Foreshadow (SGX), L1 terminal fault - * CPU microcode mitigates the vulnerability: N/A - > STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not vulnerable) - - CVE-2018-3620 aka Foreshadow-NG (OS), L1 terminal fault - * Mitigated according to the /sys interface: YES (Mitigation: PTE Inversion; VMX: conditional cache flushes, SMT vulnerable) - * Kernel supports PTE inversion: YES (found in kernel image) - * PTE inversion enabled and active: YES - > STATUS: NOT VULNERABLE (Mitigation: PTE Inversion; VMX: conditional cache flushes, SMT vulnerable) - - CVE-2018-3646 aka Foreshadow-NG (VMM), L1 terminal fault - * Information from the /sys interface: Mitigation: PTE Inversion; VMX: conditional cache flushes, SMT vulnerable - * This system is a host running a hypervisor: NO - * Mitigation 1 (KVM) - * EPT is disabled: NO - * Mitigation 2 - * L1D flush is supported by kernel: YES (found flush_l1d in /proc/cpuinfo) - * L1D flush enabled: YES (conditional flushes) - * Hardware-backed L1D flush supported: YES (performance impact of the mitigation will be greatly reduced) - * Hyper-Threading (SMT) is enabled: YES - > STATUS: NOT VULNERABLE (this system is not running a hypervisor) - - CVE-2018-12126 aka Fallout, microarchitectural store buffer data sampling (MSBDS) - * Mitigated according to the /sys interface: YES (Mitigation: Clear CPU buffers; SMT vulnerable) - * Kernel supports using MD_CLEAR mitigation: YES (md_clear found in /proc/cpuinfo) - * Kernel mitigation is enabled and active: YES - * SMT is either mitigated or disabled: NO - > STATUS: NOT VULNERABLE (Your microcode and kernel are both up to date for this mitigation, and mitigation is enabled) - - CVE-2018-12130 aka ZombieLoad, microarchitectural fill buffer data sampling (MFBDS) - * Mitigated according to the /sys interface: YES (Mitigation: Clear CPU buffers; SMT vulnerable) - * Kernel supports using MD_CLEAR mitigation: YES (md_clear found in /proc/cpuinfo) - * Kernel mitigation is enabled and active: YES - * SMT is either mitigated or disabled: NO - > STATUS: NOT VULNERABLE (Your microcode and kernel are both up to date for this mitigation, and mitigation is enabled) - - CVE-2018-12127 aka RIDL, microarchitectural load port data sampling (MLPDS) - * Mitigated according to the /sys interface: YES (Mitigation: Clear CPU buffers; SMT vulnerable) - * Kernel supports using MD_CLEAR mitigation: YES (md_clear found in /proc/cpuinfo) - * Kernel mitigation is enabled and active: YES - * SMT is either mitigated or disabled: NO - > STATUS: NOT VULNERABLE (Your microcode and kernel are both up to date for this mitigation, and mitigation is enabled) - - CVE-2019-11091 aka RIDL, microarchitectural data sampling uncacheable memory (MDSUM) - * Mitigated according to the /sys interface: YES (Mitigation: Clear CPU buffers; SMT vulnerable) - * Kernel supports using MD_CLEAR mitigation: YES (md_clear found in /proc/cpuinfo) - * Kernel mitigation is enabled and active: YES - * SMT is either mitigated or disabled: NO - > STATUS: NOT VULNERABLE (Your microcode and kernel are both up to date for this mitigation, and mitigation is enabled) - - CVE-2019-11135 aka ZombieLoad V2, TSX Asynchronous Abort (TAA) - * Mitigated according to the /sys interface: YES (Mitigation: Clear CPU buffers; SMT vulnerable) - * TAA mitigation is supported by kernel: YES (found tsx_async_abort in kernel image) - * TAA mitigation enabled and active: YES (Mitigation: Clear CPU buffers; SMT vulnerable) - > STATUS: NOT VULNERABLE (Mitigation: Clear CPU buffers; SMT vulnerable) - - CVE-2018-12207 aka No eXcuses, iTLB Multihit, machine check exception on page size changes (MCEPSC) - * Mitigated according to the /sys interface: YES (KVM: Mitigation: Split huge pages) - * This system is a host running a hypervisor: NO - * iTLB Multihit mitigation is supported by kernel: YES (found itlb_multihit in kernel image) - * iTLB Multihit mitigation enabled and active: YES (KVM: Mitigation: Split huge pages) - > STATUS: NOT VULNERABLE (this system is not running a hypervisor) - - CVE-2020-0543 aka Special Register Buffer Data Sampling (SRBDS) - * Mitigated according to the /sys interface: YES (Not affected) - * SRBDS mitigation control is supported by the kernel: YES (found SRBDS implementation evidence in kernel image. Your kernel is up to date for SRBDS mitigation) - * SRBDS mitigation control is enabled and active: NO - > STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not vulnerable) - - > SUMMARY: CVE-2017-5753:OK CVE-2017-5715:OK CVE-2017-5754:OK CVE-2018-3640:OK CVE-2018-3639:OK CVE-2018-3615:OK CVE-2018-3620:OK CVE-2018-3646:OK CVE-2018-12126:OK CVE-2018-12130:OK CVE-2018-12127:OK CVE-2019-11091:OK CVE-2019-11135:OK CVE-2018-12207:OK CVE-2020-0543:OK - -:: - - Spectre and Meltdown mitigation detection tool v0.44+ - - Checking for vulnerabilities on current system - Kernel is Linux 5.4.0-65-generic #73-Ubuntu SMP Mon Jan 18 17:27:25 UTC 2021 aarch64 - CPU is ARM v8 model 0xd08 - - Hardware check - * CPU vulnerability to the speculative execution attack variants - * Affected by CVE-2017-5753 (Spectre Variant 1, bounds check bypass): YES - * Affected by CVE-2017-5715 (Spectre Variant 2, branch target injection): YES - * Affected by CVE-2017-5754 (Variant 3, Meltdown, rogue data cache load): NO - * Affected by CVE-2018-3640 (Variant 3a, rogue system register read): YES - * Affected by CVE-2018-3639 (Variant 4, speculative store bypass): YES - * Affected by CVE-2018-3615 (Foreshadow (SGX), L1 terminal fault): NO - * Affected by CVE-2018-3620 (Foreshadow-NG (OS), L1 terminal fault): NO - * Affected by CVE-2018-3646 (Foreshadow-NG (VMM), L1 terminal fault): NO - * Affected by CVE-2018-12126 (Fallout, microarchitectural store buffer data sampling (MSBDS)): NO - * Affected by CVE-2018-12130 (ZombieLoad, microarchitectural fill buffer data sampling (MFBDS)): NO - * Affected by CVE-2018-12127 (RIDL, microarchitectural load port data sampling (MLPDS)): NO - * Affected by CVE-2019-11091 (RIDL, microarchitectural data sampling uncacheable memory (MDSUM)): NO - * Affected by CVE-2019-11135 (ZombieLoad V2, TSX Asynchronous Abort (TAA)): NO - * Affected by CVE-2018-12207 (No eXcuses, iTLB Multihit, machine check exception on page size changes (MCEPSC)): NO - * Affected by CVE-2020-0543 (Special Register Buffer Data Sampling (SRBDS)): NO - - CVE-2017-5753 aka Spectre Variant 1, bounds check bypass - * Mitigated according to the /sys interface: YES (Mitigation: __user pointer sanitization) - * Kernel has array_index_mask_nospec: NO - * Kernel has the Red Hat/Ubuntu patch: NO - * Kernel has mask_nospec64 (arm64): NO - * Kernel has array_index_nospec (arm64): NO - * Checking count of LFENCE instructions following a jump in kernel... NO (only 0 jump-then-lfence instructions found, should be >= 30 (heuristic)) - > STATUS: NOT VULNERABLE (Mitigation: __user pointer sanitization) - - CVE-2017-5715 aka Spectre Variant 2, branch target injection - * Mitigated according to the /sys interface: NO (Vulnerable) - * Mitigation 1 - * Kernel is compiled with IBRS support: YES - * IBRS enabled and active: NO - * Kernel is compiled with IBPB support: NO - * IBPB enabled and active: NO - * Mitigation 2 - * Kernel has branch predictor hardening (arm): YES - * Kernel compiled with retpoline option: NO - > STATUS: NOT VULNERABLE (Branch predictor hardening mitigates the vulnerability) - - CVE-2017-5754 aka Variant 3, Meltdown, rogue data cache load - * Mitigated according to the /sys interface: YES (Not affected) - * Kernel supports Page Table Isolation (PTI): YES - * PTI enabled and active: UNKNOWN (dmesg truncated, please reboot and relaunch this script) - * Reduced performance impact of PTI: NO (PCID/INVPCID not supported, performance impact of PTI will be significant) - * Running as a Xen PV DomU: NO - > STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not vulnerable) - - CVE-2018-3640 aka Variant 3a, rogue system register read - * CPU microcode mitigates the vulnerability: NO - > STATUS: VULNERABLE (an up-to-date CPU microcode is needed to mitigate this vulnerability) - - CVE-2018-3639 aka Variant 4, speculative store bypass - * Mitigated according to the /sys interface: NO (Vulnerable) - * Kernel supports disabling speculative store bypass (SSB): YES (found in /proc/self/status) - * SSB mitigation is enabled and active: NO - > STATUS: VULNERABLE (Your CPU doesnt support SSBD) - - CVE-2018-3615 aka Foreshadow (SGX), L1 terminal fault - * CPU microcode mitigates the vulnerability: N/A - > STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not vulnerable) - - CVE-2018-3620 aka Foreshadow-NG (OS), L1 terminal fault - * Mitigated according to the /sys interface: YES (Not affected) - * Kernel supports PTE inversion: NO - * PTE inversion enabled and active: NO - > STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not vulnerable) - - CVE-2018-3646 aka Foreshadow-NG (VMM), L1 terminal fault - * Information from the /sys interface: Not affected - * This system is a host running a hypervisor: NO - * Mitigation 1 (KVM) - * EPT is disabled: N/A (the kvm_intel module is not loaded) - * Mitigation 2 - * L1D flush is supported by kernel: NO - * L1D flush enabled: NO - * Hardware-backed L1D flush supported: NO (flush will be done in software, this is slower) - * Hyper-Threading (SMT) is enabled: UNKNOWN - > STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not vulnerable) - - CVE-2018-12126 aka Fallout, microarchitectural store buffer data sampling (MSBDS) - * Mitigated according to the /sys interface: YES (Not affected) - * Kernel supports using MD_CLEAR mitigation: NO - * Kernel mitigation is enabled and active: NO - * SMT is either mitigated or disabled: NO - > STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not vulnerable) - - CVE-2018-12130 aka ZombieLoad, microarchitectural fill buffer data sampling (MFBDS) - * Mitigated according to the /sys interface: YES (Not affected) - * Kernel supports using MD_CLEAR mitigation: NO - * Kernel mitigation is enabled and active: NO - * SMT is either mitigated or disabled: NO - > STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not vulnerable) - - CVE-2018-12127 aka RIDL, microarchitectural load port data sampling (MLPDS) - * Mitigated according to the /sys interface: YES (Not affected) - * Kernel supports using MD_CLEAR mitigation: NO - * Kernel mitigation is enabled and active: NO - * SMT is either mitigated or disabled: NO - > STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not vulnerable) - - CVE-2019-11091 aka RIDL, microarchitectural data sampling uncacheable memory (MDSUM) - * Mitigated according to the /sys interface: YES (Not affected) - * Kernel supports using MD_CLEAR mitigation: NO - * Kernel mitigation is enabled and active: NO - * SMT is either mitigated or disabled: NO - > STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not vulnerable) - - CVE-2019-11135 aka ZombieLoad V2, TSX Asynchronous Abort (TAA) - * Mitigated according to the /sys interface: YES (Not affected) - * TAA mitigation is supported by kernel: YES (found tsx_async_abort in kernel image) - * TAA mitigation enabled and active: NO - > STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not vulnerable) - - CVE-2018-12207 aka No eXcuses, iTLB Multihit, machine check exception on page size changes (MCEPSC) - * Mitigated according to the /sys interface: YES (Not affected) - * This system is a host running a hypervisor: NO - * iTLB Multihit mitigation is supported by kernel: YES (found itlb_multihit in kernel image) - * iTLB Multihit mitigation enabled and active: NO - > STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not vulnerable) - - CVE-2020-0543 aka Special Register Buffer Data Sampling (SRBDS) - * Mitigated according to the /sys interface: YES (Not affected) - * SRBDS mitigation control is supported by the kernel: NO - * SRBDS mitigation control is enabled and active: NO - > STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not vulnerable) - - > SUMMARY: CVE-2017-5753:OK CVE-2017-5715:OK CVE-2017-5754:OK CVE-2018-3640:KO CVE-2018-3639:KO CVE-2018-3615:OK CVE-2018-3620:OK CVE-2018-3646:OK CVE-2018-12126:OK CVE-2018-12130:OK CVE-2018-12127:OK CVE-2019-11091:OK CVE-2019-11135:OK CVE-2018-12207:OK CVE-2020-0543:OK - - Need more detailed information about mitigation options? Use --explain - A false sense of security is worse than no security at all, see --disclaimer - ok: [10.30.51.37] => - spectre_meltdown_poll_results.stdout_lines: - Spectre and Meltdown mitigation detection tool v0.44+ - - Checking for vulnerabilities on current system - Kernel is Linux 5.4.0-65-generic #73-Ubuntu SMP Mon Jan 18 17:27:25 UTC 2021 aarch64 - CPU is ARM v8 model 0xd08 - - Hardware check - * CPU vulnerability to the speculative execution attack variants - * Affected by CVE-2017-5753 (Spectre Variant 1, bounds check bypass): YES - * Affected by CVE-2017-5715 (Spectre Variant 2, branch target injection): YES - * Affected by CVE-2017-5754 (Variant 3, Meltdown, rogue data cache load): NO - * Affected by CVE-2018-3640 (Variant 3a, rogue system register read): YES - * Affected by CVE-2018-3639 (Variant 4, speculative store bypass): YES - * Affected by CVE-2018-3615 (Foreshadow (SGX), L1 terminal fault): NO - * Affected by CVE-2018-3620 (Foreshadow-NG (OS), L1 terminal fault): NO - * Affected by CVE-2018-3646 (Foreshadow-NG (VMM), L1 terminal fault): NO - * Affected by CVE-2018-12126 (Fallout, microarchitectural store buffer data sampling (MSBDS)): NO - * Affected by CVE-2018-12130 (ZombieLoad, microarchitectural fill buffer data sampling (MFBDS)): NO - * Affected by CVE-2018-12127 (RIDL, microarchitectural load port data sampling (MLPDS)): NO - * Affected by CVE-2019-11091 (RIDL, microarchitectural data sampling uncacheable memory (MDSUM)): NO - * Affected by CVE-2019-11135 (ZombieLoad V2, TSX Asynchronous Abort (TAA)): NO - * Affected by CVE-2018-12207 (No eXcuses, iTLB Multihit, machine check exception on page size changes (MCEPSC)): NO - * Affected by CVE-2020-0543 (Special Register Buffer Data Sampling (SRBDS)): NO - - CVE-2017-5753 aka Spectre Variant 1, bounds check bypass - * Mitigated according to the /sys interface: YES (Mitigation: __user pointer sanitization) - * Kernel has array_index_mask_nospec: NO - * Kernel has the Red Hat/Ubuntu patch: NO - * Kernel has mask_nospec64 (arm64): NO - * Kernel has array_index_nospec (arm64): NO - * Checking count of LFENCE instructions following a jump in kernel... NO (only 0 jump-then-lfence instructions found, should be >= 30 (heuristic)) - > STATUS: NOT VULNERABLE (Mitigation: __user pointer sanitization) - - CVE-2017-5715 aka Spectre Variant 2, branch target injection - * Mitigated according to the /sys interface: NO (Vulnerable) - * Mitigation 1 - * Kernel is compiled with IBRS support: YES - * IBRS enabled and active: NO - * Kernel is compiled with IBPB support: NO - * IBPB enabled and active: NO - * Mitigation 2 - * Kernel has branch predictor hardening (arm): YES - * Kernel compiled with retpoline option: NO - > STATUS: NOT VULNERABLE (Branch predictor hardening mitigates the vulnerability) - - CVE-2017-5754 aka Variant 3, Meltdown, rogue data cache load - * Mitigated according to the /sys interface: YES (Not affected) - * Kernel supports Page Table Isolation (PTI): YES - * PTI enabled and active: UNKNOWN (dmesg truncated, please reboot and relaunch this script) - * Reduced performance impact of PTI: NO (PCID/INVPCID not supported, performance impact of PTI will be significant) - * Running as a Xen PV DomU: NO - > STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not vulnerable) - - CVE-2018-3640 aka Variant 3a, rogue system register read - * CPU microcode mitigates the vulnerability: NO - > STATUS: VULNERABLE (an up-to-date CPU microcode is needed to mitigate this vulnerability) - - CVE-2018-3639 aka Variant 4, speculative store bypass - * Mitigated according to the /sys interface: NO (Vulnerable) - * Kernel supports disabling speculative store bypass (SSB): YES (found in /proc/self/status) - * SSB mitigation is enabled and active: NO - > STATUS: VULNERABLE (Your CPU doesnt support SSBD) - - CVE-2018-3615 aka Foreshadow (SGX), L1 terminal fault - * CPU microcode mitigates the vulnerability: N/A - > STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not vulnerable) - - CVE-2018-3620 aka Foreshadow-NG (OS), L1 terminal fault - * Mitigated according to the /sys interface: YES (Not affected) - * Kernel supports PTE inversion: NO - * PTE inversion enabled and active: NO - > STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not vulnerable) - - CVE-2018-3646 aka Foreshadow-NG (VMM), L1 terminal fault - * Information from the /sys interface: Not affected - * This system is a host running a hypervisor: NO - * Mitigation 1 (KVM) - * EPT is disabled: N/A (the kvm_intel module is not loaded) - * Mitigation 2 - * L1D flush is supported by kernel: NO - * L1D flush enabled: NO - * Hardware-backed L1D flush supported: NO (flush will be done in software, this is slower) - * Hyper-Threading (SMT) is enabled: UNKNOWN - > STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not vulnerable) - - CVE-2018-12126 aka Fallout, microarchitectural store buffer data sampling (MSBDS) - * Mitigated according to the /sys interface: YES (Not affected) - * Kernel supports using MD_CLEAR mitigation: NO - * Kernel mitigation is enabled and active: NO - * SMT is either mitigated or disabled: NO - > STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not vulnerable) - - CVE-2018-12130 aka ZombieLoad, microarchitectural fill buffer data sampling (MFBDS) - * Mitigated according to the /sys interface: YES (Not affected) - * Kernel supports using MD_CLEAR mitigation: NO - * Kernel mitigation is enabled and active: NO - * SMT is either mitigated or disabled: NO - > STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not vulnerable) - - CVE-2018-12127 aka RIDL, microarchitectural load port data sampling (MLPDS) - * Mitigated according to the /sys interface: YES (Not affected) - * Kernel supports using MD_CLEAR mitigation: NO - * Kernel mitigation is enabled and active: NO - * SMT is either mitigated or disabled: NO - > STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not vulnerable) - - CVE-2019-11091 aka RIDL, microarchitectural data sampling uncacheable memory (MDSUM) - * Mitigated according to the /sys interface: YES (Not affected) - * Kernel supports using MD_CLEAR mitigation: NO - * Kernel mitigation is enabled and active: NO - * SMT is either mitigated or disabled: NO - > STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not vulnerable) - - CVE-2019-11135 aka ZombieLoad V2, TSX Asynchronous Abort (TAA) - * Mitigated according to the /sys interface: YES (Not affected) - * TAA mitigation is supported by kernel: YES (found tsx_async_abort in kernel image) - * TAA mitigation enabled and active: NO - > STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not vulnerable) - - CVE-2018-12207 aka No eXcuses, iTLB Multihit, machine check exception on page size changes (MCEPSC) - * Mitigated according to the /sys interface: YES (Not affected) - * This system is a host running a hypervisor: NO - * iTLB Multihit mitigation is supported by kernel: YES (found itlb_multihit in kernel image) - * iTLB Multihit mitigation enabled and active: NO - > STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not vulnerable) - - CVE-2020-0543 aka Special Register Buffer Data Sampling (SRBDS) - * Mitigated according to the /sys interface: YES (Not affected) - * SRBDS mitigation control is supported by the kernel: NO - * SRBDS mitigation control is enabled and active: NO - > STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not vulnerable) - - > SUMMARY: CVE-2017-5753:OK CVE-2017-5715:OK CVE-2017-5754:OK CVE-2018-3640:KO CVE-2018-3639:KO CVE-2018-3615:OK CVE-2018-3620:OK CVE-2018-3646:OK CVE-2018-12126:OK CVE-2018-12130:OK CVE-2018-12127:OK CVE-2019-11091:OK CVE-2019-11135:OK CVE-2018-12207:OK CVE-2020-0543:OK diff --git a/docs/report/introduction/test_environment_sut_meltspec_zn2.rst b/docs/report/introduction/test_environment_sut_meltspec_zn2.rst deleted file mode 100644 index 8269ce7f92..0000000000 --- a/docs/report/introduction/test_environment_sut_meltspec_zn2.rst +++ /dev/null @@ -1,327 +0,0 @@ -Spectre and Meltdown Checks -^^^^^^^^^^^^^^^^^^^^^^^^^^^ - -Following section displays the output of a running shell script to tell if -system is vulnerable against the several speculative execution CVEs that were -made public in 2018. Script is available on `Spectre & Meltdown Checker Github -<https://github.com/speed47/spectre-meltdown-checker>`_. - -:: - - Spectre and Meltdown mitigation detection tool v0.44+ - - Checking for vulnerabilities on current system - Kernel is Linux 5.4.0-65-generic #73-Ubuntu SMP Mon Jan 18 17:25:17 UTC 2021 x86_64 - CPU is AMD EPYC 7532 32-Core Processor - - Hardware check - * Hardware support (CPU microcode) for mitigation techniques - * Indirect Branch Restricted Speculation (IBRS) - * SPEC_CTRL MSR is available: YES - * CPU indicates IBRS capability: YES (IBRS_SUPPORT feature bit) - * CPU indicates preferring IBRS always-on: NO - * CPU indicates preferring IBRS over retpoline: YES - * Indirect Branch Prediction Barrier (IBPB) - * PRED_CMD MSR is available: YES - * CPU indicates IBPB capability: YES (IBPB_SUPPORT feature bit) - * Single Thread Indirect Branch Predictors (STIBP) - * SPEC_CTRL MSR is available: YES - * CPU indicates STIBP capability: YES (AMD STIBP feature bit) - * CPU indicates preferring STIBP always-on: NO - * Speculative Store Bypass Disable (SSBD) - * CPU indicates SSBD capability: YES (AMD SSBD in SPEC_CTRL) - * L1 data cache invalidation - * FLUSH_CMD MSR is available: NO - * CPU indicates L1D flush capability: NO - * CPU supports Transactional Synchronization Extensions (TSX): NO - * CPU supports Software Guard Extensions (SGX): NO - * CPU supports Special Register Buffer Data Sampling (SRBDS): NO - * CPU microcode is known to cause stability problems: NO (family 0x17 model 0x31 stepping 0x0 ucode 0x8301038 cpuid 0x830f10) - * CPU microcode is the latest known available version: NO (latest version is 0x830104d dated 2020/07/28 according to builtin firmwares DB v191+i20210217) - * CPU vulnerability to the speculative execution attack variants - * Affected by CVE-2017-5753 (Spectre Variant 1, bounds check bypass): YES - * Affected by CVE-2017-5715 (Spectre Variant 2, branch target injection): YES - * Affected by CVE-2017-5754 (Variant 3, Meltdown, rogue data cache load): NO - * Affected by CVE-2018-3640 (Variant 3a, rogue system register read): NO - * Affected by CVE-2018-3639 (Variant 4, speculative store bypass): YES - * Affected by CVE-2018-3615 (Foreshadow (SGX), L1 terminal fault): NO - * Affected by CVE-2018-3620 (Foreshadow-NG (OS), L1 terminal fault): NO - * Affected by CVE-2018-3646 (Foreshadow-NG (VMM), L1 terminal fault): NO - * Affected by CVE-2018-12126 (Fallout, microarchitectural store buffer data sampling (MSBDS)): NO - * Affected by CVE-2018-12130 (ZombieLoad, microarchitectural fill buffer data sampling (MFBDS)): NO - * Affected by CVE-2018-12127 (RIDL, microarchitectural load port data sampling (MLPDS)): NO - * Affected by CVE-2019-11091 (RIDL, microarchitectural data sampling uncacheable memory (MDSUM)): NO - * Affected by CVE-2019-11135 (ZombieLoad V2, TSX Asynchronous Abort (TAA)): NO - * Affected by CVE-2018-12207 (No eXcuses, iTLB Multihit, machine check exception on page size changes (MCEPSC)): NO - * Affected by CVE-2020-0543 (Special Register Buffer Data Sampling (SRBDS)): NO - - CVE-2017-5753 aka Spectre Variant 1, bounds check bypass - * Mitigated according to the /sys interface: YES (Mitigation: usercopy/swapgs barriers and __user pointer sanitization) - * Kernel has array_index_mask_nospec: YES (1 occurrence(s) found of x86 64 bits array_index_mask_nospec()) - * Kernel has the Red Hat/Ubuntu patch: NO - * Kernel has mask_nospec64 (arm64): NO - * Kernel has array_index_nospec (arm64): NO - > STATUS: NOT VULNERABLE (Mitigation: usercopy/swapgs barriers and __user pointer sanitization) - - CVE-2017-5715 aka Spectre Variant 2, branch target injection - * Mitigated according to the /sys interface: YES (Mitigation: Full AMD retpoline, IBPB: conditional, IBRS_FW, STIBP: conditional, RSB filling) - * Mitigation 1 - * Kernel is compiled with IBRS support: YES - * IBRS enabled and active: YES (for firmware code only) - * Kernel is compiled with IBPB support: YES - * IBPB enabled and active: YES - * Mitigation 2 - * Kernel has branch predictor hardening (arm): NO - * Kernel compiled with retpoline option: YES - * Kernel compiled with a retpoline-aware compiler: YES (kernel reports full retpoline compilation) - > STATUS: NOT VULNERABLE (Full retpoline + IBPB are mitigating the vulnerability) - - CVE-2017-5754 aka Variant 3, Meltdown, rogue data cache load - * Mitigated according to the /sys interface: YES (Not affected) - * Kernel supports Page Table Isolation (PTI): YES - * PTI enabled and active: NO - * Reduced performance impact of PTI: NO (PCID/INVPCID not supported, performance impact of PTI will be significant) - * Running as a Xen PV DomU: NO - > STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not vulnerable) - - CVE-2018-3640 aka Variant 3a, rogue system register read - * CPU microcode mitigates the vulnerability: YES - > STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not vulnerable) - - CVE-2018-3639 aka Variant 4, speculative store bypass - * Mitigated according to the /sys interface: YES (Mitigation: Speculative Store Bypass disabled via prctl and seccomp) - * Kernel supports disabling speculative store bypass (SSB): YES (found in /proc/self/status) - * SSB mitigation is enabled and active: YES (per-thread through prctl) - * SSB mitigation currently active for selected processes: YES (irqbalance systemd-journald systemd-logind systemd-networkd systemd-resolved systemd-timesyncd systemd-udevd) - > STATUS: NOT VULNERABLE (Mitigation: Speculative Store Bypass disabled via prctl and seccomp) - - CVE-2018-3615 aka Foreshadow (SGX), L1 terminal fault - * CPU microcode mitigates the vulnerability: N/A - > STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not vulnerable) - - CVE-2018-3620 aka Foreshadow-NG (OS), L1 terminal fault - * Mitigated according to the /sys interface: YES (Not affected) - * Kernel supports PTE inversion: YES (found in kernel image) - * PTE inversion enabled and active: NO - > STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not vulnerable) - - CVE-2018-3646 aka Foreshadow-NG (VMM), L1 terminal fault - * Information from the /sys interface: Not affected - * This system is a host running a hypervisor: NO - * Mitigation 1 (KVM) - * EPT is disabled: N/A (the kvm_intel module is not loaded) - * Mitigation 2 - * L1D flush is supported by kernel: YES (found flush_l1d in kernel image) - * L1D flush enabled: NO - * Hardware-backed L1D flush supported: NO (flush will be done in software, this is slower) - * Hyper-Threading (SMT) is enabled: YES - > STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not vulnerable) - - CVE-2018-12126 aka Fallout, microarchitectural store buffer data sampling (MSBDS) - * Mitigated according to the /sys interface: YES (Not affected) - * Kernel supports using MD_CLEAR mitigation: YES (found md_clear implementation evidence in kernel image) - * Kernel mitigation is enabled and active: NO - * SMT is either mitigated or disabled: NO - > STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not vulnerable) - - CVE-2018-12130 aka ZombieLoad, microarchitectural fill buffer data sampling (MFBDS) - * Mitigated according to the /sys interface: YES (Not affected) - * Kernel supports using MD_CLEAR mitigation: YES (found md_clear implementation evidence in kernel image) - * Kernel mitigation is enabled and active: NO - * SMT is either mitigated or disabled: NO - > STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not vulnerable) - - CVE-2018-12127 aka RIDL, microarchitectural load port data sampling (MLPDS) - * Mitigated according to the /sys interface: YES (Not affected) - * Kernel supports using MD_CLEAR mitigation: YES (found md_clear implementation evidence in kernel image) - * Kernel mitigation is enabled and active: NO - * SMT is either mitigated or disabled: NO - > STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not vulnerable) - - CVE-2019-11091 aka RIDL, microarchitectural data sampling uncacheable memory (MDSUM) - * Mitigated according to the /sys interface: YES (Not affected) - * Kernel supports using MD_CLEAR mitigation: YES (found md_clear implementation evidence in kernel image) - * Kernel mitigation is enabled and active: NO - * SMT is either mitigated or disabled: NO - > STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not vulnerable) - - CVE-2019-11135 aka ZombieLoad V2, TSX Asynchronous Abort (TAA) - * Mitigated according to the /sys interface: YES (Not affected) - * TAA mitigation is supported by kernel: YES (found tsx_async_abort in kernel image) - * TAA mitigation enabled and active: NO - > STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not vulnerable) - - CVE-2018-12207 aka No eXcuses, iTLB Multihit, machine check exception on page size changes (MCEPSC) - * Mitigated according to the /sys interface: YES (Not affected) - * This system is a host running a hypervisor: NO - * iTLB Multihit mitigation is supported by kernel: YES (found itlb_multihit in kernel image) - * iTLB Multihit mitigation enabled and active: NO - > STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not vulnerable) - - CVE-2020-0543 aka Special Register Buffer Data Sampling (SRBDS) - * Mitigated according to the /sys interface: YES (Not affected) - * SRBDS mitigation control is supported by the kernel: YES (found SRBDS implementation evidence in kernel image. Your kernel is up to date for SRBDS mitigation) - * SRBDS mitigation control is enabled and active: NO - > STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not vulnerable) - - > SUMMARY: CVE-2017-5753:OK CVE-2017-5715:OK CVE-2017-5754:OK CVE-2018-3640:OK CVE-2018-3639:OK CVE-2018-3615:OK CVE-2018-3620:OK CVE-2018-3646:OK CVE-2018-12126:OK CVE-2018-12130:OK CVE-2018-12127:OK CVE-2019-11091:OK CVE-2019-11135:OK CVE-2018-12207:OK CVE-2020-0543:OK - -:: - -Spectre and Meltdown mitigation detection tool v0.44+ - -Checking for vulnerabilities on current system -Kernel is Linux 5.4.0-65-generic #73-Ubuntu SMP Mon Jan 18 17:25:17 UTC 2021 x86_64 -CPU is AMD EPYC 7532 32-Core Processor - -Hardware check -* Hardware support (CPU microcode) for mitigation techniques - * Indirect Branch Restricted Speculation (IBRS) - * SPEC_CTRL MSR is available: YES - * CPU indicates IBRS capability: YES (IBRS_SUPPORT feature bit) - * CPU indicates preferring IBRS always-on: NO - * CPU indicates preferring IBRS over retpoline: YES - * Indirect Branch Prediction Barrier (IBPB) - * PRED_CMD MSR is available: YES - * CPU indicates IBPB capability: YES (IBPB_SUPPORT feature bit) - * Single Thread Indirect Branch Predictors (STIBP) - * SPEC_CTRL MSR is available: YES - * CPU indicates STIBP capability: YES (AMD STIBP feature bit) - * CPU indicates preferring STIBP always-on: NO - * Speculative Store Bypass Disable (SSBD) - * CPU indicates SSBD capability: YES (AMD SSBD in SPEC_CTRL) - * L1 data cache invalidation - * FLUSH_CMD MSR is available: NO - * CPU indicates L1D flush capability: NO - * CPU supports Transactional Synchronization Extensions (TSX): NO - * CPU supports Software Guard Extensions (SGX): NO - * CPU supports Special Register Buffer Data Sampling (SRBDS): NO - * CPU microcode is known to cause stability problems: NO (family 0x17 model 0x31 stepping 0x0 ucode 0x8301038 cpuid 0x830f10) - * CPU microcode is the latest known available version: NO (latest version is 0x830104d dated 2020/07/28 according to builtin firmwares DB v191+i20210217) -* CPU vulnerability to the speculative execution attack variants - * Affected by CVE-2017-5753 (Spectre Variant 1, bounds check bypass): YES - * Affected by CVE-2017-5715 (Spectre Variant 2, branch target injection): YES - * Affected by CVE-2017-5754 (Variant 3, Meltdown, rogue data cache load): NO - * Affected by CVE-2018-3640 (Variant 3a, rogue system register read): NO - * Affected by CVE-2018-3639 (Variant 4, speculative store bypass): YES - * Affected by CVE-2018-3615 (Foreshadow (SGX), L1 terminal fault): NO - * Affected by CVE-2018-3620 (Foreshadow-NG (OS), L1 terminal fault): NO - * Affected by CVE-2018-3646 (Foreshadow-NG (VMM), L1 terminal fault): NO - * Affected by CVE-2018-12126 (Fallout, microarchitectural store buffer data sampling (MSBDS)): NO - * Affected by CVE-2018-12130 (ZombieLoad, microarchitectural fill buffer data sampling (MFBDS)): NO - * Affected by CVE-2018-12127 (RIDL, microarchitectural load port data sampling (MLPDS)): NO - * Affected by CVE-2019-11091 (RIDL, microarchitectural data sampling uncacheable memory (MDSUM)): NO - * Affected by CVE-2019-11135 (ZombieLoad V2, TSX Asynchronous Abort (TAA)): NO - * Affected by CVE-2018-12207 (No eXcuses, iTLB Multihit, machine check exception on page size changes (MCEPSC)): NO - * Affected by CVE-2020-0543 (Special Register Buffer Data Sampling (SRBDS)): NO - -CVE-2017-5753 aka Spectre Variant 1, bounds check bypass -* Mitigated according to the /sys interface: YES (Mitigation: usercopy/swapgs barriers and __user pointer sanitization) -* Kernel has array_index_mask_nospec: YES (1 occurrence(s) found of x86 64 bits array_index_mask_nospec()) -* Kernel has the Red Hat/Ubuntu patch: NO -* Kernel has mask_nospec64 (arm64): NO -* Kernel has array_index_nospec (arm64): NO -> STATUS: NOT VULNERABLE (Mitigation: usercopy/swapgs barriers and __user pointer sanitization) - -CVE-2017-5715 aka Spectre Variant 2, branch target injection -* Mitigated according to the /sys interface: YES (Mitigation: Full AMD retpoline, IBPB: conditional, IBRS_FW, STIBP: conditional, RSB filling) -* Mitigation 1 - * Kernel is compiled with IBRS support: YES - * IBRS enabled and active: YES (for firmware code only) - * Kernel is compiled with IBPB support: YES - * IBPB enabled and active: YES -* Mitigation 2 - * Kernel has branch predictor hardening (arm): NO - * Kernel compiled with retpoline option: YES - * Kernel compiled with a retpoline-aware compiler: YES (kernel reports full retpoline compilation) -> STATUS: NOT VULNERABLE (Full retpoline + IBPB are mitigating the vulnerability) - -CVE-2017-5754 aka Variant 3, Meltdown, rogue data cache load -* Mitigated according to the /sys interface: YES (Not affected) -* Kernel supports Page Table Isolation (PTI): YES - * PTI enabled and active: UNKNOWN (dmesg truncated, please reboot and relaunch this script) - * Reduced performance impact of PTI: NO (PCID/INVPCID not supported, performance impact of PTI will be significant) -* Running as a Xen PV DomU: NO -> STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not vulnerable) - -CVE-2018-3640 aka Variant 3a, rogue system register read -* CPU microcode mitigates the vulnerability: YES -> STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not vulnerable) - -CVE-2018-3639 aka Variant 4, speculative store bypass -* Mitigated according to the /sys interface: YES (Mitigation: Speculative Store Bypass disabled via prctl and seccomp) -* Kernel supports disabling speculative store bypass (SSB): YES (found in /proc/self/status) -* SSB mitigation is enabled and active: YES (per-thread through prctl) -* SSB mitigation currently active for selected processes: YES (irqbalance systemd-journald systemd-logind systemd-networkd systemd-resolved systemd-timesyncd systemd-udevd) -> STATUS: NOT VULNERABLE (Mitigation: Speculative Store Bypass disabled via prctl and seccomp) - -CVE-2018-3615 aka Foreshadow (SGX), L1 terminal fault -* CPU microcode mitigates the vulnerability: N/A -> STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not vulnerable) - -CVE-2018-3620 aka Foreshadow-NG (OS), L1 terminal fault -* Mitigated according to the /sys interface: YES (Not affected) -* Kernel supports PTE inversion: YES (found in kernel image) -* PTE inversion enabled and active: NO -> STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not vulnerable) - -CVE-2018-3646 aka Foreshadow-NG (VMM), L1 terminal fault -* Information from the /sys interface: Not affected -* This system is a host running a hypervisor: NO -* Mitigation 1 (KVM) - * EPT is disabled: N/A (the kvm_intel module is not loaded) -* Mitigation 2 - * L1D flush is supported by kernel: YES (found flush_l1d in kernel image) - * L1D flush enabled: NO - * Hardware-backed L1D flush supported: NO (flush will be done in software, this is slower) - * Hyper-Threading (SMT) is enabled: YES -> STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not vulnerable) - -CVE-2018-12126 aka Fallout, microarchitectural store buffer data sampling (MSBDS) -* Mitigated according to the /sys interface: YES (Not affected) -* Kernel supports using MD_CLEAR mitigation: YES (found md_clear implementation evidence in kernel image) -* Kernel mitigation is enabled and active: NO -* SMT is either mitigated or disabled: NO -> STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not vulnerable) - -CVE-2018-12130 aka ZombieLoad, microarchitectural fill buffer data sampling (MFBDS) -* Mitigated according to the /sys interface: YES (Not affected) -* Kernel supports using MD_CLEAR mitigation: YES (found md_clear implementation evidence in kernel image) -* Kernel mitigation is enabled and active: NO -* SMT is either mitigated or disabled: NO -> STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not vulnerable) - -CVE-2018-12127 aka RIDL, microarchitectural load port data sampling (MLPDS) -* Mitigated according to the /sys interface: YES (Not affected) -* Kernel supports using MD_CLEAR mitigation: YES (found md_clear implementation evidence in kernel image) -* Kernel mitigation is enabled and active: NO -* SMT is either mitigated or disabled: NO -> STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not vulnerable) - -CVE-2019-11091 aka RIDL, microarchitectural data sampling uncacheable memory (MDSUM) -* Mitigated according to the /sys interface: YES (Not affected) -* Kernel supports using MD_CLEAR mitigation: YES (found md_clear implementation evidence in kernel image) -* Kernel mitigation is enabled and active: NO -* SMT is either mitigated or disabled: NO -> STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not vulnerable) - -CVE-2019-11135 aka ZombieLoad V2, TSX Asynchronous Abort (TAA) -* Mitigated according to the /sys interface: YES (Not affected) -* TAA mitigation is supported by kernel: YES (found tsx_async_abort in kernel image) -* TAA mitigation enabled and active: NO -> STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not vulnerable) - -CVE-2018-12207 aka No eXcuses, iTLB Multihit, machine check exception on page size changes (MCEPSC) -* Mitigated according to the /sys interface: YES (Not affected) -* This system is a host running a hypervisor: NO -* iTLB Multihit mitigation is supported by kernel: YES (found itlb_multihit in kernel image) -* iTLB Multihit mitigation enabled and active: NO -> STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not vulnerable) - -CVE-2020-0543 aka Special Register Buffer Data Sampling (SRBDS) -* Mitigated according to the /sys interface: YES (Not affected) -* SRBDS mitigation control is supported by the kernel: YES (found SRBDS implementation evidence in kernel image. Your kernel is up to date for SRBDS mitigation) -* SRBDS mitigation control is enabled and active: NO -> STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not vulnerable) - -> SUMMARY: CVE-2017-5753:OK CVE-2017-5715:OK CVE-2017-5754:OK CVE-2018-3640:OK CVE-2018-3639:OK CVE-2018-3615:OK CVE-2018-3620:OK CVE-2018-3646:OK CVE-2018-12126:OK CVE-2018-12130:OK CVE-2018-12127:OK CVE-2019-11091:OK CVE-2019-11135:OK CVE-2018-12207:OK CVE-2020-0543:OK diff --git a/docs/report/introduction/test_scenarios_overview.rst b/docs/report/introduction/test_scenarios_overview.rst index c102f76cde..304a00e74e 100644 --- a/docs/report/introduction/test_scenarios_overview.rst +++ b/docs/report/introduction/test_scenarios_overview.rst @@ -11,9 +11,7 @@ Brief overview of test scenarios covered in this report: #. **VPP Performance**: VPP performance tests are executed in physical FD.io testbeds, focusing on VPP network data plane performance in - NIC-to-NIC switching topologies. Tested across Intel Cascadelake - and Skylake servers, ARM, Denverton, range of NICs (10GE, 25GE, 40GE, 100GE) - and multi-thread/multi-core configurations. VPP application runs in + NIC-to-NIC switching topologies. VPP application runs in bare-metal host user-mode handling NICs. TRex is used as a traffic generator. #. **VPP Vhostuser Performance with KVM VMs**: VPP VM service switching @@ -44,8 +42,7 @@ Brief overview of test scenarios covered in this report: #. **T-Rex Performance**: T-Rex perfomance tests are executed in physical FD.io testbeds, focusing on T-Rex data plane performance in NIC-to-NIC - loopback topologies. Tested across Intel Skylake servers, range of NICs - (10GE) and selected traffic profiles. TRex is used as a traffic generator. + loopback topologies. #. **VPP Functional**: VPP functional tests are executed in virtual FD.io testbeds, focusing on VPP packet processing functionality, diff --git a/docs/report/introduction/testbed-2n-skx.svg b/docs/report/introduction/testbed-2n-skx.svg deleted file mode 100644 index 5f22ae1fb3..0000000000 --- a/docs/report/introduction/testbed-2n-skx.svg +++ /dev/null @@ -1,1858 +0,0 @@ -<?xml version="1.0" encoding="UTF-8"?> -<!DOCTYPE svg PUBLIC "-//W3C//DTD SVG 1.1//EN" "http://www.w3.org/Graphics/SVG/1.1/DTD/svg11.dtd"> -<svg version="1.2" width="90.84mm" height="128.96mm" viewBox="501 1325 9084 12896" preserveAspectRatio="xMidYMid" fill-rule="evenodd" stroke-width="28.222" stroke-linejoin="round" xmlns="http://www.w3.org/2000/svg" xmlns:ooo="http://xml.openoffice.org/svg/export" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:presentation="http://sun.com/xmlns/staroffice/presentation" xmlns:smil="http://www.w3.org/2001/SMIL20/" xmlns:anim="urn:oasis:names:tc:opendocument:xmlns:animation:1.0" xml:space="preserve"> - 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\ No newline at end of file diff --git a/docs/report/stats/durations.rst b/docs/report/stats/durations.rst deleted file mode 100644 index b493ef034a..0000000000 --- a/docs/report/stats/durations.rst +++ /dev/null @@ -1,56 +0,0 @@ -Job Durations -============= - -2n-icx ------- - - - `ASCII Iterative jobs <../_static/vpp/job-spec-duration-2n-icx-iter.txt>`_ - - `ASCII Coverage jobs <../_static/vpp/job-spec-duration-2n-icx-cov.txt>`_ - -3n-icx ------- - - - `ASCII Iterative jobs <../_static/vpp/job-spec-duration-3n-icx-iter.txt>`_ - - `ASCII Coverage jobs <../_static/vpp/job-spec-duration-3n-icx-cov.txt>`_ - -2n-clx ------- - - - `ASCII Iterative jobs <../_static/vpp/job-spec-duration-2n-clx-iter.txt>`_ - - `ASCII Coverage jobs <../_static/vpp/job-spec-duration-2n-clx-cov.txt>`_ - -2n-dnv ------- - - - `ASCII Iterative jobs <../_static/vpp/job-spec-duration-2n-dnv-iter.txt>`_ - - `ASCII Coverage jobs <../_static/vpp/job-spec-duration-2n-dnv-cov.txt>`_ - -2n-tx2 ------- - - - `ASCII Iterative jobs <../_static/vpp/job-spec-duration-2n-tx2-iter.txt>`_ - - `ASCII Coverage jobs <../_static/vpp/job-spec-duration-2n-tx2-cov.txt>`_ - -2n-zn2 ------- - - - `ASCII Iterative jobs <../_static/vpp/job-spec-duration-2n-zn2-iter.txt>`_ - - `ASCII Coverage jobs <../_static/vpp/job-spec-duration-2n-zn2-cov.txt>`_ - -3n-alt ------- - - - `ASCII Iterative jobs <../_static/vpp/job-spec-duration-3n-alt-iter.txt>`_ - - `ASCII Coverage jobs <../_static/vpp/job-spec-duration-3n-alt-cov.txt>`_ - -3n-dnv ------- - - - `ASCII Iterative jobs <../_static/vpp/job-spec-duration-3n-dnv-iter.txt>`_ - - `ASCII Coverage jobs <../_static/vpp/job-spec-duration-3n-dnv-cov.txt>`_ - -3n-tsh ------- - - - `ASCII Iterative jobs <../_static/vpp/job-spec-duration-3n-tsh-iter.txt>`_ - - `ASCII Coverage jobs <../_static/vpp/job-spec-duration-3n-tsh-cov.txt>`_ diff --git a/docs/report/trex_performance_tests/overview.rst b/docs/report/trex_performance_tests/overview.rst index 8ad8850ea8..5ad340744e 100644 --- a/docs/report/trex_performance_tests/overview.rst +++ b/docs/report/trex_performance_tests/overview.rst @@ -76,7 +76,7 @@ Performance Tests Naming ------------------------ FD.io |csit-release| follows a common structured naming convention for -all performance and system functional tests, introduced in CSIT-17.01. +all performance and system functional tests. The naming should be intuitive for majority of the tests. Complete description of FD.io CSIT test naming convention is provided on diff --git a/docs/report/trex_performance_tests/test_environment.rst b/docs/report/trex_performance_tests/test_environment.rst index 06b6d733a5..faf2db6d20 100644 --- a/docs/report/trex_performance_tests/test_environment.rst +++ b/docs/report/trex_performance_tests/test_environment.rst @@ -2,12 +2,12 @@ \clearpage -.. include:: ../introduction/test_environment_intro.rst +.. include:: ../introduction/environment/intro.rst -.. include:: ../introduction/test_environment_changes_tg.rst +.. include:: ../introduction/environment/changes_tg.rst SUT Settings - TRex ------------------- -.. include:: ../introduction/test_environment_tg.rst +.. include:: ../introduction/environment/tg.rst diff --git a/docs/report/vpp_device_tests/overview.rst b/docs/report/vpp_device_tests/overview.rst index a596ae97ff..ba63b4b277 100644 --- a/docs/report/vpp_device_tests/overview.rst +++ b/docs/report/vpp_device_tests/overview.rst @@ -166,7 +166,7 @@ Tests Naming ------------ |csit-release| follows a common structured naming convention for all -performance and system functional tests, introduced in CSIT-17.01. +performance and system functional tests. The naming should be intuitive for majority of the tests. Complete description of CSIT test naming convention is provided on diff --git a/docs/report/vpp_device_tests/test_environment.rst b/docs/report/vpp_device_tests/test_environment.rst index 2fe4adb439..33915da83b 100644 --- a/docs/report/vpp_device_tests/test_environment.rst +++ b/docs/report/vpp_device_tests/test_environment.rst @@ -98,9 +98,6 @@ NIC interfaces are shared using Linux vfio_pci and VPP VF drivers: Provided Intel x710-da4 4p10GE NICs support 32 VFs per interface, 128 per NIC. -Complete 1n-skx testbeds specification is available on `CSIT LF Testbeds -<https://wiki.fd.io/view/CSIT/Testbeds:_Xeon_Skx,_Arm,_Atom.>`_ wiki page. - Total of two 1n-skx testbeds are in operation in FD.io labs. 1-Node Virtualbox (1n-vbox) diff --git a/docs/report/vpp_performance_tests/comparisons/nic_comparison.rst b/docs/report/vpp_performance_tests/comparisons/nic_comparison.rst index 9186ec556a..15091fca77 100644 --- a/docs/report/vpp_performance_tests/comparisons/nic_comparison.rst +++ b/docs/report/vpp_performance_tests/comparisons/nic_comparison.rst @@ -5,7 +5,7 @@ NICs Comparison --------------- Relative comparison of VPP packet throughput (NDR, PDR and MRR) between -NICs (measured for |csit-release) is calculated from results of tests +NICs (measured for |csit-release|) is calculated from results of tests running on 3n-skx, 2n-skx testbeds. Listed mean and standard deviation values are computed based on a series diff --git a/docs/report/vpp_performance_tests/gso_testing/2n-clx.rst b/docs/report/vpp_performance_tests/gso_testing/2n-clx.rst index a3e8b8cef9..8afc3df52c 100644 --- a/docs/report/vpp_performance_tests/gso_testing/2n-clx.rst +++ b/docs/report/vpp_performance_tests/gso_testing/2n-clx.rst @@ -31,9 +31,6 @@ 2n-clx ~~~~~~ -.. todo:: - Add introduction - .. raw:: latex \clearpage diff --git a/docs/report/vpp_performance_tests/gso_testing/2n-icx.rst b/docs/report/vpp_performance_tests/gso_testing/2n-icx.rst index e2f6823d54..a8a94f4bb2 100644 --- a/docs/report/vpp_performance_tests/gso_testing/2n-icx.rst +++ b/docs/report/vpp_performance_tests/gso_testing/2n-icx.rst @@ -31,9 +31,6 @@ 2n-icx ~~~~~~ -.. todo:: - Add introduction - .. raw:: latex \clearpage diff --git a/docs/report/vpp_performance_tests/gso_testing/2n-zn2.rst b/docs/report/vpp_performance_tests/gso_testing/2n-zn2.rst index ab771cb460..dddd3d81b5 100644 --- a/docs/report/vpp_performance_tests/gso_testing/2n-zn2.rst +++ b/docs/report/vpp_performance_tests/gso_testing/2n-zn2.rst @@ -31,9 +31,6 @@ 2n-zn2 ~~~~~~ -.. todo:: - Add introduction - .. raw:: latex \clearpage diff --git a/docs/report/vpp_performance_tests/hoststack_testing/iperf3/tcp/index.rst b/docs/report/vpp_performance_tests/hoststack_testing/iperf3/tcp/index.rst index b86cbeb516..da57000dec 100644 --- a/docs/report/vpp_performance_tests/hoststack_testing/iperf3/tcp/index.rst +++ b/docs/report/vpp_performance_tests/hoststack_testing/iperf3/tcp/index.rst @@ -30,9 +30,6 @@ TCP/IP with iperf3 ~~~~~~~~~~~~~~~~~~ -.. todo:: - Add introduction - .. raw:: latex \clearpage diff --git a/docs/report/vpp_performance_tests/hoststack_testing/iperf3/udp/index.rst b/docs/report/vpp_performance_tests/hoststack_testing/iperf3/udp/index.rst index 3c89c32aed..7c6db0f85c 100644 --- a/docs/report/vpp_performance_tests/hoststack_testing/iperf3/udp/index.rst +++ b/docs/report/vpp_performance_tests/hoststack_testing/iperf3/udp/index.rst @@ -30,9 +30,6 @@ UDP/IP with iperf3 ~~~~~~~~~~~~~~~~~~ -.. todo:: - Add introduction - .. raw:: latex \clearpage diff --git a/docs/report/vpp_performance_tests/hoststack_testing/quic/index.rst b/docs/report/vpp_performance_tests/hoststack_testing/quic/index.rst index 124911e8bc..716d8291f7 100644 --- a/docs/report/vpp_performance_tests/hoststack_testing/quic/index.rst +++ b/docs/report/vpp_performance_tests/hoststack_testing/quic/index.rst @@ -31,9 +31,6 @@ QUIC/UDP/IP with vpp_echo ~~~~~~~~~~~~~~~~~~~~~~~~~ -.. todo:: - Add introduction - .. raw:: latex \clearpage diff --git a/docs/report/vpp_performance_tests/nf_service_density/vnf_service_chains_vxlan.rst b/docs/report/vpp_performance_tests/nf_service_density/vnf_service_chains_vxlan.rst index 52f6116847..bfa32dd1b8 100644 --- a/docs/report/vpp_performance_tests/nf_service_density/vnf_service_chains_vxlan.rst +++ b/docs/report/vpp_performance_tests/nf_service_density/vnf_service_chains_vxlan.rst @@ -33,10 +33,6 @@ VNF Service Chains Tunnels ========================== -.. todo:: - - Add introduction. - Additional information about graph data: #. **Graph Title**: describes tested packet path including VNF workload diff --git a/docs/report/vpp_performance_tests/overview.rst b/docs/report/vpp_performance_tests/overview.rst index 9647edeabd..bb2ff6cdf1 100644 --- a/docs/report/vpp_performance_tests/overview.rst +++ b/docs/report/vpp_performance_tests/overview.rst @@ -269,10 +269,6 @@ topologies and configurations: size is set to the bi-directional link rate, unless there is a known limitation preventing Traffic Generator from achieving the line rate. -.. todo:: - - - Connections per second (CPS): TODO - |csit-release| includes following VPP data plane functionality performance tested across a range of NIC drivers and NIC models: @@ -371,7 +367,7 @@ Performance Tests Naming ------------------------ FD.io |csit-release| follows a common structured naming convention for -all performance and system functional tests, introduced in CSIT-17.01. +all performance and system functional tests. The naming should be intuitive for majority of the tests. Complete description of FD.io CSIT test naming convention is provided on diff --git a/docs/report/vpp_performance_tests/test_environment.rst b/docs/report/vpp_performance_tests/test_environment.rst index dec8780904..b71f83d9e6 100644 --- a/docs/report/vpp_performance_tests/test_environment.rst +++ b/docs/report/vpp_performance_tests/test_environment.rst @@ -5,11 +5,11 @@ .. _vpp_test_environment: -.. include:: ../introduction/test_environment_intro.rst +.. include:: ../introduction/environment/intro.rst -.. include:: ../introduction/test_environment_changes_vpp.rst +.. include:: ../introduction/environment/changes_vpp.rst -.. include:: ../introduction/test_environment_sut_conf_1.rst +.. include:: ../introduction/environment/sut_conf_1.rst DUT Settings - VPP @@ -106,22 +106,30 @@ requirements. Default template is provided below: Description of VPP startup settings used in CSIT is provided in :ref:`test_methodology`. -.. include:: ../introduction/test_environment_tg.rst +.. include:: ../introduction/environment/tg.rst -.. include:: ../introduction/test_environment_pre_test_server_calib.rst +.. include:: ../introduction/environment/pre_test_server_calib.rst -.. include:: ../introduction/test_environment_sut_calib_icx.rst +.. include:: ../introduction/environment/sut_calib_icx.rst +.. include:: ../introduction/environment/sut_meltspec_icx.rst -.. include:: ../introduction/test_environment_sut_calib_skx.rst +.. include:: ../introduction/environment/sut_calib_clx.rst +.. include:: ../introduction/environment/sut_meltspec_clx.rst -.. include:: ../introduction/test_environment_sut_calib_clx.rst +.. include:: ../introduction/environment/sut_calib_zn2.rst +.. include:: ../introduction/environment/sut_meltspec_zn2.rst -.. include:: ../introduction/test_environment_sut_calib_hsw.rst +.. include:: ../introduction/environment/sut_calib_dnv.rst +.. include:: ../introduction/environment/sut_meltspec_dnv.rst -.. include:: ../introduction/test_environment_sut_calib_dnv.rst +.. include:: ../introduction/environment/sut_calib_snr.rst +.. include:: ../introduction/environment/sut_meltspec_snr.rst -.. include:: ../introduction/test_environment_sut_calib_alt.rst +.. include:: ../introduction/environment/sut_calib_alt.rst +.. include:: ../introduction/environment/sut_meltspec_alt.rst -.. include:: ../introduction/test_environment_sut_calib_tsh.rst +.. include:: ../introduction/environment/sut_calib_tsh.rst +.. include:: ../introduction/environment/sut_meltspec_tsh.rst -.. include:: ../introduction/test_environment_sut_calib_tx2.rst +.. include:: ../introduction/environment/sut_calib_tx2.rst +.. include:: ../introduction/environment/sut_meltspec_tx2.rst diff --git a/resources/tools/presentation/sphinx_conf/report/conf.py b/resources/tools/presentation/sphinx_conf/report/conf.py index 1031ef000c..6ebf915d72 100644 --- a/resources/tools/presentation/sphinx_conf/report/conf.py +++ b/resources/tools/presentation/sphinx_conf/report/conf.py @@ -80,7 +80,10 @@ rst_epilog = """ .. _TRex driver: https://git.fd.io/csit/tree/GPL/tools/trex/trex_stl_profile.py?h={release} .. _CSIT Performance Tests Documentation: https://s3-docs.fd.io/csit/{release}/docs/index.html .. _VPP test framework documentation: https://docs.fd.io/vpp/{vpprelease}/vpp_make_test/html/ -.. _FD.io CSIT testbeds - Xeon Skylake, Arm, Atom: https://git.fd.io/csit/tree/docs/lab/testbeds_sm_skx_hw_bios_cfg.md?h={release} +.. _FD.io CSIT testbeds - Atom Snowridge: https://git.fd.io/csit/tree/docs/lab/testbeds_sm_snr_hw_bios_cfg.md?h={release} +.. _FD.io CSIT testbeds - Atom Denverton: https://git.fd.io/csit/tree/docs/lab/testbeds_sm_dnv_hw_bios_cfg.md?h={release} +.. _FD.io CSIT testbeds - EPYC Zen2: https://git.fd.io/csit/tree/docs/lab/testbeds_sm_zn2_hw_bios_cfg.md?h={release} +.. _FD.io CSIT testbeds - Xeon Ice Lake: https://git.fd.io/csit/tree/docs/lab/testbeds_sm_icx_hw_bios_cfg.md?h={release} .. _FD.io CSIT testbeds - Xeon Cascade Lake: https://git.fd.io/csit/tree/docs/lab/testbeds_sm_clx_hw_bios_cfg.md?h={release} .. _Ansible inventory - hosts: https://git.fd.io/csit/tree/fdio.infra.ansible/inventories/lf_inventory/host_vars?h={release} .. _build logs from FD.io trex performance job 2n-aws: https://s3-logs.fd.io/vex-yul-rot-jenkins-1/csit-trex-perf-report-iterative-{srelease}-2n-aws |
