diff options
12 files changed, 190 insertions, 11 deletions
diff --git a/docs/report/dpdk_performance_tests/csit_release_notes.rst b/docs/report/dpdk_performance_tests/csit_release_notes.rst index 9e16b6c53e..c6498a348f 100644 --- a/docs/report/dpdk_performance_tests/csit_release_notes.rst +++ b/docs/report/dpdk_performance_tests/csit_release_notes.rst @@ -9,6 +9,13 @@ Changes in |csit-release| - **CSIT test environment** version has been updated to ver. 8, see :ref:`test_environment_versioning`. +#. DPDK PERFORMANCE TESTS + + - **Arm Ampere Altra**: Performance test data for these platforms + is now provided by testbeds newly installed in FD.io CSIT labs. + For details about the physical setup see + :ref:`physical_testbeds_3n_alt`. + #. DPDK RELEASE VERSION CHANGE - |csit-release| tested |dpdk-release|, as used by |vpp-release|. diff --git a/docs/report/dpdk_performance_tests/packet_latency/index.rst b/docs/report/dpdk_performance_tests/packet_latency/index.rst index 3076d572cd..623111ada5 100644 --- a/docs/report/dpdk_performance_tests/packet_latency/index.rst +++ b/docs/report/dpdk_performance_tests/packet_latency/index.rst @@ -8,8 +8,8 @@ Packet Latency DPDK Testpmd and L3fwd latency results are generated based on the test data obtained from |csit-release| NDR-PDR throughput tests executed -across physical testbeds hosted in LF FD.io labs: 2n-icx, 3n-icx, 3n-skx, 2n- -skx, 2n-clx, 3n-dnv, 2n-dnv, 3n-tsh, 2n-tx2. +across physical testbeds hosted in LF FD.io labs: 2n-icx, 3n-icx, 2n-skx, +3n-skx, 2n-clx, 2n-zn2, 3n-alt, 3n-tsh, 2n-tx2. Latency by percentile distribution plots are used to show packet latency percentiles at different packet rate load levels: i) No-Load latency @@ -38,8 +38,8 @@ Additional information about graph data: `build logs from FD.io dpdk performance job 2n-icx`_, `build logs from FD.io dpdk performance job 3n-icx`_, `build logs from FD.io dpdk performance job 2n-skx`_, - `build logs from FD.io dpdk performance job 2n-clx`_, `build logs from FD.io dpdk performance job 3n-skx`_, + `build logs from FD.io dpdk performance job 2n-clx`_, `build logs from FD.io dpdk performance job 2n-zn2`_, `build logs from FD.io dpdk performance job 3n-alt`_, `build logs from FD.io dpdk performance job 3n-tsh`_ and diff --git a/docs/report/dpdk_performance_tests/packet_throughput_graphs/index.rst b/docs/report/dpdk_performance_tests/packet_throughput_graphs/index.rst index a5f3281ac0..653586a65d 100644 --- a/docs/report/dpdk_performance_tests/packet_throughput_graphs/index.rst +++ b/docs/report/dpdk_performance_tests/packet_throughput_graphs/index.rst @@ -8,7 +8,7 @@ Packet Throughput Throughput graphs are generated by multiple executions of the same performance tests across physical testbeds hosted LF FD.io labs: -2n-skx, 3n-skx, 2n-clx, 2n-tx2, 2n-zn2, 3n-tsh. +2n-icx, 3n-icx, 2n-skx, 3n-skx, 2n-clx, 2n-zn2, 3n-alt, 3n-tsh, 2n-tx2. Box-and-Whisker plots are used to display variations in measured throughput values, without making any assumptions of the underlying statistical distribution. diff --git a/docs/report/dpdk_performance_tests/test_environment.rst b/docs/report/dpdk_performance_tests/test_environment.rst index 194b28ed58..9f34685c48 100644 --- a/docs/report/dpdk_performance_tests/test_environment.rst +++ b/docs/report/dpdk_performance_tests/test_environment.rst @@ -59,6 +59,8 @@ Startup command template: .. include:: ../introduction/test_environment_sut_calib_dnv.rst +.. include:: ../introduction/test_environment_sut_calib_alt.rst + .. include:: ../introduction/test_environment_sut_calib_tsh.rst .. include:: ../introduction/test_environment_sut_calib_tx2.rst diff --git a/docs/report/introduction/physical_testbeds.rst b/docs/report/introduction/physical_testbeds.rst index cfd43d0653..30a4698f8b 100644 --- a/docs/report/introduction/physical_testbeds.rst +++ b/docs/report/introduction/physical_testbeds.rst @@ -402,6 +402,44 @@ TG NICs: #. NIC-1: x710-DA4 4p10GE Intel. +.. _physical_testbeds_3n_alt: + +3-Node ARM Altra (3n-alt) +--------------------------- + +One 3n-tsh testbed is built with: i) one SuperMicro SYS-740GP-TNRT +server acting as TG and equipped with two Intel Xeon Icelake Platinum +8358 processors (80 MB Cache, 2.60 GHz, 32 cores), and ii) one Ampere +Altra server acting as SUT and equipped with two Q80-30 processors +(80* ARM Neoverse N1). 3n-alt physical topology is shown below. + +.. only:: latex + + .. raw:: latex + + \begin{figure}[H] + \centering + \graphicspath{{../_tmp/src/introduction/}} + \includegraphics[width=0.90\textwidth]{testbed-3n-alt} + \label{fig:testbed-3n-alt} + \end{figure} + +.. only:: html + + .. figure:: testbed-3n-alt.svg + :alt: testbed-3n-alt + :align: center + +SUT1 and SUT2 NICs: + +#. NIC-1: xl710-QDA2-2p40GE Intel. + +TG NICs: + +#. NIC-1: xxv710-DA2-2p25GE Intel. +#. NIC-2: e810-XXVDA4-4p25GE Intel. +#. NIC-3: e810-2CQDA2-2p100GE Intel. + 3-Node ARM TaiShan (3n-tsh) --------------------------- diff --git a/docs/report/introduction/test_environment_sut_calib_alt.rst b/docs/report/introduction/test_environment_sut_calib_alt.rst new file mode 100644 index 0000000000..dae1d1bf14 --- /dev/null +++ b/docs/report/introduction/test_environment_sut_calib_alt.rst @@ -0,0 +1,25 @@ +Altra +~~~~~ + +Following sections include sample calibration data measured on +s62-t34-sut1 server running in one of the Altra testbeds. + + +Linux cmdline +^^^^^^^^^^^^^ + +:: + + $ cat /proc/cmdline + BOOT_IMAGE=/vmlinuz-5.4.0-65-generic root=/dev/mapper/ubuntu--vg-ubuntu--lv ro audit=0 default_hugepagesz=2M hugepagesz=1G hugepages=32 hugepagesz=2M hugepages=32768 iommu.passthrough=1 isolcpus=1-40,81-120 nmi_watchdog=0 nohz_full=1-40,81-120 nosoftlockup processor.max_cstate=1 rcu_nocbs=1-40,81-120 + +Linux uname +^^^^^^^^^^^ + +:: + + $ uname -a + Linux s62-t34-sut1 5.4.0-65-generic #73-Ubuntu SMP Mon Jan 18 17:27:25 UTC 2021 aarch64 aarch64 aarch64 GNU/Linux + + +.. include:: ../introduction/test_environment_sut_meltspec_alt.rst diff --git a/docs/report/introduction/test_environment_sut_meltspec_alt.rst b/docs/report/introduction/test_environment_sut_meltspec_alt.rst new file mode 100644 index 0000000000..b087a93900 --- /dev/null +++ b/docs/report/introduction/test_environment_sut_meltspec_alt.rst @@ -0,0 +1,96 @@ +Spectre and Meltdown Checks +^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +Following section displays the output of a running shell script to tell if +system is vulnerable against the several "speculative execution" CVEs that were +made public in 2018. Script is available on `Spectre & Meltdown Checker Github +<https://github.com/speed47/spectre-meltdown-checker>`_. + +:: + + Spectre and Meltdown mitigation detection tool v0.45 + + Checking for vulnerabilities on current system + Kernel is Linux 5.4.0-65-generic #73-Ubuntu SMP Mon Jan 18 17:27:25 UTC 2021 aarch64 + CPU is ARM v8 model 0xd0c + + Hardware check + * CPU vulnerability to the speculative execution attack variants + * Affected by CVE-2017-5753 (Spectre Variant 1, bounds check bypass): YES + * Affected by CVE-2017-5715 (Spectre Variant 2, branch target injection): NO + * Affected by CVE-2017-5754 (Variant 3, Meltdown, rogue data cache load): NO + * Affected by CVE-2018-3640 (Variant 3a, rogue system register read): NO + * Affected by CVE-2018-3639 (Variant 4, speculative store bypass): YES + * Affected by CVE-2018-3615 (Foreshadow (SGX), L1 terminal fault): NO + * Affected by CVE-2018-3620 (Foreshadow-NG (OS), L1 terminal fault): NO + * Affected by CVE-2018-3646 (Foreshadow-NG (VMM), L1 terminal fault): NO + * Affected by CVE-2018-12126 (Fallout, microarchitectural store buffer data sampling (MSBDS)): NO + * Affected by CVE-2018-12130 (ZombieLoad, microarchitectural fill buffer data sampling (MFBDS)): NO + * Affected by CVE-2018-12127 (RIDL, microarchitectural load port data sampling (MLPDS)): NO + * Affected by CVE-2019-11091 (RIDL, microarchitectural data sampling uncacheable memory (MDSUM)): NO + * Affected by CVE-2019-11135 (ZombieLoad V2, TSX Asynchronous Abort (TAA)): NO + * Affected by CVE-2018-12207 (No eXcuses, iTLB Multihit, machine check exception on page size changes (MCEPSC)): NO + * Affected by CVE-2020-0543 (Special Register Buffer Data Sampling (SRBDS)): NO + + CVE-2017-5753 aka Spectre Variant 1, bounds check bypass + * Mitigated according to the /sys interface: YES (Mitigation: __user pointer sanitization) + > STATUS: UNKNOWN (/sys vulnerability interface use forced, but it's not available!) + + CVE-2017-5715 aka Spectre Variant 2, branch target injection + * Mitigated according to the /sys interface: YES (Not affected) + > STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not affected) + + CVE-2017-5754 aka Variant 3, Meltdown, rogue data cache load + * Mitigated according to the /sys interface: YES (Not affected) + * Running as a Xen PV DomU: NO + > STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not affected) + + CVE-2018-3640 aka Variant 3a, rogue system register read + * CPU microcode mitigates the vulnerability: NO + > STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not affected) + + CVE-2018-3639 aka Variant 4, speculative store bypass + * Mitigated according to the /sys interface: YES (Mitigation: Speculative Store Bypass disabled via prctl) + > STATUS: NOT VULNERABLE (Mitigation: Speculative Store Bypass disabled via prctl) + + CVE-2018-3615 aka Foreshadow (SGX), L1 terminal fault + * CPU microcode mitigates the vulnerability: N/A + > STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not affected) + + CVE-2018-3620 aka Foreshadow-NG (OS), L1 terminal fault + * Mitigated according to the /sys interface: YES (Not affected) + > STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not affected) + + CVE-2018-3646 aka Foreshadow-NG (VMM), L1 terminal fault + * Information from the /sys interface: Not affected + > STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not affected) + + CVE-2018-12126 aka Fallout, microarchitectural store buffer data sampling (MSBDS) + * Mitigated according to the /sys interface: YES (Not affected) + > STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not affected) + + CVE-2018-12130 aka ZombieLoad, microarchitectural fill buffer data sampling (MFBDS) + * Mitigated according to the /sys interface: YES (Not affected) + > STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not affected) + + CVE-2018-12127 aka RIDL, microarchitectural load port data sampling (MLPDS) + * Mitigated according to the /sys interface: YES (Not affected) + > STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not affected) + + CVE-2019-11091 aka RIDL, microarchitectural data sampling uncacheable memory (MDSUM) + * Mitigated according to the /sys interface: YES (Not affected) + > STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not affected) + + CVE-2019-11135 aka ZombieLoad V2, TSX Asynchronous Abort (TAA) + * Mitigated according to the /sys interface: YES (Not affected) + > STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not affected) + + CVE-2018-12207 aka No eXcuses, iTLB Multihit, machine check exception on page size changes (MCEPSC) + * Mitigated according to the /sys interface: YES (Not affected) + > STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not affected) + + CVE-2020-0543 aka Special Register Buffer Data Sampling (SRBDS) + * Mitigated according to the /sys interface: YES (Not affected) + > STATUS: NOT VULNERABLE (your CPU vendor reported your CPU model as not affected) + + > SUMMARY: CVE-2017-5753:?? CVE-2017-5715:OK CVE-2017-5754:OK CVE-2018-3640:OK CVE-2018-3639:OK CVE-2018-3615:OK CVE-2018-3620:OK CVE-2018-3646:OK CVE-2018-12126:OK CVE-2018-12130:OK CVE-2018-12127:OK CVE-2019-11091:OK CVE-2019-11135:OK CVE-2018-12207:OK CVE-2020-0543:OK diff --git a/docs/report/vpp_performance_tests/csit_release_notes.rst b/docs/report/vpp_performance_tests/csit_release_notes.rst index 8590ac5c2e..9b7a0a145c 100644 --- a/docs/report/vpp_performance_tests/csit_release_notes.rst +++ b/docs/report/vpp_performance_tests/csit_release_notes.rst @@ -30,6 +30,11 @@ Changes in |csit-release| :ref:`physical_testbeds_2n_icx` and :ref:`physical_testbeds_3n_icx`. + - **Arm Ampere Altra**: Performance test data for these platforms + is now provided by testbeds newly installed in FD.io CSIT labs. + For details about the physical setup see + :ref:`physical_testbeds_3n_alt`. + - **Reduction of tests**: Removed certain test variations executed iteratively for the report (as well as in daily and weekly trending) due to physical testbeds overload. diff --git a/docs/report/vpp_performance_tests/packet_latency/index.rst b/docs/report/vpp_performance_tests/packet_latency/index.rst index 8bc4cd5457..40274b0d06 100644 --- a/docs/report/vpp_performance_tests/packet_latency/index.rst +++ b/docs/report/vpp_performance_tests/packet_latency/index.rst @@ -9,8 +9,8 @@ Packet Latency VPP latency results are generated based on the test data obtained from |csit-release| NDR-PDR throughput tests executed across physical -testbeds hosted in LF FD.io labs: 3n-skx, 2n-skx, 2n-clx, 3n-tsh, 2n-tx2, -2n-zn2, 2n-aws. +testbeds hosted in LF FD.io labs: 2n-icx, 3n-icx, 2n-aws, 2n-skx, 3n-skx, +2n-clx, 2n-zn2, 3n-alt, 3n-tsh, 2n-tx2. Latency by percentile distribution plots are used to show packet latency percentiles at different packet rate load levels: i) No-Load latency diff --git a/docs/report/vpp_performance_tests/packet_throughput_graphs/index.rst b/docs/report/vpp_performance_tests/packet_throughput_graphs/index.rst index d0b0810f82..6371e010c9 100644 --- a/docs/report/vpp_performance_tests/packet_throughput_graphs/index.rst +++ b/docs/report/vpp_performance_tests/packet_throughput_graphs/index.rst @@ -39,17 +39,18 @@ Graphs are split into sections as follows: - **testbed_type**: + - 2n-icx: 2-node Xeon Icelake + - 3n-icx: 3-node Xeon Icelake + - 2n-aws: 2-node AWS - 2n-skx: 2-node Xeon Skylake - 3n-skx: 3-node Xeon Skylake - 2n-clx: 2-node Xeon Cascade Lake + - 2n-zn2: 2-node AMD Zen2 + - 3n-alt: 2-node Arm Altra - 3n-tsh: 3-node Arm TaiShan - 2n-tx2: 2-node Arm ThunderX2 - - 2n zn2: 2-node AMD Zen2 - 2n-dnv: 2-node Atom Denverton - 3n-dnv: 3-node Atom Denverton - - 2n-aws: 2-node AWS - - 2n-icx: 2-node Xeon Icelake - - 3n-icx: 3-node Xeon Icelake - **nic_model**: @@ -135,6 +136,8 @@ Additional information about graph data: .. note:: Test results are stored in + `build logs from FD.io vpp performance job 2n-icx`_, + `build logs from FD.io vpp performance job 3n-icx`_, `build logs from FD.io vpp performance job 2n-aws`_, `build logs from FD.io vpp performance job 2n-skx`_, `build logs from FD.io vpp performance job 3n-skx`_, diff --git a/docs/report/vpp_performance_tests/test_environment.rst b/docs/report/vpp_performance_tests/test_environment.rst index f51d07c0ff..dec8780904 100644 --- a/docs/report/vpp_performance_tests/test_environment.rst +++ b/docs/report/vpp_performance_tests/test_environment.rst @@ -120,6 +120,8 @@ Description of VPP startup settings used in CSIT is provided in .. include:: ../introduction/test_environment_sut_calib_dnv.rst +.. include:: ../introduction/test_environment_sut_calib_alt.rst + .. include:: ../introduction/test_environment_sut_calib_tsh.rst .. include:: ../introduction/test_environment_sut_calib_tx2.rst diff --git a/docs/report/vpp_performance_tests/throughput_speedup_multi_core/index.rst b/docs/report/vpp_performance_tests/throughput_speedup_multi_core/index.rst index 0f3f5598bb..0bb3b19f39 100644 --- a/docs/report/vpp_performance_tests/throughput_speedup_multi_core/index.rst +++ b/docs/report/vpp_performance_tests/throughput_speedup_multi_core/index.rst @@ -10,7 +10,8 @@ Speedup Multi-Core Speedup Multi-Core throughput graphs are generated by multiple executions of the same performance tests across physical testbeds hosted -LF FD.io labs: 2n-skx, 3n-skx, 2n-clx, 3n-tsh, 2n-tx2, 2n-dnv, 3n-dnv. +LF FD.io labs: 2n-aws, 2n-skx, 3n-skx, 2n-clx, 2n-zn2, 3n-alt, 3n-tsh, 2n-tx2, +2n-dnv, 3n-dnv. Grouped bars illustrate the 64B/78B packet throughput speedup ratio for 2- and 4-core multi-threaded VPP configurations relative to 1-core configurations. |