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-rw-r--r--docs/report/dpdk_performance_tests/packet_latency_graphs/ip4.rst4
-rw-r--r--docs/report/dpdk_performance_tests/packet_latency_graphs/l2.rst4
-rw-r--r--docs/report/dpdk_performance_tests/packet_throughput_graphs/ip4.rst4
-rw-r--r--docs/report/dpdk_performance_tests/packet_throughput_graphs/l2.rst8
4 files changed, 16 insertions, 4 deletions
diff --git a/docs/report/dpdk_performance_tests/packet_latency_graphs/ip4.rst b/docs/report/dpdk_performance_tests/packet_latency_graphs/ip4.rst
index 9dd2add5aa..8f5b807240 100644
--- a/docs/report/dpdk_performance_tests/packet_latency_graphs/ip4.rst
+++ b/docs/report/dpdk_performance_tests/packet_latency_graphs/ip4.rst
@@ -39,6 +39,10 @@ a.k.a. L3FWD data plane thread(s), and their physical CPU core(s) placement.
CSIT source code for the test cases used for plots can be found in
`CSIT git repository <https://git.fd.io/csit/tree/tests/dpdk/perf?h=rls1810>`_.
+.. raw:: latex
+
+ \clearpage
+
3n-hsw-x520
~~~~~~~~~~~
diff --git a/docs/report/dpdk_performance_tests/packet_latency_graphs/l2.rst b/docs/report/dpdk_performance_tests/packet_latency_graphs/l2.rst
index a673dc1318..32dec95c00 100644
--- a/docs/report/dpdk_performance_tests/packet_latency_graphs/l2.rst
+++ b/docs/report/dpdk_performance_tests/packet_latency_graphs/l2.rst
@@ -40,6 +40,10 @@ thread(s), and their physical CPU core(s) placement.
CSIT source code for the test cases used for plots can be found in
`CSIT git repository <https://git.fd.io/csit/tree/tests/dpdk/perf?h=rls1810>`_.
+.. raw:: latex
+
+ \clearpage
+
3n-hsw-x520
~~~~~~~~~~~
diff --git a/docs/report/dpdk_performance_tests/packet_throughput_graphs/ip4.rst b/docs/report/dpdk_performance_tests/packet_throughput_graphs/ip4.rst
index 77ed39ad32..190aa3d6ac 100644
--- a/docs/report/dpdk_performance_tests/packet_throughput_graphs/ip4.rst
+++ b/docs/report/dpdk_performance_tests/packet_throughput_graphs/ip4.rst
@@ -40,6 +40,10 @@ data plane thread(s), and their physical CPU core(s) placement.
CSIT source code for the test cases used for plots can be found in
`CSIT git repository <https://git.fd.io/csit/tree/tests/dpdk/perf?h=rls1810>`_.
+.. raw:: latex
+
+ \clearpage
+
3n-hsw-x520
~~~~~~~~~~~
diff --git a/docs/report/dpdk_performance_tests/packet_throughput_graphs/l2.rst b/docs/report/dpdk_performance_tests/packet_throughput_graphs/l2.rst
index eeb4d652d5..143b864e8f 100644
--- a/docs/report/dpdk_performance_tests/packet_throughput_graphs/l2.rst
+++ b/docs/report/dpdk_performance_tests/packet_throughput_graphs/l2.rst
@@ -1,8 +1,4 @@
-.. raw:: latex
-
- \clearpage
-
.. raw:: html
<script type="text/javascript">
@@ -40,6 +36,10 @@ data plane thread(s), and their physical CPU core(s) placement.
CSIT source code for the test cases used for plots can be found in
`CSIT git repository <https://git.fd.io/csit/tree/tests/dpdk/perf?h=rls1810>`_.
+.. raw:: latex
+
+ \clearpage
+
3n-hsw-x520
~~~~~~~~~~~