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-rw-r--r--docs/report/vpp_performance_tests/packet_latency_graphs/vm_vhost.rst11
1 files changed, 4 insertions, 7 deletions
diff --git a/docs/report/vpp_performance_tests/packet_latency_graphs/vm_vhost.rst b/docs/report/vpp_performance_tests/packet_latency_graphs/vm_vhost.rst
index eff64690c0..b229eff2a4 100644
--- a/docs/report/vpp_performance_tests/packet_latency_graphs/vm_vhost.rst
+++ b/docs/report/vpp_performance_tests/packet_latency_graphs/vm_vhost.rst
@@ -14,14 +14,11 @@ a.k.a. VPP data plane thread(s), and their physical CPU core(s)
placement.
CSIT source code for the test cases used for plots can be found in
-`CSIT git repository <https://git.fd.io/csit/tree/tests/vpp/perf/vm_vhost?h=rls1901>`_.
+`CSIT git repository <https://git.fd.io/csit/tree/tests/vpp/perf/vm_vhost?h=rls1908>`_.
.. toctree::
- vm_vhost-3n-hsw-x520
- vm_vhost-3n-hsw-x710
- vm_vhost-3n-skx-x710
- vm_vhost-2n-skx-x710
-
-..
vm_vhost-2n-skx-xxv710
+ vm_vhost-3n-skx-xxv710
+ vm_vhost-3n-skx-x710
+ vm_vhost-3n-hsw-xl710