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Diffstat (limited to 'docs/report/vpp_performance_tests/packet_latency_graphs/vts.rst')
| -rw-r--r-- | docs/report/vpp_performance_tests/packet_latency_graphs/vts.rst | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/docs/report/vpp_performance_tests/packet_latency_graphs/vts.rst b/docs/report/vpp_performance_tests/packet_latency_graphs/vts.rst index 65a4dcf8b3..5a5a9a64d2 100644 --- a/docs/report/vpp_performance_tests/packet_latency_graphs/vts.rst +++ b/docs/report/vpp_performance_tests/packet_latency_graphs/vts.rst @@ -14,7 +14,7 @@ a.k.a. VPP data plane thread(s), and their physical CPU core(s) placement. CSIT source code for the test cases used for plots can be found in -`CSIT git repository <https://git.fd.io/csit/tree/tests/vpp/perf/vts?h=rls1810>`_. +`CSIT git repository <https://git.fd.io/csit/tree/tests/vpp/perf/vts?h=rls1901>`_. .. toctree:: |