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-rw-r--r--docs/report/vpp_performance_tests/packet_latency_graphs/vts.rst9
1 files changed, 5 insertions, 4 deletions
diff --git a/docs/report/vpp_performance_tests/packet_latency_graphs/vts.rst b/docs/report/vpp_performance_tests/packet_latency_graphs/vts.rst
index 5a5a9a64d2..dc05549b0d 100644
--- a/docs/report/vpp_performance_tests/packet_latency_graphs/vts.rst
+++ b/docs/report/vpp_performance_tests/packet_latency_graphs/vts.rst
@@ -3,8 +3,8 @@
\clearpage
-VTS
-===
+Virtual Topology System
+=======================
This section includes summary graphs of VPP Phy-to-VM(s)-to-Phy packet
latency with with VM virtio and VPP vhost-user virtual interfaces
@@ -14,8 +14,9 @@ a.k.a. VPP data plane thread(s), and their physical CPU core(s)
placement.
CSIT source code for the test cases used for plots can be found in
-`CSIT git repository <https://git.fd.io/csit/tree/tests/vpp/perf/vts?h=rls1901>`_.
+`CSIT git repository <https://git.fd.io/csit/tree/tests/vpp/perf/vts?h=rls1908>`_.
.. toctree::
- vts-3n-hsw-x520
+ vts-3n-skx-xxv710
+ vts-3n-hsw-xl710