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diff --git a/docs/report/vpp_performance_tests/throughput_speedup_multi_core/container_memif.rst b/docs/report/vpp_performance_tests/throughput_speedup_multi_core/container_memif.rst new file mode 100644 index 0000000000..4fb8791dff --- /dev/null +++ b/docs/report/vpp_performance_tests/throughput_speedup_multi_core/container_memif.rst @@ -0,0 +1,66 @@ +Container memif Connections +=========================== + +Following sections include Throughput Speedup Analysis for VPP multi- +core multi-thread configurations with no Hyper-Threading, specifically +for tested 2t2c (2threads, 2cores) and 4t4c scenarios. 1t1c throughput +results are used as a reference for reported speedup ratio. +Performance is reported for VPP +running in multiple configurations of VPP worker thread(s), a.k.a. VPP +data plane thread(s), and their physical CPU core(s) placement. + +NDR Throughput +-------------- + +VPP NDR 64B packet throughput speedup ratio is presented in the graphs +below for 10ge2p1x520 network interface card. + +NIC 10ge2p1x520 +~~~~~~~~~~~~~~~ + +.. raw:: html + + <iframe width="700" height="1000" frameborder="0" scrolling="no" src="../../_static/vpp/10ge2p1x520-64B-container-memif-tsa-ndrdisc.html"></iframe> + +.. raw:: latex + + \begin{figure}[H] + \centering + \graphicspath{{../_build/_static/vpp/}} + \includegraphics[clip, trim=0cm 8cm 5cm 0cm, width=0.70\textwidth]{10ge2p1x520-64B-container-memif-tsa-ndrdisc} + \label{fig:10ge2p1x520-64B-container-memif-tsa-ndrdisc} + \end{figure} + +*Figure 1. Throughput Speedup Analysis - Multi-Core Speedup Ratio - Normalized +NDR Throughput for Phy-to-Phy L2 Ethernet Switching (base).* + +CSIT source code for the test cases used for above plots can be found in +`CSIT git repository <https://git.fd.io/csit/tree/tests/vpp/perf/container_memif?h=rls1804>`_. + +PDR Throughput +-------------- + +VPP PDR 64B packet throughput speedup ratio is presented in the graphs +below for 10ge2p1x520 network interface card. + +NIC 10ge2p1x520 +~~~~~~~~~~~~~~~ + +.. raw:: html + + <iframe width="700" height="1000" frameborder="0" scrolling="no" src="../../_static/vpp/10ge2p1x520-64B-container-memif-tsa-pdrdisc.html"></iframe> + +.. raw:: latex + + \begin{figure}[H] + \centering + \graphicspath{{../_build/_static/vpp/}} + \includegraphics[clip, trim=0cm 8cm 5cm 0cm, width=0.70\textwidth]{10ge2p1x520-64B-container-memif-tsa-pdrdisc} + \label{fig:10ge2p1x520-64B-container-memif-tsa-pdrdisc} + \end{figure} + +*Figure 2. Throughput Speedup Analysis - Multi-Core Speedup Ratio - Normalized +PDR Throughput for Phy-to-Phy L2 Ethernet Switching (base).* + +CSIT source code for the test cases used for above plots can be found in +`CSIT git repository <https://git.fd.io/csit/tree/tests/vpp/perf/container_memif?h=rls1804>`_. |