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- Refactor Performance TCs due to changes in Hyperthreading and RXQ allocations.
- Simplify the structure of suite to avoid large refactors in future.
Change-Id: Ifb1b9719391f26745f075a900bd9fb39b6cb809c
Signed-off-by: Peter Mikus <pmikus@cisco.com>
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Due to automatization of SMT detection this change is suppose to
remove static thread/core tags in favor of dynamic one. Leaving the
static tags for number of physical cores to be able to select TCs.
Change-Id: I7f99f605821f363e45c333f46d1dea786693521b
Signed-off-by: Peter Mikus <pmikus@cisco.com>
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- Clean up of 2-node setup KWs
Change-Id: I59fc901fb57544eceb6a041b56b515cda8babf85
Signed-off-by: Peter Mikus <pmikus@cisco.com>
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+ 40ge2p1xl710-ethip4ipsecbasetnl-ip4base-int-aes-gcm-mrr.robot
+ 40ge2p1xl710-ethip4ipsecbasetnl-ip4base-int-cbc-sha1-mrr.robot
+ 40ge2p1xl710-ethip4ipsecbasetnlsw-ip4base-int-aes-gcm-mrr.robot
+ 40ge2p1xl710-ethip4ipsecbasetnlsw-ip4base-int-cbc-sha1-mrr.robot
+ 40ge2p1xl710-ethip4ipsecscale1000tnl-ip4base-int-aes-gcm-mrr.robot
+ 40ge2p1xl710-ethip4ipsecscale1000tnl-ip4base-int-cbc-sha1-mrr.robot
Do not add test cases for 9000B framesize yet.
Improve other suites to keep the style consistent.
Change-Id: I03a58e8d6745083e267b9d53bb3b85efcb2ea827
Signed-off-by: Vratko Polak <vrpolak@cisco.com>
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- Reduce binary step fof:
64B -> 50Kpps
1518B -> 50Kpps
9000B -> 10Kpps
IMIX -> 50Kpps
Change-Id: Id88bff7b1c37b2a03583dd27ca3db720ec7ae4a2
Signed-off-by: Peter Mikus <pmikus@cisco.com>
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Configure RX-desc and TX-desc to 2048 for FVL XL710 cards.
Change-Id: I1876f332bdc6100bf24f2b2317de33c0d1a4c9bf
Signed-off-by: Peter Mikus <pmikus@cisco.com>
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Change-Id: I772c9e214be2461adf58124998d272e7d795220f
Signed-off-by: Tibor Frank <tifrank@cisco.com>
Signed-off-by: Maciek Konstantynowicz <mkonstan@cisco.com>
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