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fdio_csit_dev_plan.txt - DRAFT

FD.io CSIT High-Level Development Plan
======================================

Proposed Work Organisation
--------------------------

* Each work area is covered by owners.
  - Technical Lead (TL) - overall responsibility incl. design, detailed
    work plan, DT coordination, managing dependencies.
  - Development Team (DT) - doing work following the TL.
  - Project Lead (PL) - involved in all work areas at higher level,
    focusing on requirements definitions, design and work reviews,
    acceptance.
  - For work areas with large number of deliverables there could be
    multiple TLs e.g. for operations, framework or test refactor.
  - FD.io CSIT owners' initials listed with suffix strings:
    "[TL;DT1..DTn;PL]", contact details at the end of this note.

* Actual work breakdown tracked in FD.io CSIT jira:
  - Tasks tracked in Jira under CSIT Epics.

Plan Timeline
-------------

* Current release cycle:
  - FD.io CSIT rls18.07, associated with VPP-18.07.
* Sub-sequent releases:
  - FD.io CSIT rls18.10, rls1812, ..
  - Work not completed fully in current release cycle marked as backlog
    for follow-on release(s).

Plan Summary
------------

* Infrastructure, Framework, Tools
  * New Skylake testbed infra to increase FD.io CSIT lab capacity.
    [PM;EK,PM;MK]
  * Introduce 2-node performance tests for new Skylake testbed infra.
    [TF;JG,PM,TF;MK]
  * Productize duration aware multi-rate MLR search. [VP;PM,VP;MK]
  * Improve continuous performance trending: anomaly detection tunings,
    add dpdk. [TF;TF,VP;MK]
  * Complete and phase into production continuous per VPP patch
    performance tests. [PM;PM,TF,VP;MK]
  * Implement proper per-packet latency measurements, reporting and
    analytics with TRex HdrHistogram. [TF;PM,TF,VP;MK]
  * Evolve presentation and analytics layer (PAL) addressing growing
    volumes of test measurement and telemetry data. [TF;EK,PM,TF,VP;MK]
  * Start migration from CSIT_VIRL to VPP_Path (make_test) and
    VPP_Device integration tests. [JG;EK,JG,TF;MK]
  * Enhance CSIT reports, trending pages, PAL backend and trending test
    code addressing wider set of data plane workloads and automate
    CI/CD trending communication to FD.io community. [TF;PM,TF,VP;MK]
  * Automate VPP performance regression search. [TF;TF,VP;MK]
  * Other refactor: VAT to PAPI, data driven tests, suite duration,
    infra overhead. [VP;JG,PM,TF,VP;MK]

* Testing, Performance
  * New tests: more TCP stack, SRv6, memif; AVF driver (no DPDK).
    [MK;JG,PM,TF,VP;MK]
  * VPP_Path: migration of P0 VIRL tests to VPP_make_test, followed by
    qualification of VIRL P1, P2 tests; adding use case driven
    functional tests.
  * VPP_Device: new use cases per VPP_Device design note <add link>.
  * VPP_Path_Device: continue to add relevant tests.

* Other
  * FD.io Operations. [All]
  * ARM, Atom servers. [?]
  * API changes across VPP major versions. [?]
  * Plugin dependencies. [?]
  * DPDK driver dependencies. [?]

FD.io CSIT Contributors
-----------------------

* JG - Jan Gelety <jgelety@cisco.com>, irc: jgelety.
* EK - Ed Kern <ejk@cisco.com>, irc: snergster.
* MK - Maciek Konstantynowicz <mkonstan@cisco.com>, irc: mackonstan.
* PM - Peter Mikus <pmikus@cisco.com>, irc: pmikus.
* TF - Tibor Frank <tifrank@cisco.com>, irc: tifrank.
* VP - Vratko Polak <vrpolak@cisco.com>, irc: vrpolak.
N | FEATURE | ACL | ACL_STATEFUL | ... | OACL | ACL1 | 100k_FLOWS | ... | Suite Setup | Run Keywords | ... | Set up 3-node performance topology with DUT's NIC model | L2 | ... | Intel-X520-DA2 | ... | AND | Set up performance test suite with ACL | ... | Suite Teardown | Tear down 3-node performance topology | ... | Test Setup | Set up performance test | ... | Test Teardown | Tear down mrr test with ACL | ... | Test Template | Local Template | ... | Documentation | *Raw results L2BD test cases with ACL* | ... | ... | *[Top] Network Topologies:* TG-DUT1-DUT2-TG 3-node circular topology\ | ... | with single links between nodes. | ... | *[Enc] Packet Encapsulations:* Eth-IPv4-UDP for L2 switching of IPv4. | ... | *[Cfg] DUT configuration:* DUT1 is configured with L2 bridge domain\ | ... | and MAC learning enabled. DUT2 is configured with L2 cross-connects.\ | ... | Required ACL rules are applied to input paths of both DUT1 intefaces.\ | ... | DUT1 and DUT2 are tested with 2p10GE NIC X520 Niantic by Intel.\ | ... | *[Ver] TG verification:* In MaxReceivedRate test TG sends traffic | ... | at line rate and reports total received/sent packets over trial period. | ... | Test packets are generated by TG on\ | ... | links to DUTs. TG traffic profile contains two L3 flow-groups\ | ... | (flow-group per direction, ${flows_per_dir} flows per flow-group) with\ | ... | all packets containing Ethernet header, IPv4 header with UDP header and\ | ... | static payload. MAC addresses are matching MAC addresses of the TG node\ | ... | interfaces. | ... | *[Ref] Applicable standard specifications:* RFC2544. *** Variables *** # X520-DA2 bandwidth limit | ${s_limit}= | ${10000000000} # ACL test setup | ${acl_action}= | permit+reflect | ${acl_apply_type}= | output | ${no_hit_aces_number}= | 1 | ${flows_per_dir}= | 100k # starting points for non-hitting ACLs | ${src_ip_start}= | 30.30.30.1 | ${dst_ip_start}= | 40.40.40.1 | ${ip_step}= | ${1} | ${sport_start}= | ${1000} | ${dport_start}= | ${1000} | ${port_step}= | ${1} | ${trex_stream1_subnet}= | 10.10.10.0/24 | ${trex_stream2_subnet}= | 20.20.20.0/24 | ${traffic_profile}= | trex-sl-3n-ethip4udp-100u1000p-conc *** Keywords *** | Local Template | | [Documentation] | FIXME. | | [Arguments] | ${framesize} | ${phy_cores} | ${rxq}=${None} | | ... | | Given Add worker threads and rxqueues to all DUTs | ${phy_cores} | ${rxq} | | And Add PCI devices to all DUTs | | ${max_rate} | ${jumbo} = | Get Max Rate And Jumbo And Handle Multi Seg | | ... | ${s_limit} | ${framesize} | | And Apply startup configuration on all VPP DUTs | | When Initialize L2 bridge domain with IPv4 ACLs on DUT1 in 3-node circular topology | | Then Traffic should pass with maximum rate | | ... | ${max_rate}pps | ${framesize} | ${traffic_profile} *** Test Cases *** | tc01-64B-1c-eth-l2bdbasemaclrn-oacl1sf-100kflows-mrr | | [Tags] | 64B | 1C | | framesize=${64} | phy_cores=${1} | tc02-64B-2c-eth-l2bdbasemaclrn-oacl1sf-100kflows-mrr | | [Tags] | 64B | 2C | | framesize=${64} | phy_cores=${2} | tc03-64B-4c-eth-l2bdbasemaclrn-oacl1sf-100kflows-mrr | | [Tags] | 64B | 4C | | framesize=${64} | phy_cores=${4} | tc04-1518B-1c-eth-l2bdbasemaclrn-oacl1sf-100kflows-mrr | | [Tags] | 1518B | 1C | | framesize=${1518} | phy_cores=${1} | tc05-1518B-2c-eth-l2bdbasemaclrn-oacl1sf-100kflows-mrr | | [Tags] | 1518B | 2C | | framesize=${1518} | phy_cores=${2} | tc06-1518B-4c-eth-l2bdbasemaclrn-oacl1sf-100kflows-mrr | | [Tags] | 1518B | 4C | | framesize=${1518} | phy_cores=${4} | tc07-9000B-1c-eth-l2bdbasemaclrn-oacl1sf-100kflows-mrr | | [Tags] | 9000B | 1C | | framesize=${9000} | phy_cores=${1} | tc08-9000B-2c-eth-l2bdbasemaclrn-oacl1sf-100kflows-mrr | | [Tags] | 9000B | 2C | | framesize=${9000} | phy_cores=${2} | tc09-9000B-4c-eth-l2bdbasemaclrn-oacl1sf-100kflows-mrr | | [Tags] | 9000B | 4C | | framesize=${9000} | phy_cores=${4} | tc10-IMIX-1c-eth-l2bdbasemaclrn-oacl1sf-100kflows-mrr | | [Tags] | IMIX | 1C | | framesize=IMIX_v4_1 | phy_cores=${1} | tc11-IMIX-2c-eth-l2bdbasemaclrn-oacl1sf-100kflows-mrr | | [Tags] | IMIX | 2C | | framesize=IMIX_v4_1 | phy_cores=${2} | tc12-IMIX-4c-eth-l2bdbasemaclrn-oacl1sf-100kflows-mrr | | [Tags] | IMIX | 4C | | framesize=IMIX_v4_1 | phy_cores=${4}