m_rx_queue=rx_queue; } void configure(uint16_t nb_rx_queue, uint16_t nb_tx_queue, const struct rte_eth_conf *eth_conf); void get_stats(CPhyEthIFStats *stats); int dump_fdir_global_stats(FILE *fd); int reset_hw_flow_stats(); int get_flow_stats(rx_per_flow_t *rx_stats, tx_per_flow_t *tx_stats, int min, int max, bool reset); int get_flow_stats_payload(rx_per_flow_t *rx_stats, tx_per_flow_t *tx_stats, int min, int max, bool reset); void rx_queue_setup(uint16_t rx_queue_id, uint16_t nb_rx_desc, unsigned int socket_id, const struct rte_eth_rxconf *rx_conf, struct rte_mempool *mb_pool); void tx_queue_setup(uint16_t tx_queue_id, uint16_t nb_tx_desc, unsigned int socket_id, const struct rte_eth_txconf *tx_conf); void stop_rx_drop_queue(); void configure_rx_duplicate_rules(); void start(); void stop(); void disable_flow_control(); void dump_stats(FILE *fd); void set_ignore_stats_base(CPreTestStats &pre_stats); void update_counters(); void stats_clear(); uint8_t get_port_id(){ return (m_port_id); } float get_last_tx_rate(){ return (m_last_tx_rate); } float get_last_rx_rate(){ return (m_last_rx_rate); } float get_last_tx_pps_rate(){ return (m_last_tx_pps); } float get_last_rx_pps_rate(){ return (m_last_rx_pps); } CPhyEthIFStats & get_stats(){ return ( m_stats ); } CPhyEthIgnoreStats & get_ignore_stats() { return m_ignore_stats; } void flush_dp_rx_queue(void); void flush_rx_queue(void); int add_rx_flow_stat_rule(uint8_t port_id, uint16_t l3_type, uint8_t l4_proto , uint8_t ipv6_next_h, uint16_t id) const; int del_rx_flow_stat_rule(uint8_t port_id, uint16_t l3_type, uint8_t l4_proto , uint8_t ipv6_next_h, uint16_t id) const; inline uint16_t tx_burst(uint16_t queue_id, struct rte_mbuf **tx_pkts, uint16_t nb_pkts) { return rte_eth_tx_burst(m_port_id, queue_id, tx_pkts, nb_pkts); } inline uint16_t rx_burst(uint16_t queue_id, struct rte_mbuf **rx_pkts, uint16_t nb_pkts) { return rte_eth_rx_burst(m_port_id, queue_id, rx_pkts, nb_pkts); } inline uint32_t pci_reg_read(uint32_t reg_off) { void *reg_addr; uint32_t reg_v; reg_addr = (void *)((char *)m_dev_info.pci_dev->mem_resource[0].addr + reg_off); reg_v = *((volatile uint32_t *)reg_addr); return rte_le_to_cpu_32(reg_v); } inline void pci_reg_write(uint32_t reg_off, uint32_t reg_v) { void *reg_addr; reg_addr = (void *)((char *)m_dev_info.pci_dev->mem_resource[0].addr + reg_off); *((volatile uint32_t *)reg_addr) = rte_cpu_to_le_32(reg_v); } void dump_stats_extended(FILE *fd); uint8_t get_rte_port_id(void) { return m_port_id; } int get_rx_stat_capabilities(); const std::vector<std::pair<uint8_t, uint8_t>> & get_core_list(); TRexPortAttr * get_port_attr() { return m_port_attr; } private: uint8_t m_port_id; uint8_t m_rx_queue; uint64_t m_sw_try_tx_pkt; uint64_t m_sw_tx_drop_pkt; CBwMeasure m_bw_tx; CBwMeasure m_bw_rx; CPPSMeasure m_pps_tx; CPPSMeasure m_pps_rx; CPhyEthIFStats m_stats; CPhyEthIgnoreStats m_ignore_stats; TRexPortAttr *m_port_attr; float m_last_tx_rate; float m_last_rx_rate; float m_last_tx_pps; float m_last_rx_pps; /* holds the core ID list for this port - (core, dir) list*/ std::vector<std::pair<uint8_t, uint8_t>> m_core_id_list; public: struct rte_eth_dev_info m_dev_info; }; // Because it is difficult to move CGlobalTRex into this h file, defining interface class to it class CGlobalTRexInterface { public: CPhyEthIF *get_ports(uint8_t &port_num); }; #endif