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# Copyright (c) 2021 Intel and/or its affiliates.
# Copyright (c) 2021 Cisco and/or its affiliates.
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at:
#
#     http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.

*** Settings ***
| Resource | resources/libraries/robot/shared/default.robot
| Resource | resources/libraries/robot/crypto/ipsec.robot
|
| Force Tags | 3_NODE_SINGLE_LINK_TOPO | PERFTEST | HW_ENV | NDRPDR | TNL_2
| ... | IP4FWD | IPSEC | IPSECSW | ASYNC | IPSECINT | NIC_Intel-X710 | SCALE
| ... | SCHEDULER | AES_128_CBC | HMAC_SHA_256 | HMAC | AES | DRV_VFIO_PCI
| ... | RXQ_SIZE_0 | TXQ_SIZE_0
| ... | ethip4ipsec2tnlswasync-scheduler-ip4base-int-aes128cbc-hmac256sha
|
| Suite Setup | Setup suite topology interfaces | performance
| Suite Teardown | Tear down suite | performance
| Test Setup | Setup test | performance
| Test Teardown | Tear down test | performance | ipsec_sa
|
| Test Template | Local Template
|
| Documentation | *RFC2544: Pkt throughput IPv4 IPsec tunnel mode.*
|
| ... | *[Top] Network Topologies:* TG-DUT1-DUT2-TG 3-node circular topology
| ... | with single links between nodes.
| ... | *[Enc] Packet Encapsulations:* Eth-IPv4 on TG-DUTn,
| ... | Eth-IPv4-IPSec on DUT1-DUT2
| ... | *[Cfg] DUT configuration:* DUT1 and DUT2 are configured with multiple
| ... | IPsec tunnels between them, run with IPsec async mode and use crypto
| ... | sw scheduler engine to schedule crypto work to crypto cores. DUTs get
| ... | IPv4 traffic from TG, encrypt it and send to another DUT, where packets
| ... | are decrypted and sent back to TG.
| ... | *[Ver] TG verification:* TG finds and reports throughput NDR (Non Drop\
| ... | Rate) with zero packet loss tolerance and throughput PDR (Partial Drop\
| ... | Rate) with non-zero packet loss tolerance (LT) expressed in percentage\
| ... | of packets transmitted. NDR and PDR are discovered for different\
| ... | Ethernet L2 frame sizes using MLRsearch library.\
| ... | Test packets are generated by TG on
| ... | links to DUTs. TG traffic profile contains two L3 flow-groups
| ... | (flow-group per direction, number of flows per flow-group equals to
| ... | number of IPSec tunnels) with all packets
| ... | containing Ethernet header, IPv4 header with IP protocol=61 and
| ... | static payload. MAC addresses are matching MAC addresses of the TG
| ... | node interfaces. Incrementing of IP.dst (IPv4 destination address) field
| ... | is applied to both streams.
| ... | *[Ref] Applicable standard specifications:* RFC4303 and RFC2544.

*** Variables ***
| @{plugins_to_enable}= | dpdk_plugin.so | perfmon_plugin.so
| ... | crypto_native_plugin.so
| ... | crypto_ipsecmb_plugin.so | crypto_sw_scheduler_plugin.so
| ... | crypto_openssl_plugin.so
| ${crypto_type}= | ${None}
| ${nic_name}= | Intel-X710
| ${nic_driver}= | vfio-pci
| ${nic_rxq_size}= | 0
| ${nic_txq_size}= | 0
| ${nic_pfs}= | 2
| ${nic_vfs}= | 0
| ${osi_layer}= | L3
| ${overhead}= | ${62}
| ${tg_if1_ip4}= | 192.168.10.2
| ${dut1_if1_ip4}= | 192.168.10.1
| ${dut1_if2_ip4}= | 100.0.0.1
| ${dut2_if1_ip4}= | 200.0.0.2
| ${dut2_if2_ip4}= | 192.168.20.1
| ${tg_if2_ip4}= | 192.168.20.2
| ${raddr_ip4}= | 20.0.0.0
| ${laddr_ip4}= | 10.0.0.0
| ${addr_range}= | ${24}
| ${n_tunnels}= | ${2}
| ${dp_cores_count}= | ${1}
# Traffic profile:
| ${traffic_profile}= | trex-stl-3n-ethip4-ip4dst${n_tunnels}

*** Keywords ***
| Local Template
| | [Documentation]
| | ... | [Cfg] DUT runs IPSec tunneling AES_128_CBC / HMAC_SHA_256 config.\
| | ... | Each DUT uses one physical core for data plane workers
| | ... | and rest of ${phy_cores} physical core(s) for crypto workers.
| | ... | [Ver] Measure NDR and PDR values using MLRsearch algorithm.\
| |
| | ... | *Arguments:*
| | ... | - frame_size - Framesize in Bytes in integer or string (IMIX_v4_1).
| | ... | Type: integer, string
| | ... | - phy_cores - Total number of physical cores. Type: integer
| | ... | - rxq - Number of RX queues, default value: ${1}. Type: integer
| |
| | [Arguments] | ${frame_size} | ${phy_cores} | ${rxq}=${None}
| |
| | Set Test Variable | \${frame_size}
| |
| | # These are enums (not strings) so they cannot be in Variables table.
| | ${encr_alg}= | Crypto Alg AES CBC 128
| | ${auth_alg}= | Integ Alg SHA 256 128
| |
| | Given Set Max Rate And Jumbo
| | And Add worker threads to all DUTs | ${phy_cores} | ${rxq}
| | And Pre-initialize layer driver | ${nic_driver}
| | And Apply startup configuration on all VPP DUTs
| | When Initialize layer driver | ${nic_driver}
| | And Initialize layer interface
| | And Enable IPSec Async Mode on all VPP DUTs
| | And Set Data Plane And Feature Plane Workers for IPsec on all VPP DUTs
| | And Initialize IPSec in 3-node circular topology
| | And VPP IPsec Create Tunnel Interfaces
| | ... | ${nodes} | ${dut1_if2_ip4} | ${dut2_if1_ip4} | ${DUT1_${int}2}[0]
| | ... | ${DUT2_${int}1}[0] | ${n_tunnels} | ${encr_alg} | ${auth_alg}
| | ... | ${laddr_ip4} | ${raddr_ip4} | ${addr_range}
| | Then Find NDR and PDR intervals using optimized search

*** Test Cases ***
| 64B-2c-ethip4ipsec2tnlswasync-scheduler-ip4base-int-aes128cbc-hmac256sha-ndrpdr
| | [Tags] | 64B | 2C
| | frame_size=${64} | phy_cores=${2}

| 64B-3c-ethip4ipsec2tnlswasync-scheduler-ip4base-int-aes128cbc-hmac256sha-ndrpdr
| | [Tags] | 64B | 3C
| | frame_size=${64} | phy_cores=${3}

| 64B-4c-ethip4ipsec2tnlswasync-scheduler-ip4base-int-aes128cbc-hmac256sha-ndrpdr
| | [Tags] | 64B | 4C
| | frame_size=${64} | phy_cores=${4}

| 1518B-2c-ethip4ipsec2tnlswasync-scheduler-ip4base-int-aes128cbc-hmac256sha-ndrpdr
| | [Tags] | 1518B | 2C
| | frame_size=${1518} | phy_cores=${2}

| 1518B-3c-ethip4ipsec2tnlswasync-scheduler-ip4base-int-aes128cbc-hmac256sha-ndrpdr
| | [Tags] | 1518B | 3C
| | frame_size=${1518} | phy_cores=${3}

| 1518B-4c-ethip4ipsec2tnlswasync-scheduler-ip4base-int-aes128cbc-hmac256sha-ndrpdr
| | [Tags] | 1518B | 4C
| | frame_size=${1518} | phy_cores=${4}

| 9000B-2c-ethip4ipsec2tnlswasync-scheduler-ip4base-int-aes128cbc-hmac256sha-ndrpdr
| | [Tags] | 9000B | 2C
| | frame_size=${9000} | phy_cores=${2}

| 9000B-3c-ethip4ipsec2tnlswasync-scheduler-ip4base-int-aes128cbc-hmac256sha-ndrpdr
| | [Tags] | 9000B | 3C
| | frame_size=${9000} | phy_cores=${3}

| 9000B-4c-ethip4ipsec2tnlswasync-scheduler-ip4base-int-aes128cbc-hmac256sha-ndrpdr
| | [Tags] | 9000B | 4C
| | frame_size=${9000} | phy_cores=${4}

| IMIX-2c-ethip4ipsec2tnlswasync-scheduler-ip4base-int-aes128cbc-hmac256sha-ndrpdr
| | [Tags] | IMIX | 2C
| | frame_size=IMIX_v4_1 | phy_cores=${2}

| IMIX-3c-ethip4ipsec2tnlswasync-scheduler-ip4base-int-aes128cbc-hmac256sha-ndrpdr
| | [Tags] | IMIX | 3C
| | frame_size=IMIX_v4_1 | phy_cores=${3}

| IMIX-4c-ethip4ipsec2tnlswasync-scheduler-ip4base-int-aes128cbc-hmac256sha-ndrpdr
| | [Tags] | IMIX | 4C
| | frame_size=IMIX_v4_1 | phy_cores=${4}
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#include <perfmon/perfmon_intel.h>

static perfmon_intel_pmc_cpu_model_t cpu_model_table[] = {
  {0x56, 0x00, 0},

};

static perfmon_intel_pmc_event_t event_table[] = {
  {
   .event_code = {0x00},
   .umask = 0x01,
   .event_name = "inst_retired.any",
   },
  {
   .event_code = {0x00},
   .umask = 0x02,
   .event_name = "cpu_clk_unhalted.thread",
   },
  {
   .event_code = {0x00},
   .umask = 0x02,
   .event_name = "cpu_clk_unhalted.thread_any",
   },
  {
   .event_code = {0x00},
   .umask = 0x03,
   .event_name = "cpu_clk_unhalted.ref_tsc",
   },
  {
   .event_code = {0x03},
   .umask = 0x02,
   .event_name = "ld_blocks.store_forward",
   },
  {
   .event_code = {0x03},
   .umask = 0x08,
   .event_name = "ld_blocks.no_sr",
   },
  {
   .event_code = {0x05},
   .umask = 0x01,
   .event_name = "misalign_mem_ref.loads",
   },
  {
   .event_code = {0x05},
   .umask = 0x02,
   .event_name = "misalign_mem_ref.stores",
   },
  {
   .event_code = {0x07},
   .umask = 0x01,
   .event_name = "ld_blocks_partial.address_alias",
   },
  {
   .event_code = {0x08},
   .umask = 0x01,
   .event_name = "dtlb_load_misses.miss_causes_a_walk",
   },
  {
   .event_code = {0x08},
   .umask = 0x02,
   .event_name = "dtlb_load_misses.walk_completed_4k",
   },
  {
   .event_code = {0x08},
   .umask = 0x04,
   .event_name = "dtlb_load_misses.walk_completed_2m_4m",
   },
  {
   .event_code = {0x08},
   .umask = 0x08,
   .event_name = "dtlb_load_misses.walk_completed_1g",
   },
  {
   .event_code = {0x08},
   .umask = 0x0e,
   .event_name = "dtlb_load_misses.walk_completed",
   },
  {
   .event_code = {0x08},
   .umask = 0x10,
   .event_name = "dtlb_load_misses.walk_duration",
   },
  {
   .event_code = {0x08},
   .umask = 0x20,
   .event_name = "dtlb_load_misses.stlb_hit_4k",
   },
  {
   .event_code = {0x08},
   .umask = 0x40,
   .event_name = "dtlb_load_misses.stlb_hit_2m",
   },
  {
   .event_code = {0x08},
   .umask = 0x60,
   .event_name = "dtlb_load_misses.stlb_hit",
   },
  {
   .event_code = {0x0D},
   .umask = 0x03,
   .event_name = "int_misc.recovery_cycles",
   },
  {
   .event_code = {0x0D},
   .umask = 0x03,
   .event_name = "int_misc.recovery_cycles_any",
   },
  {
   .event_code = {0x0D},
   .umask = 0x08,
   .event_name = "int_misc.rat_stall_cycles",
   },
  {
   .event_code = {0x0E},
   .umask = 0x01,
   .event_name = "uops_issued.any",
   },
  {
   .event_code = {0x0E},
   .umask = 0x01,
   .event_name = "uops_issued.stall_cycles",
   },
  {
   .event_code = {0x0E},
   .umask = 0x10,
   .event_name = "uops_issued.flags_merge",
   },
  {
   .event_code = {0x0E},
   .umask = 0x20,
   .event_name = "uops_issued.slow_lea",
   },
  {
   .event_code = {0x0E},
   .umask = 0x40,
   .event_name = "uops_issued.single_mul",
   },
  {
   .event_code = {0x14},
   .umask = 0x01,
   .event_name = "arith.fpu_div_active",
   },
  {
   .event_code = {0x24},
   .umask = 0x21,
   .event_name = "l2_rqsts.demand_data_rd_miss",
   },
  {
   .event_code = {0x24},
   .umask = 0x22,
   .event_name = "l2_rqsts.rfo_miss",
   },
  {
   .event_code = {0x24},
   .umask = 0x24,
   .event_name = "l2_rqsts.code_rd_miss",
   },
  {
   .event_code = {0x24},
   .umask = 0x27,
   .event_name = "l2_rqsts.all_demand_miss",
   },
  {
   .event_code = {0x24},
   .umask = 0x30,
   .event_name = "l2_rqsts.l2_pf_miss",
   },
  {
   .event_code = {0x24},
   .umask = 0x3F,
   .event_name = "l2_rqsts.miss",
   },
  {
   .event_code = {0x24},
   .umask = 0x41,
   .event_name = "l2_rqsts.demand_data_rd_hit",
   },
  {
   .event_code = {0x24},
   .umask = 0x42,
   .event_name = "l2_rqsts.rfo_hit",
   },
  {
   .event_code = {0x24},
   .umask = 0x44,
   .event_name = "l2_rqsts.code_rd_hit",
   },
  {
   .event_code = {0x24},
   .umask = 0x50,
   .event_name = "l2_rqsts.l2_pf_hit",
   },
  {
   .event_code = {0x24},
   .umask = 0xE1,
   .event_name = "l2_rqsts.all_demand_data_rd",
   },
  {
   .event_code = {0x24},
   .umask = 0xE2,
   .event_name = "l2_rqsts.all_rfo",
   },
  {
   .event_code = {0x24},
   .umask = 0xE4,
   .event_name = "l2_rqsts.all_code_rd",
   },
  {
   .event_code = {0x24},
   .umask = 0xe7,
   .event_name = "l2_rqsts.all_demand_references",
   },
  {
   .event_code = {0x24},
   .umask = 0xF8,
   .event_name = "l2_rqsts.all_pf",
   },
  {
   .event_code = {0x24},
   .umask = 0xFF,
   .event_name = "l2_rqsts.references",
   },
  {
   .event_code = {0x27},
   .umask = 0x50,
   .event_name = "l2_demand_rqsts.wb_hit",
   },
  {
   .event_code = {0x2E},
   .umask = 0x41,
   .event_name = "longest_lat_cache.miss",
   },
  {
   .event_code = {0x2E},
   .umask = 0x4F,
   .event_name = "longest_lat_cache.reference",
   },
  {
   .event_code = {0x3C},
   .umask = 0x00,
   .event_name = "cpu_clk_unhalted.thread_p",
   },
  {
   .event_code = {0x3C},
   .umask = 0x00,
   .event_name = "cpu_clk_unhalted.thread_p_any",
   },
  {
   .event_code = {0x3C},
   .umask = 0x01,
   .event_name = "cpu_clk_thread_unhalted.ref_xclk",
   },
  {
   .event_code = {0x3C},
   .umask = 0x01,
   .event_name = "cpu_clk_thread_unhalted.ref_xclk_any",
   },
  {
   .event_code = {0x3C},
   .umask = 0x01,
   .event_name = "cpu_clk_unhalted.ref_xclk",
   },
  {
   .event_code = {0x3C},
   .umask = 0x01,
   .event_name = "cpu_clk_unhalted.ref_xclk_any",
   },
  {
   .event_code = {0x3c},
   .umask = 0x02,
   .event_name = "cpu_clk_thread_unhalted.one_thread_active",
   },
  {
   .event_code = {0x3C},
   .umask = 0x02,
   .event_name = "cpu_clk_unhalted.one_thread_active",
   },
  {
   .event_code = {0x48},
   .umask = 0x01,
   .event_name = "l1d_pend_miss.pending",
   },
  {
   .event_code = {0x48},
   .umask = 0x01,
   .event_name = "l1d_pend_miss.pending_cycles",
   },
  {
   .event_code = {0x48},
   .umask = 0x01,
   .event_name = "l1d_pend_miss.pending_cycles_any",
   },
  {
   .event_code = {0x48},
   .umask = 0x02,
   .event_name = "l1d_pend_miss.fb_full",
   },
  {
   .event_code = {0x49},
   .umask = 0x01,
   .event_name = "dtlb_store_misses.miss_causes_a_walk",
   },
  {
   .event_code = {0x49},
   .umask = 0x02,
   .event_name = "dtlb_store_misses.walk_completed_4k",
   },
  {
   .event_code = {0x49},
   .umask = 0x04,
   .event_name = "dtlb_store_misses.walk_completed_2m_4m",
   },
  {
   .event_code = {0x49},
   .umask = 0x08,
   .event_name = "dtlb_store_misses.walk_completed_1g",
   },
  {
   .event_code = {0x49},
   .umask = 0x0e,
   .event_name = "dtlb_store_misses.walk_completed",
   },
  {
   .event_code = {0x49},
   .umask = 0x10,
   .event_name = "dtlb_store_misses.walk_duration",
   },
  {
   .event_code = {0x49},
   .umask = 0x20,
   .event_name = "dtlb_store_misses.stlb_hit_4k",
   },
  {
   .event_code = {0x49},
   .umask = 0x40,
   .event_name = "dtlb_store_misses.stlb_hit_2m",
   },
  {
   .event_code = {0x49},
   .umask = 0x60,
   .event_name = "dtlb_store_misses.stlb_hit",
   },
  {
   .event_code = {0x4c},
   .umask = 0x01,
   .event_name = "load_hit_pre.sw_pf",
   },
  {
   .event_code = {0x4C},
   .umask = 0x02,
   .event_name = "load_hit_pre.hw_pf",
   },
  {
   .event_code = {0x4F},
   .umask = 0x10,
   .event_name = "ept.walk_cycles",
   },
  {
   .event_code = {0x51},
   .umask = 0x01,
   .event_name = "l1d.replacement",
   },
  {
   .event_code = {0x54},
   .umask = 0x01,
   .event_name = "tx_mem.abort_conflict",
   },
  {
   .event_code = {0x54},
   .umask = 0x02,
   .event_name = "tx_mem.abort_capacity_write",
   },
  {
   .event_code = {0x54},
   .umask = 0x04,
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   .event_code = {0xBC},
   .umask = 0x12,
   .event_name = "page_walker_loads.dtlb_l2",
   },
  {
   .event_code = {0xBC},
   .umask = 0x14,
   .event_name = "page_walker_loads.dtlb_l3",
   },
  {
   .event_code = {0xBC},
   .umask = 0x18,
   .event_name = "page_walker_loads.dtlb_memory",
   },
  {
   .event_code = {0xBC},
   .umask = 0x21,
   .event_name = "page_walker_loads.itlb_l1",
   },
  {
   .event_code = {0xBC},
   .umask = 0x22,
   .event_name = "page_walker_loads.itlb_l2",
   },
  {
   .event_code = {0xBC},
   .umask = 0x24,
   .event_name = "page_walker_loads.itlb_l3",
   },
  {
   .event_code = {0xBD},
   .umask = 0x01,
   .event_name = "tlb_flush.dtlb_thread",
   },
  {
   .event_code = {0xBD},
   .umask = 0x20,
   .event_name = "tlb_flush.stlb_any",
   },
  {
   .event_code = {0xC0},
   .umask = 0x00,
   .event_name = "inst_retired.any_p",
   },
  {
   .event_code = {0xC0},
   .umask = 0x01,
   .event_name = "inst_retired.prec_dist",
   },
  {
   .event_code = {0xC0},
   .umask = 0x02,
   .event_name = "inst_retired.x87",
   },
  {
   .event_code = {0xC1},
   .umask = 0x08,
   .event_name = "other_assists.avx_to_sse",
   },
  {
   .event_code = {0xC1},
   .umask = 0x10,
   .event_name = "other_assists.sse_to_avx",
   },
  {
   .event_code = {0xC1},
   .umask = 0x40,
   .event_name = "other_assists.any_wb_assist",
   },
  {
   .event_code = {0xC2},
   .umask = 0x01,
   .event_name = "uops_retired.all",
   },
  {
   .event_code = {0xC2},
   .umask = 0x01,
   .event_name = "uops_retired.stall_cycles",
   },
  {
   .event_code = {0xC2},
   .umask = 0x01,
   .event_name = "uops_retired.total_cycles",
   },
  {
   .event_code = {0xC2},
   .umask = 0x02,
   .event_name = "uops_retired.retire_slots",
   },
  {
   .event_code = {0xC3},
   .umask = 0x01,
   .event_name = "machine_clears.cycles",
   },
  {
   .event_code = {0xC3},
   .umask = 0x01,
   .event_name = "machine_clears.count",
   },
  {
   .event_code = {0xC3},
   .umask = 0x02,
   .event_name = "machine_clears.memory_ordering",
   },
  {
   .event_code = {0xC3},
   .umask = 0x04,
   .event_name = "machine_clears.smc",
   },
  {
   .event_code = {0xC3},
   .umask = 0x20,
   .event_name = "machine_clears.maskmov",
   },
  {
   .event_code = {0xC4},
   .umask = 0x00,
   .event_name = "br_inst_retired.all_branches",
   },
  {
   .event_code = {0xC4},
   .umask = 0x01,
   .event_name = "br_inst_retired.conditional",
   },
  {
   .event_code = {0xC4},
   .umask = 0x02,
   .event_name = "br_inst_retired.near_call",
   },
  {
   .event_code = {0xC4},
   .umask = 0x02,
   .event_name = "br_inst_retired.near_call_r3",
   },
  {
   .event_code = {0xC4},
   .umask = 0x04,
   .event_name = "br_inst_retired.all_branches_pebs",
   },
  {
   .event_code = {0xC4},
   .umask = 0x08,
   .event_name = "br_inst_retired.near_return",
   },
  {
   .event_code = {0xC4},
   .umask = 0x10,
   .event_name = "br_inst_retired.not_taken",
   },
  {
   .event_code = {0xC4},
   .umask = 0x20,
   .event_name = "br_inst_retired.near_taken",
   },
  {
   .event_code = {0xC4},
   .umask = 0x40,
   .event_name = "br_inst_retired.far_branch",
   },
  {
   .event_code = {0xC5},
   .umask = 0x00,
   .event_name = "br_misp_retired.all_branches",
   },
  {
   .event_code = {0xC5},
   .umask = 0x01,
   .event_name = "br_misp_retired.conditional",
   },
  {
   .event_code = {0xC5},
   .umask = 0x04,
   .event_name = "br_misp_retired.all_branches_pebs",
   },
  {
   .event_code = {0xC5},
   .umask = 0x08,
   .event_name = "br_misp_retired.ret",
   },
  {
   .event_code = {0xC5},
   .umask = 0x20,
   .event_name = "br_misp_retired.near_taken",
   },
  {
   .event_code = {0xC7},
   .umask = 0x01,
   .event_name = "fp_arith_inst_retired.scalar_double",
   },
  {
   .event_code = {0xC7},
   .umask = 0x02,
   .event_name = "fp_arith_inst_retired.scalar_single",
   },
  {
   .event_code = {0xC7},
   .umask = 0x03,
   .event_name = "fp_arith_inst_retired.scalar",
   },
  {
   .event_code = {0xC7},
   .umask = 0x04,
   .event_name = "fp_arith_inst_retired.128b_packed_double",
   },
  {
   .event_code = {0xC7},
   .umask = 0x08,
   .event_name = "fp_arith_inst_retired.128b_packed_single",
   },
  {
   .event_code = {0xC7},
   .umask = 0x10,
   .event_name = "fp_arith_inst_retired.256b_packed_double",
   },
  {
   .event_code = {0xC7},
   .umask = 0x15,
   .event_name = "fp_arith_inst_retired.double",
   },
  {
   .event_code = {0xc7},
   .umask = 0x20,
   .event_name = "fp_arith_inst_retired.256b_packed_single",
   },
  {
   .event_code = {0xC7},
   .umask = 0x2A,
   .event_name = "fp_arith_inst_retired.single",
   },
  {
   .event_code = {0xC7},
   .umask = 0x3C,
   .event_name = "fp_arith_inst_retired.packed",
   },
  {
   .event_code = {0xc8},
   .umask = 0x01,
   .event_name = "hle_retired.start",
   },
  {
   .event_code = {0xc8},
   .umask = 0x02,
   .event_name = "hle_retired.commit",
   },
  {
   .event_code = {0xc8},
   .umask = 0x04,
   .event_name = "hle_retired.aborted",
   },
  {
   .event_code = {0xc8},
   .umask = 0x08,
   .event_name = "hle_retired.aborted_misc1",
   },
  {
   .event_code = {0xc8},
   .umask = 0x10,
   .event_name = "hle_retired.aborted_misc2",
   },
  {
   .event_code = {0xc8},
   .umask = 0x20,
   .event_name = "hle_retired.aborted_misc3",
   },
  {
   .event_code = {0xc8},
   .umask = 0x40,
   .event_name = "hle_retired.aborted_misc4",
   },
  {
   .event_code = {0xc8},
   .umask = 0x80,
   .event_name = "hle_retired.aborted_misc5",
   },
  {
   .event_code = {0xc9},
   .umask = 0x01,
   .event_name = "rtm_retired.start",
   },
  {
   .event_code = {0xc9},
   .umask = 0x02,
   .event_name = "rtm_retired.commit",
   },
  {
   .event_code = {0xc9},
   .umask = 0x04,
   .event_name = "rtm_retired.aborted",
   },
  {
   .event_code = {0xc9},
   .umask = 0x08,
   .event_name = "rtm_retired.aborted_misc1",
   },
  {
   .event_code = {0xc9},
   .umask = 0x10,
   .event_name = "rtm_retired.aborted_misc2",
   },
  {
   .event_code = {0xc9},
   .umask = 0x20,
   .event_name = "rtm_retired.aborted_misc3",
   },
  {
   .event_code = {0xc9},
   .umask = 0x40,
   .event_name = "rtm_retired.aborted_misc4",
   },
  {
   .event_code = {0xc9},
   .umask = 0x80,
   .event_name = "rtm_retired.aborted_misc5",
   },
  {
   .event_code = {0xCA},
   .umask = 0x02,
   .event_name = "fp_assist.x87_output",
   },
  {
   .event_code = {0xCA},
   .umask = 0x04,
   .event_name = "fp_assist.x87_input",
   },
  {
   .event_code = {0xCA},
   .umask = 0x08,
   .event_name = "fp_assist.simd_output",
   },
  {
   .event_code = {0xCA},
   .umask = 0x10,
   .event_name = "fp_assist.simd_input",
   },
  {
   .event_code = {0xCA},
   .umask = 0x1E,
   .event_name = "fp_assist.any",
   },
  {
   .event_code = {0xCC},
   .umask = 0x20,
   .event_name = "rob_misc_events.lbr_inserts",
   },
  {
   .event_code = {0xD0},
   .umask = 0x11,
   .event_name = "mem_uops_retired.stlb_miss_loads",
   },
  {
   .event_code = {0xD0},
   .umask = 0x12,
   .event_name = "mem_uops_retired.stlb_miss_stores",
   },
  {
   .event_code = {0xD0},
   .umask = 0x21,
   .event_name = "mem_uops_retired.lock_loads",
   },
  {
   .event_code = {0xD0},
   .umask = 0x41,
   .event_name = "mem_uops_retired.split_loads",
   },
  {
   .event_code = {0xD0},
   .umask = 0x42,
   .event_name = "mem_uops_retired.split_stores",
   },
  {
   .event_code = {0xD0},
   .umask = 0x81,
   .event_name = "mem_uops_retired.all_loads",
   },
  {
   .event_code = {0xD0},
   .umask = 0x82,
   .event_name = "mem_uops_retired.all_stores",
   },
  {
   .event_code = {0xD1},
   .umask = 0x01,
   .event_name = "mem_load_uops_retired.l1_hit",
   },
  {
   .event_code = {0xD1},
   .umask = 0x02,
   .event_name = "mem_load_uops_retired.l2_hit",
   },
  {
   .event_code = {0xD1},
   .umask = 0x04,
   .event_name = "mem_load_uops_retired.l3_hit",
   },
  {
   .event_code = {0xD1},
   .umask = 0x08,
   .event_name = "mem_load_uops_retired.l1_miss",
   },
  {
   .event_code = {0xD1},
   .umask = 0x10,
   .event_name = "mem_load_uops_retired.l2_miss",
   },
  {
   .event_code = {0xD1},
   .umask = 0x20,
   .event_name = "mem_load_uops_retired.l3_miss",
   },
  {
   .event_code = {0xD1},
   .umask = 0x40,
   .event_name = "mem_load_uops_retired.hit_lfb",
   },
  {
   .event_code = {0xD2},
   .umask = 0x01,
   .event_name = "mem_load_uops_l3_hit_retired.xsnp_miss",
   },
  {
   .event_code = {0xD2},
   .umask = 0x02,
   .event_name = "mem_load_uops_l3_hit_retired.xsnp_hit",
   },
  {
   .event_code = {0xD2},
   .umask = 0x04,
   .event_name = "mem_load_uops_l3_hit_retired.xsnp_hitm",
   },
  {
   .event_code = {0xD2},
   .umask = 0x08,
   .event_name = "mem_load_uops_l3_hit_retired.xsnp_none",
   },
  {
   .event_code = {0xD3},
   .umask = 0x01,
   .event_name = "mem_load_uops_l3_miss_retired.local_dram",
   },
  {
   .event_code = {0xD3},
   .umask = 0x04,
   .event_name = "mem_load_uops_l3_miss_retired.remote_dram",
   },
  {
   .event_code = {0xD3},
   .umask = 0x10,
   .event_name = "mem_load_uops_l3_miss_retired.remote_hitm",
   },
  {
   .event_code = {0xD3},
   .umask = 0x20,
   .event_name = "mem_load_uops_l3_miss_retired.remote_fwd",
   },
  {
   .event_code = {0xe6},
   .umask = 0x1f,
   .event_name = "baclears.any",
   },
  {
   .event_code = {0xF0},
   .umask = 0x01,
   .event_name = "l2_trans.demand_data_rd",
   },
  {
   .event_code = {0xF0},
   .umask = 0x02,
   .event_name = "l2_trans.rfo",
   },
  {
   .event_code = {0xF0},
   .umask = 0x04,
   .event_name = "l2_trans.code_rd",
   },
  {
   .event_code = {0xF0},
   .umask = 0x08,
   .event_name = "l2_trans.all_pf",
   },
  {
   .event_code = {0xF0},
   .umask = 0x10,
   .event_name = "l2_trans.l1d_wb",
   },
  {
   .event_code = {0xF0},
   .umask = 0x20,
   .event_name = "l2_trans.l2_fill",
   },
  {
   .event_code = {0xF0},
   .umask = 0x40,
   .event_name = "l2_trans.l2_wb",
   },
  {
   .event_code = {0xF0},
   .umask = 0x80,
   .event_name = "l2_trans.all_requests",
   },
  {
   .event_code = {0xF1},
   .umask = 0x01,
   .event_name = "l2_lines_in.i",
   },
  {
   .event_code = {0xF1},
   .umask = 0x02,
   .event_name = "l2_lines_in.s",
   },
  {
   .event_code = {0xF1},
   .umask = 0x04,
   .event_name = "l2_lines_in.e",
   },
  {
   .event_code = {0xF1},
   .umask = 0x07,
   .event_name = "l2_lines_in.all",
   },
  {
   .event_code = {0xF2},
   .umask = 0x05,
   .event_name = "l2_lines_out.demand_clean",
   },
  {
   .event_code = {0xf4},
   .umask = 0x10,
   .event_name = "sq_misc.split_lock",
   },
  {
   .event_name = 0,
   },
};

PERFMON_REGISTER_INTEL_PMC (cpu_model_table, event_table);