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# Copyright (c) 2018 Cisco and/or its affiliates.
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at:
#
#     http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.

*** Settings ***
| Resource | resources/libraries/robot/performance/performance_setup.robot
| ...
| Force Tags | 2_NODE_SINGLE_LINK_TOPO | PERFTEST | HW_ENV | NDRPDR
| ... | NIC_Intel-X553 | ETH | L2XCFWD | BASE | L2XCBASE
| ...
| Suite Setup | Set up 2-node performance topology with DUT's NIC model
| ... | L2 | Intel-X553
| ...
| Suite Teardown | Tear down 2-node performance topology
| ...
| Test Setup | Set up performance test
| ...
| Test Teardown | Tear down performance discovery test | ${min_rate}pps
| ... | ${framesize} | ${traffic_profile}
| ...
| Test Template | Local Template
| ...
| Documentation | *RFC2544: Pkt throughput L2XC test cases*
| ...
| ... | *[Top] Network Topologies:* TG-DUT1-TG 2-node circular topology
| ... | with single links between nodes.
| ... | *[Enc] Packet Encapsulations:* Eth-IPv4 for L2 switching of IPv4.
| ... | *[Cfg] DUT configuration:* DUT1 is configured with L2 cross-connect.
| ... | DUT1 tested with 2p10GE NIC X553 by Intel.
| ... | *[Ver] TG verification:* TG finds and reports throughput NDR (Non Drop\
| ... | Rate) with zero packet loss tolerance or throughput PDR (Partial Drop\
| ... | Rate) with non-zero packet loss tolerance (LT) expressed in percentage\
| ... | of packets transmitted. NDR and PDR are discovered for different\
| ... | Ethernet L2 frame sizes using MLRsearch library\
| ... | Test packets are generated by TG on\
| ... | links to DUTs. TG traffic profile contains two L3 flow-groups\
| ... | (flow-group per direction, 254 flows per flow-group) with\
| ... | all packets containing Ethernet header,IPv4 header with static payload.\
| ... | MAC addresses are matching MAC addresses of the TG node interfaces.
| ... | *[Ref] Applicable standard specifications:* RFC2544.

*** Variables ***
# X553 bandwidth limit
| ${s_limit}= | ${10000000000}
# Traffic profile:
| ${traffic_profile}= | trex-sl-2n-ethip4-ip4src254

*** Keywords ***
| Local Template
| | [Documentation]
| | ... | [Cfg] DUT runs L2XC config.\
| | ... | Each DUT uses ${phy_cores} physical core(s) for worker threads.
| | ... | [Ver] Measure NDR and PDR values using MLRsearch algorithm.
| | ...
| | ... | *Arguments:*
| | ... | - framesize - Framesize in Bytes in integer or string (IMIX_v4_1).
| | ... |   Type: integer, string
| | ... | - phy_cores - Number of physical cores. Type: integer
| | ... | - rxq - Number of RX queues, default value: ${None}. Type: integer
| | ...
| | [Arguments] | ${framesize} | ${phy_cores} | ${rxq}=${None}
| | ...
| | Set Test Variable | ${framesize}
| | Set Test Variable | ${min_rate} | ${10000}
| | ...
| | Given Add worker threads and rxqueues to all DUTs | ${phy_cores} | ${rxq}
| | And Add PCI devices to all DUTs
| | ${max_rate} | ${jumbo} = | Get Max Rate And Jumbo And Handle Multi Seg
| | ... | ${s_limit} | ${framesize}
| | And Apply startup configuration on all VPP DUTs
| | And Initialize L2 xconnect in 2-node circular topology
| | Then Find NDR and PDR intervals using optimized search
| | ... | ${framesize} | ${traffic_profile} | ${min_rate} | ${max_rate}

*** Test Cases ***
| tc01-64B-1c-eth-l2xcbase-ndrpdr
| | [Tags] | 64B | 1C
| | framesize=${64} | phy_cores=${1}

| tc02-64B-2c-eth-l2xcbase-ndrpdr
| | [Tags] | 64B | 2C
| | framesize=${64} | phy_cores=${2}

| tc03-64B-4c-eth-l2xcbase-ndrpdr
| | [Tags] | 64B | 4C
| | framesize=${64} | phy_cores=${4}

| tc04-1518B-1c-eth-l2xcbase-ndrpdr
| | [Tags] | 1518B | 1C
| | framesize=${1518} | phy_cores=${1}

| tc05-1518B-2c-eth-l2xcbase-ndrpdr
| | [Tags] | 1518B | 2C
| | framesize=${1518} | phy_cores=${2}

| tc06-1518B-4c-eth-l2xcbase-ndrpdr
| | [Tags] | 1518B | 4C
| | framesize=${1518} | phy_cores=${4}

| tc07-9000B-1c-eth-l2xcbase-ndrpdr
| | [Tags] | 9000B | 1C
| | framesize=${9000} | phy_cores=${1}

| tc08-9000B-2c-eth-l2xcbase-ndrpdr
| | [Tags] | 9000B | 2C
| | framesize=${9000} | phy_cores=${2}

| tc09-9000B-4c-eth-l2xcbase-ndrpdr
| | [Tags] | 9000B | 4C
| | framesize=${9000} | phy_cores=${4}

| tc10-IMIX-1c-eth-l2xcbase-ndrpdr
| | [Tags] | IMIX | 1C
| | framesize=IMIX_v4_1 | phy_cores=${1}

| tc11-IMIX-2c-eth-l2xcbase-ndrpdr
| | [Tags] | IMIX | 2C
| | framesize=IMIX_v4_1 | phy_cores=${2}

| tc12-IMIX-4c-eth-l2xcbase-ndrpdr
| | [Tags] | IMIX | 4C
| | framesize=IMIX_v4_1 | phy_cores=${4}
02' href='#n1102'>1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112 1113 1114 1115 1116 1117 1118 1119 1120 1121 1122 1123 1124 1125 1126 1127 1128 1129 1130 1131 1132 1133 1134 1135 1136 1137 1138 1139 1140 1141 1142 1143 1144 1145 1146 1147 1148 1149 1150 1151 1152 1153 1154 1155 1156 1157 1158 1159 1160 1161 1162 1163 1164 1165 1166 1167 1168 1169 1170 1171 1172 1173 1174 1175 1176 1177 1178 1179 1180 1181 1182 1183 1184 1185 1186 1187 1188 1189 1190 1191 1192 1193 1194 1195 1196 1197 1198 1199 1200 1201 1202 1203 1204 1205 1206 1207 1208 1209 1210 1211 1212 1213 1214 1215 1216 1217 1218 1219 1220 1221 1222 1223 1224 1225 1226 1227 1228 1229 1230 1231 1232 1233 1234 1235 1236 1237 1238 1239 1240 1241 1242 1243 1244 1245 1246 1247 1248 1249 1250 1251 1252 1253 1254 1255 1256 1257 1258 1259 1260 1261 1262 1263 1264 1265 1266 1267 1268 1269 1270 1271 1272 1273 1274 1275 1276 1277 1278 1279 1280 1281 1282 1283 1284 1285 1286 1287 1288 1289 1290 1291 1292 1293 1294 1295 1296 1297 1298 1299 1300 1301 1302 1303 1304 1305 1306 1307 1308 1309 1310 1311 1312 1313 1314 1315 1316 1317 1318 1319 1320 1321 1322 1323 1324 1325 1326 1327 1328 1329 1330 1331 1332 1333 1334 1335 1336 1337 1338 1339 1340 1341 1342 1343 1344 1345 1346 1347 1348 1349 1350 1351 1352 1353 1354 1355 1356 1357 1358 1359 1360 1361 1362 1363 1364 1365 1366 1367 1368 1369 1370 1371 1372 1373 1374 1375 1376 1377 1378 1379 1380 1381 1382 1383
#include <perfmon/perfmon_intel.h>

static perfmon_intel_pmc_cpu_model_t cpu_model_table[] = {
  {0x1E, 0x00, 0},
  {0x1F, 0x00, 0},
  {0x1A, 0x00, 0},

};

static perfmon_intel_pmc_event_t event_table[] = {
  {
   .event_code = {0x14},
   .umask = 0x1,
   .event_name = "arith.cycles_div_busy",
   },
  {
   .event_code = {0x14},
   .umask = 0x1,
   .event_name = "arith.div",
   },
  {
   .event_code = {0x14},
   .umask = 0x2,
   .event_name = "arith.mul",
   },
  {
   .event_code = {0xE6},
   .umask = 0x2,
   .event_name = "baclear.bad_target",
   },
  {
   .event_code = {0xE6},
   .umask = 0x1,
   .event_name = "baclear.clear",
   },
  {
   .event_code = {0xA7},
   .umask = 0x1,
   .event_name = "baclear_force_iq",
   },
  {
   .event_code = {0xE8},
   .umask = 0x1,
   .event_name = "bpu_clears.early",
   },
  {
   .event_code = {0xE8},
   .umask = 0x2,
   .event_name = "bpu_clears.late",
   },
  {
   .event_code = {0xE5},
   .umask = 0x1,
   .event_name = "bpu_missed_call_ret",
   },
  {
   .event_code = {0xE0},
   .umask = 0x1,
   .event_name = "br_inst_decoded",
   },
  {
   .event_code = {0x88},
   .umask = 0x7F,
   .event_name = "br_inst_exec.any",
   },
  {
   .event_code = {0x88},
   .umask = 0x1,
   .event_name = "br_inst_exec.cond",
   },
  {
   .event_code = {0x88},
   .umask = 0x2,
   .event_name = "br_inst_exec.direct",
   },
  {
   .event_code = {0x88},
   .umask = 0x10,
   .event_name = "br_inst_exec.direct_near_call",
   },
  {
   .event_code = {0x88},
   .umask = 0x20,
   .event_name = "br_inst_exec.indirect_near_call",
   },
  {
   .event_code = {0x88},
   .umask = 0x4,
   .event_name = "br_inst_exec.indirect_non_call",
   },
  {
   .event_code = {0x88},
   .umask = 0x30,
   .event_name = "br_inst_exec.near_calls",
   },
  {
   .event_code = {0x88},
   .umask = 0x7,
   .event_name = "br_inst_exec.non_calls",
   },
  {
   .event_code = {0x88},
   .umask = 0x8,
   .event_name = "br_inst_exec.return_near",
   },
  {
   .event_code = {0x88},
   .umask = 0x40,
   .event_name = "br_inst_exec.taken",
   },
  {
   .event_code = {0xC4},
   .umask = 0x4,
   .event_name = "br_inst_retired.all_branches",
   },
  {
   .event_code = {0xC4},
   .umask = 0x1,
   .event_name = "br_inst_retired.conditional",
   },
  {
   .event_code = {0xC4},
   .umask = 0x2,
   .event_name = "br_inst_retired.near_call",
   },
  {
   .event_code = {0x89},
   .umask = 0x7F,
   .event_name = "br_misp_exec.any",
   },
  {
   .event_code = {0x89},
   .umask = 0x1,
   .event_name = "br_misp_exec.cond",
   },
  {
   .event_code = {0x89},
   .umask = 0x2,
   .event_name = "br_misp_exec.direct",
   },
  {
   .event_code = {0x89},
   .umask = 0x10,
   .event_name = "br_misp_exec.direct_near_call",
   },
  {
   .event_code = {0x89},
   .umask = 0x20,
   .event_name = "br_misp_exec.indirect_near_call",
   },
  {
   .event_code = {0x89},
   .umask = 0x4,
   .event_name = "br_misp_exec.indirect_non_call",
   },
  {
   .event_code = {0x89},
   .umask = 0x30,
   .event_name = "br_misp_exec.near_calls",
   },
  {
   .event_code = {0x89},
   .umask = 0x7,
   .event_name = "br_misp_exec.non_calls",
   },
  {
   .event_code = {0x89},
   .umask = 0x8,
   .event_name = "br_misp_exec.return_near",
   },
  {
   .event_code = {0x89},
   .umask = 0x40,
   .event_name = "br_misp_exec.taken",
   },
  {
   .event_code = {0xC5},
   .umask = 0x2,
   .event_name = "br_misp_retired.near_call",
   },
  {
   .event_code = {0x63},
   .umask = 0x2,
   .event_name = "cache_lock_cycles.l1d",
   },
  {
   .event_code = {0x63},
   .umask = 0x1,
   .event_name = "cache_lock_cycles.l1d_l2",
   },
  {
   .event_code = {0x0},
   .umask = 0x0,
   .event_name = "cpu_clk_unhalted.ref",
   },
  {
   .event_code = {0x3C},
   .umask = 0x1,
   .event_name = "cpu_clk_unhalted.ref_p",
   },
  {
   .event_code = {0x0},
   .umask = 0x0,
   .event_name = "cpu_clk_unhalted.thread",
   },
  {
   .event_code = {0x3C},
   .umask = 0x0,
   .event_name = "cpu_clk_unhalted.thread_p",
   },
  {
   .event_code = {0x3C},
   .umask = 0x0,
   .event_name = "cpu_clk_unhalted.total_cycles",
   },
  {
   .event_code = {0x8},
   .umask = 0x1,
   .event_name = "dtlb_load_misses.any",
   },
  {
   .event_code = {0x8},
   .umask = 0x20,
   .event_name = "dtlb_load_misses.pde_miss",
   },
  {
   .event_code = {0x8},
   .umask = 0x10,
   .event_name = "dtlb_load_misses.stlb_hit",
   },
  {
   .event_code = {0x8},
   .umask = 0x2,
   .event_name = "dtlb_load_misses.walk_completed",
   },
  {
   .event_code = {0x49},
   .umask = 0x1,
   .event_name = "dtlb_misses.any",
   },
  {
   .event_code = {0x49},
   .umask = 0x10,
   .event_name = "dtlb_misses.stlb_hit",
   },
  {
   .event_code = {0x49},
   .umask = 0x2,
   .event_name = "dtlb_misses.walk_completed",
   },
  {
   .event_code = {0xD5},
   .umask = 0x1,
   .event_name = "es_reg_renames",
   },
  {
   .event_code = {0xF7},
   .umask = 0x1,
   .event_name = "fp_assist.all",
   },
  {
   .event_code = {0xF7},
   .umask = 0x4,
   .event_name = "fp_assist.input",
   },
  {
   .event_code = {0xF7},
   .umask = 0x2,
   .event_name = "fp_assist.output",
   },
  {
   .event_code = {0x10},
   .umask = 0x2,
   .event_name = "fp_comp_ops_exe.mmx",
   },
  {
   .event_code = {0x10},
   .umask = 0x80,
   .event_name = "fp_comp_ops_exe.sse_double_precision",
   },
  {
   .event_code = {0x10},
   .umask = 0x4,
   .event_name = "fp_comp_ops_exe.sse_fp",
   },
  {
   .event_code = {0x10},
   .umask = 0x10,
   .event_name = "fp_comp_ops_exe.sse_fp_packed",
   },
  {
   .event_code = {0x10},
   .umask = 0x20,
   .event_name = "fp_comp_ops_exe.sse_fp_scalar",
   },
  {
   .event_code = {0x10},
   .umask = 0x40,
   .event_name = "fp_comp_ops_exe.sse_single_precision",
   },
  {
   .event_code = {0x10},
   .umask = 0x8,
   .event_name = "fp_comp_ops_exe.sse2_integer",
   },
  {
   .event_code = {0x10},
   .umask = 0x1,
   .event_name = "fp_comp_ops_exe.x87",
   },
  {
   .event_code = {0xCC},
   .umask = 0x3,
   .event_name = "fp_mmx_trans.any",
   },
  {
   .event_code = {0xCC},
   .umask = 0x1,
   .event_name = "fp_mmx_trans.to_fp",
   },
  {
   .event_code = {0xCC},
   .umask = 0x2,
   .event_name = "fp_mmx_trans.to_mmx",
   },
  {
   .event_code = {0x87},
   .umask = 0xF,
   .event_name = "ild_stall.any",
   },
  {
   .event_code = {0x87},
   .umask = 0x4,
   .event_name = "ild_stall.iq_full",
   },
  {
   .event_code = {0x87},
   .umask = 0x1,
   .event_name = "ild_stall.lcp",
   },
  {
   .event_code = {0x87},
   .umask = 0x2,
   .event_name = "ild_stall.mru",
   },
  {
   .event_code = {0x87},
   .umask = 0x8,
   .event_name = "ild_stall.regen",
   },
  {
   .event_code = {0x18},
   .umask = 0x1,
   .event_name = "inst_decoded.dec0",
   },
  {
   .event_code = {0x1E},
   .umask = 0x1,
   .event_name = "inst_queue_write_cycles",
   },
  {
   .event_code = {0x17},
   .umask = 0x1,
   .event_name = "inst_queue_writes",
   },
  {
   .event_code = {0x0},
   .umask = 0x0,
   .event_name = "inst_retired.any",
   },
  {
   .event_code = {0xC0},
   .umask = 0x1,
   .event_name = "inst_retired.any_p",
   },
  {
   .event_code = {0xC0},
   .umask = 0x4,
   .event_name = "inst_retired.mmx",
   },
  {
   .event_code = {0xC0},
   .umask = 0x1,
   .event_name = "inst_retired.total_cycles",
   },
  {
   .event_code = {0xC0},
   .umask = 0x2,
   .event_name = "inst_retired.x87",
   },
  {
   .event_code = {0x6C},
   .umask = 0x1,
   .event_name = "io_transactions",
   },
  {
   .event_code = {0xAE},
   .umask = 0x1,
   .event_name = "itlb_flush",
   },
  {
   .event_code = {0xC8},
   .umask = 0x20,
   .event_name = "itlb_miss_retired",
   },
  {
   .event_code = {0x85},
   .umask = 0x1,
   .event_name = "itlb_misses.any",
   },
  {
   .event_code = {0x85},
   .umask = 0x2,
   .event_name = "itlb_misses.walk_completed",
   },
  {
   .event_code = {0x51},
   .umask = 0x4,
   .event_name = "l1d.m_evict",
   },
  {
   .event_code = {0x51},
   .umask = 0x2,
   .event_name = "l1d.m_repl",
   },
  {
   .event_code = {0x51},
   .umask = 0x8,
   .event_name = "l1d.m_snoop_evict",
   },
  {
   .event_code = {0x51},
   .umask = 0x1,
   .event_name = "l1d.repl",
   },
  {
   .event_code = {0x43},
   .umask = 0x1,
   .event_name = "l1d_all_ref.any",
   },
  {
   .event_code = {0x43},
   .umask = 0x2,
   .event_name = "l1d_all_ref.cacheable",
   },
  {
   .event_code = {0x40},
   .umask = 0x4,
   .event_name = "l1d_cache_ld.e_state",
   },
  {
   .event_code = {0x40},
   .umask = 0x1,
   .event_name = "l1d_cache_ld.i_state",
   },
  {
   .event_code = {0x40},
   .umask = 0x8,
   .event_name = "l1d_cache_ld.m_state",
   },
  {
   .event_code = {0x40},
   .umask = 0xF,
   .event_name = "l1d_cache_ld.mesi",
   },
  {
   .event_code = {0x40},
   .umask = 0x2,
   .event_name = "l1d_cache_ld.s_state",
   },
  {
   .event_code = {0x42},
   .umask = 0x4,
   .event_name = "l1d_cache_lock.e_state",
   },
  {
   .event_code = {0x42},
   .umask = 0x1,
   .event_name = "l1d_cache_lock.hit",
   },
  {
   .event_code = {0x42},
   .umask = 0x8,
   .event_name = "l1d_cache_lock.m_state",
   },
  {
   .event_code = {0x42},
   .umask = 0x2,
   .event_name = "l1d_cache_lock.s_state",
   },
  {
   .event_code = {0x53},
   .umask = 0x1,
   .event_name = "l1d_cache_lock_fb_hit",
   },
  {
   .event_code = {0x52},
   .umask = 0x1,
   .event_name = "l1d_cache_prefetch_lock_fb_hit",
   },
  {
   .event_code = {0x41},
   .umask = 0x4,
   .event_name = "l1d_cache_st.e_state",
   },
  {
   .event_code = {0x41},
   .umask = 0x8,
   .event_name = "l1d_cache_st.m_state",
   },
  {
   .event_code = {0x41},
   .umask = 0x2,
   .event_name = "l1d_cache_st.s_state",
   },
  {
   .event_code = {0x4E},
   .umask = 0x2,
   .event_name = "l1d_prefetch.miss",
   },
  {
   .event_code = {0x4E},
   .umask = 0x1,
   .event_name = "l1d_prefetch.requests",
   },
  {
   .event_code = {0x4E},
   .umask = 0x4,
   .event_name = "l1d_prefetch.triggers",
   },
  {
   .event_code = {0x28},
   .umask = 0x4,
   .event_name = "l1d_wb_l2.e_state",
   },
  {
   .event_code = {0x28},
   .umask = 0x1,
   .event_name = "l1d_wb_l2.i_state",
   },
  {
   .event_code = {0x28},
   .umask = 0x8,
   .event_name = "l1d_wb_l2.m_state",
   },
  {
   .event_code = {0x28},
   .umask = 0xF,
   .event_name = "l1d_wb_l2.mesi",
   },
  {
   .event_code = {0x28},
   .umask = 0x2,
   .event_name = "l1d_wb_l2.s_state",
   },
  {
   .event_code = {0x80},
   .umask = 0x4,
   .event_name = "l1i.cycles_stalled",
   },
  {
   .event_code = {0x80},
   .umask = 0x1,
   .event_name = "l1i.hits",
   },
  {
   .event_code = {0x80},
   .umask = 0x2,
   .event_name = "l1i.misses",
   },
  {
   .event_code = {0x80},
   .umask = 0x3,
   .event_name = "l1i.reads",
   },
  {
   .event_code = {0x26},
   .umask = 0xFF,
   .event_name = "l2_data_rqsts.any",
   },
  {
   .event_code = {0x26},
   .umask = 0x4,
   .event_name = "l2_data_rqsts.demand.e_state",
   },
  {
   .event_code = {0x26},
   .umask = 0x1,
   .event_name = "l2_data_rqsts.demand.i_state",
   },
  {
   .event_code = {0x26},
   .umask = 0x8,
   .event_name = "l2_data_rqsts.demand.m_state",
   },
  {
   .event_code = {0x26},
   .umask = 0xF,
   .event_name = "l2_data_rqsts.demand.mesi",
   },
  {
   .event_code = {0x26},
   .umask = 0x2,
   .event_name = "l2_data_rqsts.demand.s_state",
   },
  {
   .event_code = {0x26},
   .umask = 0x40,
   .event_name = "l2_data_rqsts.prefetch.e_state",
   },
  {
   .event_code = {0x26},
   .umask = 0x10,
   .event_name = "l2_data_rqsts.prefetch.i_state",
   },
  {
   .event_code = {0x26},
   .umask = 0x80,
   .event_name = "l2_data_rqsts.prefetch.m_state",
   },
  {
   .event_code = {0x26},
   .umask = 0xF0,
   .event_name = "l2_data_rqsts.prefetch.mesi",
   },
  {
   .event_code = {0x26},
   .umask = 0x20,
   .event_name = "l2_data_rqsts.prefetch.s_state",
   },
  {
   .event_code = {0xF1},
   .umask = 0x7,
   .event_name = "l2_lines_in.any",
   },
  {
   .event_code = {0xF1},
   .umask = 0x4,
   .event_name = "l2_lines_in.e_state",
   },
  {
   .event_code = {0xF1},
   .umask = 0x2,
   .event_name = "l2_lines_in.s_state",
   },
  {
   .event_code = {0xF2},
   .umask = 0xF,
   .event_name = "l2_lines_out.any",
   },
  {
   .event_code = {0xF2},
   .umask = 0x1,
   .event_name = "l2_lines_out.demand_clean",
   },
  {
   .event_code = {0xF2},
   .umask = 0x2,
   .event_name = "l2_lines_out.demand_dirty",
   },
  {
   .event_code = {0xF2},
   .umask = 0x4,
   .event_name = "l2_lines_out.prefetch_clean",
   },
  {
   .event_code = {0xF2},
   .umask = 0x8,
   .event_name = "l2_lines_out.prefetch_dirty",
   },
  {
   .event_code = {0x24},
   .umask = 0x10,
   .event_name = "l2_rqsts.ifetch_hit",
   },
  {
   .event_code = {0x24},
   .umask = 0x20,
   .event_name = "l2_rqsts.ifetch_miss",
   },
  {
   .event_code = {0x24},
   .umask = 0x30,
   .event_name = "l2_rqsts.ifetches",
   },
  {
   .event_code = {0x24},
   .umask = 0x1,
   .event_name = "l2_rqsts.ld_hit",
   },
  {
   .event_code = {0x24},
   .umask = 0x2,
   .event_name = "l2_rqsts.ld_miss",
   },
  {
   .event_code = {0x24},
   .umask = 0x3,
   .event_name = "l2_rqsts.loads",
   },
  {
   .event_code = {0x24},
   .umask = 0xAA,
   .event_name = "l2_rqsts.miss",
   },
  {
   .event_code = {0x24},
   .umask = 0x40,
   .event_name = "l2_rqsts.prefetch_hit",
   },
  {
   .event_code = {0x24},
   .umask = 0x80,
   .event_name = "l2_rqsts.prefetch_miss",
   },
  {
   .event_code = {0x24},
   .umask = 0xC0,
   .event_name = "l2_rqsts.prefetches",
   },
  {
   .event_code = {0x24},
   .umask = 0xFF,
   .event_name = "l2_rqsts.references",
   },
  {
   .event_code = {0x24},
   .umask = 0x4,
   .event_name = "l2_rqsts.rfo_hit",
   },
  {
   .event_code = {0x24},
   .umask = 0x8,
   .event_name = "l2_rqsts.rfo_miss",
   },
  {
   .event_code = {0x24},
   .umask = 0xC,
   .event_name = "l2_rqsts.rfos",
   },
  {
   .event_code = {0xF0},
   .umask = 0x80,
   .event_name = "l2_transactions.any",
   },
  {
   .event_code = {0xF0},
   .umask = 0x20,
   .event_name = "l2_transactions.fill",
   },
  {
   .event_code = {0xF0},
   .umask = 0x4,
   .event_name = "l2_transactions.ifetch",
   },
  {
   .event_code = {0xF0},
   .umask = 0x10,
   .event_name = "l2_transactions.l1d_wb",
   },
  {
   .event_code = {0xF0},
   .umask = 0x1,
   .event_name = "l2_transactions.load",
   },
  {
   .event_code = {0xF0},
   .umask = 0x8,
   .event_name = "l2_transactions.prefetch",
   },
  {
   .event_code = {0xF0},
   .umask = 0x2,
   .event_name = "l2_transactions.rfo",
   },
  {
   .event_code = {0xF0},
   .umask = 0x40,
   .event_name = "l2_transactions.wb",
   },
  {
   .event_code = {0x27},
   .umask = 0x40,
   .event_name = "l2_write.lock.e_state",
   },
  {
   .event_code = {0x27},
   .umask = 0xE0,
   .event_name = "l2_write.lock.hit",
   },
  {
   .event_code = {0x27},
   .umask = 0x10,
   .event_name = "l2_write.lock.i_state",
   },
  {
   .event_code = {0x27},
   .umask = 0x80,
   .event_name = "l2_write.lock.m_state",
   },
  {
   .event_code = {0x27},
   .umask = 0xF0,
   .event_name = "l2_write.lock.mesi",
   },
  {
   .event_code = {0x27},
   .umask = 0x20,
   .event_name = "l2_write.lock.s_state",
   },
  {
   .event_code = {0x27},
   .umask = 0xE,
   .event_name = "l2_write.rfo.hit",
   },
  {
   .event_code = {0x27},
   .umask = 0x1,
   .event_name = "l2_write.rfo.i_state",
   },
  {
   .event_code = {0x27},
   .umask = 0x8,
   .event_name = "l2_write.rfo.m_state",
   },
  {
   .event_code = {0x27},
   .umask = 0xF,
   .event_name = "l2_write.rfo.mesi",
   },
  {
   .event_code = {0x27},
   .umask = 0x2,
   .event_name = "l2_write.rfo.s_state",
   },
  {
   .event_code = {0x82},
   .umask = 0x1,
   .event_name = "large_itlb.hit",
   },
  {
   .event_code = {0x13},
   .umask = 0x7,
   .event_name = "load_dispatch.any",
   },
  {
   .event_code = {0x13},
   .umask = 0x4,
   .event_name = "load_dispatch.mob",
   },
  {
   .event_code = {0x13},
   .umask = 0x1,
   .event_name = "load_dispatch.rs",
   },
  {
   .event_code = {0x13},
   .umask = 0x2,
   .event_name = "load_dispatch.rs_delayed",
   },
  {
   .event_code = {0x4C},
   .umask = 0x1,
   .event_name = "load_hit_pre",
   },
  {
   .event_code = {0x2E},
   .umask = 0x41,
   .event_name = "longest_lat_cache.miss",
   },
  {
   .event_code = {0x2E},
   .umask = 0x4F,
   .event_name = "longest_lat_cache.reference",
   },
  {
   .event_code = {0xA8},
   .umask = 0x1,
   .event_name = "lsd.active",
   },
  {
   .event_code = {0xA8},
   .umask = 0x1,
   .event_name = "lsd.inactive",
   },
  {
   .event_code = {0x20},
   .umask = 0x1,
   .event_name = "lsd_overflow",
   },
  {
   .event_code = {0xC3},
   .umask = 0x1,
   .event_name = "machine_clears.cycles",
   },
  {
   .event_code = {0xC3},
   .umask = 0x2,
   .event_name = "machine_clears.mem_order",
   },
  {
   .event_code = {0xC3},
   .umask = 0x4,
   .event_name = "machine_clears.smc",
   },
  {
   .event_code = {0xD0},
   .umask = 0x1,
   .event_name = "macro_insts.decoded",
   },
  {
   .event_code = {0xA6},
   .umask = 0x1,
   .event_name = "macro_insts.fusions_decoded",
   },
  {
   .event_code = {0xB},
   .umask = 0x1,
   .event_name = "mem_inst_retired.loads",
   },
  {
   .event_code = {0xB},
   .umask = 0x2,
   .event_name = "mem_inst_retired.stores",
   },
  {
   .event_code = {0xCB},
   .umask = 0x80,
   .event_name = "mem_load_retired.dtlb_miss",
   },
  {
   .event_code = {0xCB},
   .umask = 0x40,
   .event_name = "mem_load_retired.hit_lfb",
   },
  {
   .event_code = {0xCB},
   .umask = 0x1,
   .event_name = "mem_load_retired.l1d_hit",
   },
  {
   .event_code = {0xCB},
   .umask = 0x2,
   .event_name = "mem_load_retired.l2_hit",
   },
  {
   .event_code = {0xCB},
   .umask = 0x10,
   .event_name = "mem_load_retired.llc_miss",
   },
  {
   .event_code = {0xCB},
   .umask = 0x4,
   .event_name = "mem_load_retired.llc_unshared_hit",
   },
  {
   .event_code = {0xCB},
   .umask = 0x8,
   .event_name = "mem_load_retired.other_core_l2_hit_hitm",
   },
  {
   .event_code = {0xC},
   .umask = 0x1,
   .event_name = "mem_store_retired.dtlb_miss",
   },
  {
   .event_code = {0xF},
   .umask = 0x20,
   .event_name = "mem_uncore_retired.local_dram",
   },
  {
   .event_code = {0xF},
   .umask = 0x2,
   .event_name = "mem_uncore_retired.other_core_l2_hitm",
   },
  {
   .event_code = {0xF},
   .umask = 0x8,
   .event_name = "mem_uncore_retired.remote_cache_local_home_hit",
   },
  {
   .event_code = {0xF},
   .umask = 0x10,
   .event_name = "mem_uncore_retired.remote_dram",
   },
  {
   .event_code = {0xF},
   .umask = 0x80,
   .event_name = "mem_uncore_retired.uncacheable",
   },
  {
   .event_code = {0xB0},
   .umask = 0x40,
   .event_name = "offcore_requests.l1d_writeback",
   },
  {
   .event_code = {0xB2},
   .umask = 0x1,
   .event_name = "offcore_requests_sq_full",
   },
  {
   .event_code = {0x7},
   .umask = 0x1,
   .event_name = "partial_address_alias",
   },
  {
   .event_code = {0xD2},
   .umask = 0xF,
   .event_name = "rat_stalls.any",
   },
  {
   .event_code = {0xD2},
   .umask = 0x1,
   .event_name = "rat_stalls.flags",
   },
  {
   .event_code = {0xD2},
   .umask = 0x2,
   .event_name = "rat_stalls.registers",
   },
  {
   .event_code = {0xD2},
   .umask = 0x4,
   .event_name = "rat_stalls.rob_read_port",
   },
  {
   .event_code = {0xD2},
   .umask = 0x8,
   .event_name = "rat_stalls.scoreboard",
   },
  {
   .event_code = {0xA2},
   .umask = 0x1,
   .event_name = "resource_stalls.any",
   },
  {
   .event_code = {0xA2},
   .umask = 0x20,
   .event_name = "resource_stalls.fpcw",
   },
  {
   .event_code = {0xA2},
   .umask = 0x2,
   .event_name = "resource_stalls.load",
   },
  {
   .event_code = {0xA2},
   .umask = 0x40,
   .event_name = "resource_stalls.mxcsr",
   },
  {
   .event_code = {0xA2},
   .umask = 0x80,
   .event_name = "resource_stalls.other",
   },
  {
   .event_code = {0xA2},
   .umask = 0x10,
   .event_name = "resource_stalls.rob_full",
   },
  {
   .event_code = {0xA2},
   .umask = 0x4,
   .event_name = "resource_stalls.rs_full",
   },
  {
   .event_code = {0xA2},
   .umask = 0x8,
   .event_name = "resource_stalls.store",
   },
  {
   .event_code = {0x4},
   .umask = 0x7,
   .event_name = "sb_drain.any",
   },
  {
   .event_code = {0xD4},
   .umask = 0x1,
   .event_name = "seg_rename_stalls",
   },
  {
   .event_code = {0x12},
   .umask = 0x4,
   .event_name = "simd_int_128.pack",
   },
  {
   .event_code = {0x12},
   .umask = 0x20,
   .event_name = "simd_int_128.packed_arith",
   },
  {
   .event_code = {0x12},
   .umask = 0x10,
   .event_name = "simd_int_128.packed_logical",
   },
  {
   .event_code = {0x12},
   .umask = 0x1,
   .event_name = "simd_int_128.packed_mpy",
   },
  {
   .event_code = {0x12},
   .umask = 0x2,
   .event_name = "simd_int_128.packed_shift",
   },
  {
   .event_code = {0x12},
   .umask = 0x40,
   .event_name = "simd_int_128.shuffle_move",
   },
  {
   .event_code = {0x12},
   .umask = 0x8,
   .event_name = "simd_int_128.unpack",
   },
  {
   .event_code = {0xFD},
   .umask = 0x4,
   .event_name = "simd_int_64.pack",
   },
  {
   .event_code = {0xFD},
   .umask = 0x20,
   .event_name = "simd_int_64.packed_arith",
   },
  {
   .event_code = {0xFD},
   .umask = 0x10,
   .event_name = "simd_int_64.packed_logical",
   },
  {
   .event_code = {0xFD},
   .umask = 0x1,
   .event_name = "simd_int_64.packed_mpy",
   },
  {
   .event_code = {0xFD},
   .umask = 0x2,
   .event_name = "simd_int_64.packed_shift",
   },
  {
   .event_code = {0xFD},
   .umask = 0x40,
   .event_name = "simd_int_64.shuffle_move",
   },
  {
   .event_code = {0xFD},
   .umask = 0x8,
   .event_name = "simd_int_64.unpack",
   },
  {
   .event_code = {0xB8},
   .umask = 0x1,
   .event_name = "snoop_response.hit",
   },
  {
   .event_code = {0xB8},
   .umask = 0x2,
   .event_name = "snoop_response.hite",
   },
  {
   .event_code = {0xB8},
   .umask = 0x4,
   .event_name = "snoop_response.hitm",
   },
  {
   .event_code = {0xF6},
   .umask = 0x1,
   .event_name = "sq_full_stall_cycles",
   },
  {
   .event_code = {0xF4},
   .umask = 0x10,
   .event_name = "sq_misc.split_lock",
   },
  {
   .event_code = {0xC7},
   .umask = 0x4,
   .event_name = "ssex_uops_retired.packed_double",
   },
  {
   .event_code = {0xC7},
   .umask = 0x1,
   .event_name = "ssex_uops_retired.packed_single",
   },
  {
   .event_code = {0xC7},
   .umask = 0x8,
   .event_name = "ssex_uops_retired.scalar_double",
   },
  {
   .event_code = {0xC7},
   .umask = 0x2,
   .event_name = "ssex_uops_retired.scalar_single",
   },
  {
   .event_code = {0xC7},
   .umask = 0x10,
   .event_name = "ssex_uops_retired.vector_integer",
   },
  {
   .event_code = {0x6},
   .umask = 0x4,
   .event_name = "store_blocks.at_ret",
   },
  {
   .event_code = {0x6},
   .umask = 0x8,
   .event_name = "store_blocks.l1d_block",
   },
  {
   .event_code = {0x19},
   .umask = 0x1,
   .event_name = "two_uop_insts_decoded",
   },
  {
   .event_code = {0xDB},
   .umask = 0x1,
   .event_name = "uop_unfusion",
   },
  {
   .event_code = {0xD1},
   .umask = 0x4,
   .event_name = "uops_decoded.esp_folding",
   },
  {
   .event_code = {0xD1},
   .umask = 0x8,
   .event_name = "uops_decoded.esp_sync",
   },
  {
   .event_code = {0xD1},
   .umask = 0x2,
   .event_name = "uops_decoded.ms_cycles_active",
   },
  {
   .event_code = {0xD1},
   .umask = 0x1,
   .event_name = "uops_decoded.stall_cycles",
   },
  {
   .event_code = {0xB1},
   .umask = 0x3F,
   .event_name = "uops_executed.core_active_cycles",
   },
  {
   .event_code = {0xB1},
   .umask = 0x1F,
   .event_name = "uops_executed.core_active_cycles_no_port5",
   },
  {
   .event_code = {0xB1},
   .umask = 0x3F,
   .event_name = "uops_executed.core_stall_count",
   },
  {
   .event_code = {0xB1},
   .umask = 0x1F,
   .event_name = "uops_executed.core_stall_count_no_port5",
   },
  {
   .event_code = {0xB1},
   .umask = 0x3F,
   .event_name = "uops_executed.core_stall_cycles",
   },
  {
   .event_code = {0xB1},
   .umask = 0x1F,
   .event_name = "uops_executed.core_stall_cycles_no_port5",
   },
  {
   .event_code = {0xB1},
   .umask = 0x1,
   .event_name = "uops_executed.port0",
   },
  {
   .event_code = {0xB1},
   .umask = 0x40,
   .event_name = "uops_executed.port015",
   },
  {
   .event_code = {0xB1},
   .umask = 0x40,
   .event_name = "uops_executed.port015_stall_cycles",
   },
  {
   .event_code = {0xB1},
   .umask = 0x2,
   .event_name = "uops_executed.port1",
   },
  {
   .event_code = {0xB1},
   .umask = 0x4,
   .event_name = "uops_executed.port2_core",
   },
  {
   .event_code = {0xB1},
   .umask = 0x80,
   .event_name = "uops_executed.port234_core",
   },
  {
   .event_code = {0xB1},
   .umask = 0x8,
   .event_name = "uops_executed.port3_core",
   },
  {
   .event_code = {0xB1},
   .umask = 0x10,
   .event_name = "uops_executed.port4_core",
   },
  {
   .event_code = {0xB1},
   .umask = 0x20,
   .event_name = "uops_executed.port5",
   },
  {
   .event_code = {0xE},
   .umask = 0x1,
   .event_name = "uops_issued.any",
   },
  {
   .event_code = {0xE},
   .umask = 0x1,
   .event_name = "uops_issued.core_stall_cycles",
   },
  {
   .event_code = {0xE},
   .umask = 0x1,
   .event_name = "uops_issued.cycles_all_threads",
   },
  {
   .event_code = {0xE},
   .umask = 0x2,
   .event_name = "uops_issued.fused",
   },
  {
   .event_code = {0xE},
   .umask = 0x1,
   .event_name = "uops_issued.stall_cycles",
   },
  {
   .event_code = {0xC2},
   .umask = 0x1,
   .event_name = "uops_retired.active_cycles",
   },
  {
   .event_code = {0xC2},
   .umask = 0x1,
   .event_name = "uops_retired.any",
   },
  {
   .event_code = {0xC2},
   .umask = 0x4,
   .event_name = "uops_retired.macro_fused",
   },
  {
   .event_code = {0xC2},
   .umask = 0x2,
   .event_name = "uops_retired.retire_slots",
   },
  {
   .event_code = {0xC2},
   .umask = 0x1,
   .event_name = "uops_retired.stall_cycles",
   },
  {
   .event_code = {0xC2},
   .umask = 0x1,
   .event_name = "uops_retired.total_cycles",
   },
  {
   .event_code = {0xC0},
   .umask = 0x1,
   .event_name = "inst_retired.total_cycles_ps",
   },
  {
   .event_name = 0,
   },
};

PERFMON_REGISTER_INTEL_PMC (cpu_model_table, event_table);