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path: root/topologies/available/lf_2n_clx_testbed29.yaml
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---
metadata:
  version: 0.1
  schema:
    - resources/topology_schemas/2_node_topology.sch.yaml
    - resources/topology_schemas/topology.sch.yaml
  tags: [hw, 2-node]

nodes:
  TG:
    type: TG
    subtype: TREX
    host: "10.32.8.23"
    arch: x86_64
    port: 22
    username: testuser
    password: Csit1234
    interfaces:
      port1:
        # s38-t29-tg1-c2/p1 - 10GE port1 on Intel NIC x710 4p10GE.
        mac_address: "3c:fd:fe:a8:b1:90"
        pci_address: "0000:18:00.0"
        ip4_address: "172.16.10.2"
        driver: i40e
        link: link1
        model: Intel-X710
      port2:
        # s38-t29-tg1-c2/p2 - 10GE port2 on Intel NIC x710 4p10GE.
        mac_address: "3c:fd:fe:a8:b1:91"
        pci_address: "0000:18:00.1"
        ip4_address: "172.16.20.2"
        driver: i40e
        link: link2
        model: Intel-X710
      port3:
        # s38-t29-tg1-c2/p3 - 10GE port3 on Intel NIC x710 4p10GE.
        mac_address: "3c:fd:fe:a8:b1:92"
        pci_address: "0000:18:00.2"
        ip4_address: "172.16.30.2"
        driver: i40e
        link: link3
        model: Intel-X710
      port4:
        # s38-t29-tg1-c2/p4 - 10GE port4 on Intel NIC x710 4p10GE.
        mac_address: "3c:fd:fe:a8:b1:93"
        pci_address: "0000:18:00.3"
        ip4_address: "172.16.40.2"
        driver: i40e
        link: link4
        model: Intel-X710
      port5:
        # s38-t29-tg1-c4/p1 - 25GE port1 on Intel NIC xxv710 2p25GE.
        mac_address: "3c:fd:fe:cf:6c:bc"
        pci_address: "0000:3b:00.0"
        ip4_address: "172.16.50.2"
        driver: i40e
        link: link5
        model: Intel-XXV710
      port6:
        # s38-t29-tg1-c4/p2 - 25GE port2 on Intel NIC xxv710 2p25GE.
        mac_address: "3c:fd:fe:cf:6c:bd"
        pci_address: "0000:3b:00.1"
        ip4_address: "172.16.60.2"
        driver: i40e
        link: link6
        model: Intel-XXV710
      port7:
        # s38-t29-tg1-c9/p1 - 100GE-port1 ConnectX5-2p100GE.
        mac_address: "b8:59:9f:fe:4a:a8"
        pci_address: "0000:5e:00.0"
        ip4_address: "172.16.70.2"
        driver: mlx5_core
        link: link7
        model: Mellanox-CX556A
      port8:
        # s38-t29-tg1-c9/p2 - 100GE-port2 ConnectX5-2p100GE.
        mac_address: "b8:59:9f:fe:4a:a9"
        pci_address: "0000:5e:00.1"
        ip4_address: "172.16.80.2"
        driver: mlx5_core
        link: link8
        model: Mellanox-CX556A
      port9:
        # s38-t29-tg1-c6/p1 - 100GE-port1 ConnectX5-2p100GE.
        mac_address: "10:70:fd:18:44:ec"
        pci_address: "0000:86:00.0"
        ip4_address: "172.16.90.2"
        driver: mlx5_core
        link: link9
        model: Mellanox-CX556A
      port10:
        # s38-t29-tg1-c6/p2 - 100GE-port2 ConnectX5-2p100GE.
        mac_address: "10:70:fd:18:44:ed"
        pci_address: "0000:86:00.1"
        ip4_address: "172.16.100.2"
        driver: mlx5_core
        link: link10
        model: Mellanox-CX556A
  DUT1:
    type: DUT
    host: "10.32.8.22"
    arch: x86_64
    port: 22
    username: testuser
    password: Csit1234
    uio_driver: vfio-pci
    interfaces:
      port1:
        # s37-t29-sut1-c2/p1 - 10GE port1 on Intel NIC x710 4p10GE.
        mac_address: "3c:fd:fe:ca:eb:10"
        pci_address: "0000:18:00.0"
        ip4_address: "172.16.10.1"
        driver: i40e
        link: link1
        model: Intel-X710
      port2:
        # s37-t29-sut1-c2/p2 - 10GE port2 on Intel NIC x710 4p10GE.
        mac_address: "3c:fd:fe:ca:eb:11"
        pci_address: "0000:18:00.1"
        ip4_address: "172.16.20.1"
        driver: i40e
        link: link2
        model: Intel-X710
      port3:
        # s37-t29-sut1-c2/p3 - 10GE port3 on Intel NIC x710 4p10GE.
        mac_address: "3c:fd:fe:ca:eb:12"
        pci_address: "0000:18:00.2"
        ip4_address: "172.16.30.1"
        driver: i40e
        link: link3
        model: Intel-X710
      port4:
        # s37-t29-sut1-c2/p4 - 10GE port4 on Intel NIC x710 4p10GE.
        mac_address: "3c:fd:fe:ca:eb:13"
        pci_address: "0000:18:00.3"
        ip4_address: "172.16.40.1"
        driver: i40e
        link: link4
        model: Intel-X710
      port5:
        # s37-t29-sut1-c2/p1 - 25GE port1 on Intel NIC xxv710 2p25GE.
        mac_address: "3c:fd:fe:dd:d3:48"
        pci_address: "0000:3b:00.0"
        ip4_address: "172.16.50.1"
        driver: i40e
        link: link5
        model: Intel-XXV710
      port6:
        # s37-t29-sut1-c2/p2 - 25GE port2 on Intel NIC xxv710 2p25GE.
        mac_address: "3c:fd:fe:dd:d3:49"
        pci_address: "0000:3b:00.1"
        ip4_address: "172.16.60.1"
        driver: i40e
        link: link6
        model: Intel-XXV710
      port7:
        # s37-t29-sut1-c9/p1 - 100GE-port1 ConnectX5-2p100GE.
        mac_address: "b8:59:9f:fe:4a:c8"
        pci_address: "0000:5e:00.0"
        ip4_address: "172.16.70.1"
        driver: mlx5_core
        link: link7
        model: Mellanox-CX556A
      port8:
        # s37-t29-sut1-c9/p2 - 100GE-port2 ConnectX5-2p100GE.
        mac_address: "b8:59:9f:fe:4a:c9"
        pci_address: "0000:5e:00.1"
        ip4_address: "172.16.80.1"
        driver: mlx5_core
        link: link8
        model: Mellanox-CX556A
      port9:
        # s37-t29-sut1-c6/p1 - 100GE-port1 Intel E810-CQDA2 2p100GE.
        mac_address: "b4:96:91:a4:23:50"
        pci_address: "0000:86:00.0"
        ip4_address: "172.16.90.1"
        driver: ice
        link: link9
        model: Intel-E810CQ
      port10:
        # s37-t29-sut1-c6/p2 - 100GE-port1 Intel E810-CQDA2 2p100GE.
        mac_address: "b4:96:91:a4:23:51"
        pci_address: "0000:86:00.1"
        ip4_address: "172.16.100.1"
        driver: ice
        link: link10
        model: Intel-E810CQ
ep++; } finalize_events(); return (0); } int trackdef_pass1(cpel_section_header_t *sh, int verbose, FILE *ofp) { int i, nevents; track_definition_section_header_t *tdh; track_definition_t *tp; u8 *this_strtab; u32 track_code; uword *p; bound_track_t *btp; int track_strlen; tdh = (track_definition_section_header_t *)(sh+1); nevents = ntohl(tdh->number_of_track_definitions); if (verbose) { fprintf(ofp, "Track Definition Section: %d definitions\n", nevents); } p = hash_get_mem(the_strtab_hash, tdh->string_table_name); if (!p) { fprintf(ofp, "Fatal: couldn't find string table\n"); return(1); } this_strtab = (u8 *)p[0]; tp = (track_definition_t *)(tdh+1); for (i = 0; i < nevents; i++) { track_code = ntohl(tp->track); p = hash_get(the_trackdef_hash, track_code); if (p) { fprintf(ofp, "track %d redefined, retain first definition\n", track_code); continue; } vec_add2(bound_tracks, btp, 1); btp->track = track_code; btp->track_str = this_strtab + ntohl(tp->track_format); hash_set(the_trackdef_hash, track_code, btp - bound_tracks); track_strlen = strlen((char *)btp->track_str); if (track_strlen > widest_track_format) widest_track_format = track_strlen; tp++; } return (0); } int unsupported_pass (cpel_section_header_t *sh, int verbose, FILE *ofp) { if (verbose) { fprintf(ofp, "Unsupported type %d section\n", ntohl(sh->section_type)); } return(0); } int event_pass2(cpel_section_header_t *sh, int verbose, FILE *ofp) { event_section_header_t *eh; u32 event_code, track_code, datum; u64 starttime = ~0ULL; int nevents; int i; event_entry_t *ep; u64 now; u64 delta; u32 time0, time1; double d; uword *p; eh = (event_section_header_t *)(sh+1); nevents = ntohl(eh->number_of_events); ticks_per_ns = ntohl(eh->clock_ticks_per_second)/1e9; ep = (event_entry_t *)(eh+1); p = hash_get_mem(the_strtab_hash, eh->string_table_name); if (!p) { fprintf(ofp, "Fatal: couldn't find string table\n"); return(1); } event_strtab = (u8 *)p[0]; cpel_event_init(nevents); for (i = 0; i < nevents; i++) { time0 = ntohl (ep->time[0]); time1 = ntohl (ep->time[1]); now = (((u64) time0)<<32) | time1; /* Convert from bus ticks to usec */ d = now; d /= ticks_per_ns; now = d; if (starttime == ~0ULL) starttime = now; delta = now - starttime; /* Delta = time since first event, in usec */ event_code = ntohl(ep->event_code); track_code = ntohl(ep->track); datum = ntohl(ep->event_datum); add_cpel_event(delta, track_code, event_code, datum); ep++; } cpel_event_finalize(); return(0); } char *strtab_ref(unsigned long datum) { return ((char *)(event_strtab + datum)); } /* * Note: If necessary, add passes / columns to this table to * handle section order dependencies. */ section_processor_t processors[CPEL_NUM_SECTION_TYPES+1] = { {bad_section, noop_pass}, /* type 0 -- f**ked */ {strtab_pass1, noop_pass}, /* type 1 -- STRTAB */ {unsupported_pass, noop_pass}, /* type 2 -- SYMTAB */ {evtdef_pass1, noop_pass}, /* type 3 -- EVTDEF */ {trackdef_pass1, noop_pass}, /* type 4 -- TRACKDEF */ {noop_pass, event_pass2}, /* type 5 -- EVENTS */ }; int process_section(cpel_section_header_t *sh, int verbose, FILE *ofp, pass_t pass) { u32 type; type = ntohl(sh->section_type); int rv; int (*fp)(cpel_section_header_t *, int, FILE *); if (type > CPEL_NUM_SECTION_TYPES) { fprintf(stderr, "Unknown section type %d\n", type); return(1); } switch(pass) { case PASS1: fp = processors[type].pass1; break; case PASS2: fp = processors[type].pass2; break; default: fprintf(stderr, "Unknown pass %d\n", pass); return(1); } rv = (*fp)(sh, verbose, ofp); return(rv); } int cpel_dump_file_header(cpel_file_header_t *fh, int verbose, FILE *ofp) { time_t file_time; if (verbose) { fprintf(ofp, "CPEL file: %s-endian, version %d\n", ((fh->endian_version & CPEL_FILE_LITTLE_ENDIAN) ? "little" : "big"), fh->endian_version & CPEL_FILE_VERSION_MASK); file_time = ntohl(fh->file_date); fprintf(ofp, "File created %s", ctime(&file_time)); } return(0); } int cpel_process(u8 *cpel, int verbose, FILE *ofp) { cpel_file_header_t *fh; cpel_section_header_t *sh; u16 nsections; u32 section_size; int i; /* First, the file header */ fh = (cpel_file_header_t *)cpel; if (fh->endian_version != CPEL_FILE_VERSION) { if (fh->endian_version & CPEL_FILE_LITTLE_ENDIAN) { fprintf(stderr, "Little endian data format not supported\n"); return(1); } fprintf(stderr, "Unsupported file version 0x%x\n", fh->endian_version); return(1); } cpel_dump_file_header(fh, verbose, ofp); nsections = ntohs(fh->nsections); /* * Take two passes through the file. PASS1 builds * data structures, PASS2 actually dumps the file. * Just in case the sections are in an unobvious order. */ sh = (cpel_section_header_t *)(fh+1); for (i = 0; i < nsections; i++) { section_size = ntohl(sh->data_length); if(verbose) { fprintf(ofp, "Section type %d, size %d\n", ntohl(sh->section_type), section_size); } if(process_section(sh, verbose, ofp, PASS1)) return(1); sh++; sh = (cpel_section_header_t *)(((u8 *)sh)+section_size); } sh = (cpel_section_header_t *)(fh+1); for (i = 0; i < nsections; i++) { if(process_section(sh, verbose, ofp, PASS2)) return(1); section_size = ntohl(sh->data_length); sh++; sh = (cpel_section_header_t *)(((u8 *)sh)+section_size); } return(0); } /* * read_cpel_file */ int read_cpel_file(char *cpel_file) { int verbose = 0; int rv; static u8 *cpel; static unsigned long size; static FILE *ofp; if (cpel) { unmapfile((char *)cpel, size); hash_free(the_strtab_hash); the_strtab_hash = 0; hash_free(the_evtdef_hash); the_evtdef_hash = 0; hash_free(the_trackdef_hash); the_trackdef_hash = 0; } cpel = (u8 *)mapfile((char *)cpel_file, &size); if (cpel == 0) { fprintf(stderr, "Couldn't map %s...\n", cpel_file); exit(1); } if (ofp == NULL) { ofp = fdopen(2, "w"); if (ofp == NULL) { fprintf(stderr, "Couldn't fdopen(2)?\n"); exit(1); } } the_strtab_hash = hash_create_string (0, sizeof (uword)); the_evtdef_hash = hash_create (0, sizeof (uword)); the_trackdef_hash = hash_create (0, sizeof (uword)); rv = cpel_process(cpel, verbose, ofp); set_pid_ax_width(8*widest_track_format); return(rv); } static bound_track_t generic_hex_track = {0, (u8 *) "0x%08x"}; static bound_track_t generic_decimal_track = {0, (u8 *) "%8ld"}; /* * get_track_label */ char *get_track_label(unsigned long track) { uword *p; bound_track_t *tp; p = hash_get(the_trackdef_hash, track); if (p) { tp = &bound_tracks[p[0]]; } else { if (track > 65535) tp = &generic_hex_track; else tp = &generic_decimal_track; } return((char *)tp->track_str); }