diff options
author | Christian Ehrhardt <christian.ehrhardt@canonical.com> | 2018-06-01 09:09:08 +0200 |
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committer | Christian Ehrhardt <christian.ehrhardt@canonical.com> | 2018-06-04 15:56:02 +0200 |
commit | 15dedf321036ae67c61f35a3ab55de767b07801f (patch) | |
tree | 08e18a1b8bb1339a8a8b68802fe4c4ad09b9cdfb /examples/ip_pipeline/examples/route.cli | |
parent | 9f3a8cb4cfe59ea63e267f69700fb0fde13d7dd3 (diff) |
New upstream version 18.05upstream-18.05-stable
Change-Id: Ib515da8d5db1114f07a5fe26239d1c2061007c1c
Signed-off-by: Christian Ehrhardt <christian.ehrhardt@canonical.com>
Diffstat (limited to 'examples/ip_pipeline/examples/route.cli')
-rw-r--r-- | examples/ip_pipeline/examples/route.cli | 60 |
1 files changed, 60 insertions, 0 deletions
diff --git a/examples/ip_pipeline/examples/route.cli b/examples/ip_pipeline/examples/route.cli new file mode 100644 index 00000000..579b36a6 --- /dev/null +++ b/examples/ip_pipeline/examples/route.cli @@ -0,0 +1,60 @@ +; SPDX-License-Identifier: BSD-3-Clause +; Copyright(c) 2010-2018 Intel Corporation + +; _______________ +; LINK0 RXQ0 --->| |---> LINK0 TXQ0 +; | | +; LINK1 RXQ0 --->| |---> LINK1 TXQ0 +; | Routing | +; LINK2 RXQ0 --->| |---> LINK2 TXQ0 +; | | +; LINK3 RXQ0 --->| |---> LINK3 TXQ0 +; |_______________| +; | +; +-----------> SINK0 (route miss) +; +; Input packet: Ethernet/IPv4 +; +; Packet buffer layout: +; # Field Name Offset (Bytes) Size (Bytes) +; 0 Mbuf 0 128 +; 1 Headroom 128 128 +; 2 Ethernet header 256 14 +; 3 IPv4 header 270 20 + +mempool MEMPOOL0 buffer 2304 pool 32K cache 256 cpu 0 + +link LINK0 dev 0000:02:00.0 rxq 1 128 MEMPOOL0 txq 1 512 promiscuous on +link LINK1 dev 0000:02:00.1 rxq 1 128 MEMPOOL0 txq 1 512 promiscuous on +link LINK2 dev 0000:06:00.0 rxq 1 128 MEMPOOL0 txq 1 512 promiscuous on +link LINK3 dev 0000:06:00.1 rxq 1 128 MEMPOOL0 txq 1 512 promiscuous on + +table action profile AP0 ipv4 offset 270 fwd encap ether + +pipeline PIPELINE0 period 10 offset_port_id 0 cpu 0 + +pipeline PIPELINE0 port in bsz 32 link LINK0 rxq 0 +pipeline PIPELINE0 port in bsz 32 link LINK1 rxq 0 +pipeline PIPELINE0 port in bsz 32 link LINK2 rxq 0 +pipeline PIPELINE0 port in bsz 32 link LINK3 rxq 0 + +pipeline PIPELINE0 port out bsz 32 link LINK0 txq 0 +pipeline PIPELINE0 port out bsz 32 link LINK1 txq 0 +pipeline PIPELINE0 port out bsz 32 link LINK2 txq 0 +pipeline PIPELINE0 port out bsz 32 link LINK3 txq 0 +pipeline PIPELINE0 port out bsz 32 sink + +pipeline PIPELINE0 table match lpm ipv4 offset 286 size 4K action AP0 + +pipeline PIPELINE0 port in 0 table 0 +pipeline PIPELINE0 port in 1 table 0 +pipeline PIPELINE0 port in 2 table 0 +pipeline PIPELINE0 port in 3 table 0 + +thread 1 pipeline PIPELINE0 enable + +pipeline PIPELINE0 table 0 rule add match default action fwd port 4 +pipeline PIPELINE0 table 0 rule add match lpm ipv4 100.0.0.0 10 action fwd port 0 encap ether a0:a1:a2:a3:a4:a5 00:01:02:03:04:05 +pipeline PIPELINE0 table 0 rule add match lpm ipv4 100.64.0.0 10 action fwd port 1 encap ether b0:b1:b2:b3:b4:b5 10:11:12:13:14:15 +pipeline PIPELINE0 table 0 rule add match lpm ipv4 100.128.0.0 10 action fwd port 2 encap ether c0:c1:c2:c3:c4:c5 20:21:22:23:24:25 +pipeline PIPELINE0 table 0 rule add match lpm ipv4 100.192.0.0 10 action fwd port 3 encap ether d0:d1:d2:d3:d4:d5 30:31:32:33:34:35 |