Make ICMP filter for 40G work

4 files changed, 32 insertions, 13 deletions

diff --git a/src/dpdk_lib18/librte_ether/rte_eth_ctrl.h b/src/dpdk_lib18/librte_ether/rte_eth_ctrl.h
index 642adb76..d9cdb379 100755
--- a/src/dpdk_lib18/librte_ether/rte_eth_ctrl.h
+++ b/src/dpdk_lib18/librte_ether/rte_eth_ctrl.h
@@ -202,6 +202,7 @@ enum rte_eth_flow_type {
 struct rte_eth_ipv4_flow {
 	uint32_t src_ip;      /**< IPv4 source address to match. */
 	uint32_t dst_ip;      /**< IPv4 destination address to match. */
+	uint8_t l4_proto;     /* IPv4 protocol to match */
 };
 
 /**
diff --git a/src/dpdk_lib18/librte_pmd_i40e/i40e_ethdev.c b/src/dpdk_lib18/librte_pmd_i40e/i40e_ethdev.c
index 9c0db84c..b0e00464 100755
--- a/src/dpdk_lib18/librte_pmd_i40e/i40e_ethdev.c
+++ b/src/dpdk_lib18/librte_pmd_i40e/i40e_ethdev.c
@@ -355,6 +355,20 @@ static inline void i40e_flex_payload_reg_init(struct i40e_hw *hw)
 #define I40E_PRTQF_FD_INSET(_i, _j)    (0x00250000 + ((_i) * 64 + (_j) * 32))
 #define I40E_GLQF_FD_MSK(_i, _j)       (0x00267200 + ((_i) * 4 + (_j) * 8))
 
+void dump_regs(struct i40e_hw *hw)
+{
+    int reg_nums[] = {31, 33, 34, 35, 41, 43};
+    int i;
+    uint32_t reg;
+
+    for (i =0; i < sizeof (reg_nums)/sizeof(int); i++) {
+	reg = I40E_READ_REG(hw,I40E_PRTQF_FD_INSET(reg_nums[i], 0));
+        printf("I40E_PRTQF_FD_INSET(%d, 0): 0x%08x\n", reg_nums[i], reg);
+	reg = I40E_READ_REG(hw,I40E_PRTQF_FD_INSET(reg_nums[i], 1));
+        printf("I40E_PRTQF_FD_INSET(%d, 1): 0x%08x\n", reg_nums[i], reg);
+    }
+}
+
 static inline void i40e_fillter_fields_reg_init(struct i40e_hw *hw)
 {
 	uint32_t reg;
@@ -403,6 +417,10 @@ static inline void i40e_fillter_fields_reg_init(struct i40e_hw *hw)
 	//printf("I40E_PRTQF_FD_INSET(34, 1) = 0x%08x\n", reg);
 	I40E_WRITE_REG(hw, I40E_PRTQF_FD_INSET(34, 1), 0x00040000);
 
+        // filter IP according to ttl and L4 protocol
+	I40E_WRITE_REG(hw, I40E_PRTQF_FD_INSET(35, 0), 0);
+	I40E_WRITE_REG(hw, I40E_PRTQF_FD_INSET(35, 1), 0x00040000);
+
 	reg = I40E_READ_REG(hw,I40E_PRTQF_FD_INSET(44, 0));
 	//printf("I40E_PRTQF_FD_INSET(44, 0) = 0x%08x\n", reg);
 	I40E_WRITE_REG(hw, I40E_PRTQF_FD_INSET(44, 0), 0);
@@ -420,8 +438,6 @@ static inline void i40e_fillter_fields_reg_init(struct i40e_hw *hw)
 	I40E_WRITE_FLUSH(hw);
 }
 
-
-
 static int
 eth_i40e_dev_init(__rte_unused struct eth_driver *eth_drv,
                   struct rte_eth_dev *dev)
diff --git a/src/dpdk_lib18/librte_pmd_i40e/i40e_fdir.c b/src/dpdk_lib18/librte_pmd_i40e/i40e_fdir.c
index 98df9357..4b209e18 100755
--- a/src/dpdk_lib18/librte_pmd_i40e/i40e_fdir.c
+++ b/src/dpdk_lib18/librte_pmd_i40e/i40e_fdir.c
@@ -727,7 +727,10 @@ i40e_fdir_fill_eth_ip_head(const struct rte_eth_fdir_input *fdir_input,
 		 */
 		ip->src_addr = fdir_input->flow.ip4_flow.dst_ip;
 		ip->dst_addr = fdir_input->flow.ip4_flow.src_ip;
-		ip->next_proto_id = next_proto[fdir_input->flow_type];
+                if (fdir_input->flow_type == RTE_ETH_FLOW_TYPE_IPV4_OTHER) {
+                    ip->next_proto_id = fdir_input->flow.ip4_flow.l4_proto;
+                } else
+                    ip->next_proto_id = next_proto[fdir_input->flow_type];
 		break;
 	case RTE_ETH_FLOW_TYPE_UDPV6:
 	case RTE_ETH_FLOW_TYPE_TCPV6:
diff --git a/src/main_dpdk.cpp b/src/main_dpdk.cpp
index 7fd5503f..65015bcd 100755
--- a/src/main_dpdk.cpp
+++ b/src/main_dpdk.cpp
@@ -4717,9 +4717,9 @@ int CTRexExtendedDriverBase1G::wait_for_stable_link(){
 int CTRexExtendedDriverBase1G::configure_drop_queue(CPhyEthIF * _if){
     uint8_t protocol;
     if (CGlobalInfo::m_options.m_l_pkt_mode == 0) {
-        protocol = 0x84;
+        protocol = IPPROTO_SCTP;
     } else {
-        protocol = 0x1;
+        protocol = IPPROTO_ICMP;
     }
 
     _if->pci_reg_write( E1000_RXDCTL(0) , 0);
@@ -5039,11 +5039,6 @@ void CTRexExtendedDriverBase40G::update_configuration(port_cfg_t * cfg){
 void CTRexExtendedDriverBase40G::add_rules(CPhyEthIF * _if,
                                            enum rte_eth_flow_type type,
                                            uint8_t ttl){
-    if (CGlobalInfo::m_options.m_l_pkt_mode != 0) {
-        printf("Currently, on 40G, only SCTP latency pkt mode is supported. Please remove --l-pkt-mode option.\n");
-        exit(-1);
-    }
-
     uint8_t port_id = _if->get_port_id();
     int ret=rte_eth_dev_filter_supported(port_id, RTE_ETH_FILTER_FDIR);
 
@@ -5065,7 +5060,11 @@ void CTRexExtendedDriverBase40G::add_rules(CPhyEthIF * _if,
     filter.input.flow_type = type;
     filter.input.ttl=ttl;
 
-    /* any SCTP move to queue number 1 */
+    if (type == RTE_ETH_FLOW_TYPE_IPV4_OTHER) {
+        filter.input.flow.ip4_flow.l4_proto = IPPROTO_ICMP; // In this case we want filter for icmp packets
+    }
+
+    /* We want to place latency packets in queue 1 */
     ret=rte_eth_dev_filter_ctrl(port_id, RTE_ETH_FILTER_FDIR,
                 RTE_ETH_FILTER_ADD, (void*)&filter);
 
@@ -5094,9 +5093,9 @@ int CTRexExtendedDriverBase40G::configure_rx_filter_rules(CPhyEthIF * _if){
 
 int CTRexExtendedDriverBase40G::configure_drop_queue(CPhyEthIF * _if){
 
-    /* ??? support ICMP in the driver */
     /* Configure queue for latency packets */
-    add_rules(_if,RTE_ETH_FLOW_TYPE_SCTPV4,0);
+    add_rules(_if,RTE_ETH_FLOW_TYPE_IPV4_OTHER,255);
+    add_rules(_if,RTE_ETH_FLOW_TYPE_SCTPV4,255);
     return (0);
 }