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authorYaroslav Brustinov <ybrustin@cisco.com>2016-05-22 18:07:15 +0300
committerYaroslav Brustinov <ybrustin@cisco.com>2016-05-22 18:07:15 +0300
commite412cf438e04b590d6c8632a67243335a9cfa827 (patch)
treea1c16157469c1d07ca02f119b56816657c829510 /scripts/automation/regression
parent8e230286998bfa7a1dfcefe2493d5bee66d2746a (diff)
regression: undo try on map
Diffstat (limited to 'scripts/automation/regression')
-rw-r--r--scripts/automation/regression/stateless_tests/stl_general_test.py17
1 files changed, 7 insertions, 10 deletions
diff --git a/scripts/automation/regression/stateless_tests/stl_general_test.py b/scripts/automation/regression/stateless_tests/stl_general_test.py
index 0700e7c2..982b0a33 100644
--- a/scripts/automation/regression/stateless_tests/stl_general_test.py
+++ b/scripts/automation/regression/stateless_tests/stl_general_test.py
@@ -35,16 +35,13 @@ class CStlGeneral_Test(CTRexGeneral_Test):
def map_ports(self, timeout = 100):
sys.stdout.write('Mapping ports')
for i in range(timeout):
- try:
- sys.stdout.write('.')
- sys.stdout.flush()
- CTRexScenario.stl_ports_map = stl_map_ports(self.stl_trex)
- if self.verify_bidirectional(CTRexScenario.stl_ports_map):
- print('')
- return True
- time.sleep(0.1)
- except:
- time.sleep()
+ sys.stdout.write('.')
+ sys.stdout.flush()
+ CTRexScenario.stl_ports_map = stl_map_ports(self.stl_trex)
+ if self.verify_bidirectional(CTRexScenario.stl_ports_map):
+ print('')
+ return True
+ time.sleep(0.1)
print('')
return False