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authorimarom <imarom@cisco.com>2016-01-07 04:38:38 -0500
committerimarom <imarom@cisco.com>2016-01-07 04:52:14 -0500
commit2dff2ccf6fd6e4dae2556c1cf392473989a826b9 (patch)
treef294070fc49d0c6cf1b7733dd42c6bbe281e71be /scripts/automation/trex_control_plane/client
parent72ca9e76d4c6a5fe48e8cd7e1e49b9e54e40fca9 (diff)
yet another stateless simulation phase
Diffstat (limited to 'scripts/automation/trex_control_plane/client')
-rw-r--r--scripts/automation/trex_control_plane/client/trex_stateless_sim.py8
1 files changed, 7 insertions, 1 deletions
diff --git a/scripts/automation/trex_control_plane/client/trex_stateless_sim.py b/scripts/automation/trex_control_plane/client/trex_stateless_sim.py
index 4382e9fb..b621be20 100644
--- a/scripts/automation/trex_control_plane/client/trex_stateless_sim.py
+++ b/scripts/automation/trex_control_plane/client/trex_stateless_sim.py
@@ -165,7 +165,11 @@ class SimRun(object):
cmd = ['gdb', '--args'] + cmd
print "executing command: '{0}'".format(" ".join(cmd))
- subprocess.call(cmd)
+ try:
+ subprocess.call(cmd)
+ except KeyboardInterrupt as e:
+ print "\n\n*** Caught Ctrl + C... Exiting...\n\n"
+ exit(-1)
self.merge_results()
@@ -181,11 +185,13 @@ class SimRun(object):
return
+ print "Mering cores output to a single pcap file...\n"
inputs = ["{0}-{1}".format(self.options.output_file, index) for index in xrange(0, self.options.cores)]
merge_cap_files(inputs, self.options.output_file, delete_src = True)
+
def is_valid_file(filename):
if not os.path.isfile(filename):
raise argparse.ArgumentTypeError("The file '%s' does not exist" % filename)