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authorimarom <imarom@cisco.com>2016-03-02 16:01:08 +0200
committerimarom <imarom@cisco.com>2016-03-02 16:01:08 +0200
commit26873712908fcfb26ee5310c961846b79f0a8249 (patch)
treea94aa192f9bdf998257b5c6764defa5dce74fcbe /scripts/automation/trex_control_plane/stl/examples
parent9c62e2a6f114d99a7271e259bad2601a28cd9c4a (diff)
port mapping - hardening
Diffstat (limited to 'scripts/automation/trex_control_plane/stl/examples')
-rw-r--r--scripts/automation/trex_control_plane/stl/examples/stl_imix.py7
1 files changed, 4 insertions, 3 deletions
diff --git a/scripts/automation/trex_control_plane/stl/examples/stl_imix.py b/scripts/automation/trex_control_plane/stl/examples/stl_imix.py
index e3c01ca9..cc7691a3 100644
--- a/scripts/automation/trex_control_plane/stl/examples/stl_imix.py
+++ b/scripts/automation/trex_control_plane/stl/examples/stl_imix.py
@@ -30,9 +30,10 @@ def imix_test ():
# map ports - identify the routes
table = stl_map_ports(c)
- print "Mapped ports to sides {0} <--> {1}".format(table['dir'][0], table['dir'][1])
- dir_0 = table['dir'][0]
- dir_1 = table['dir'][1]
+ dir_0 = [x[0] for x in table['bi']]
+ dir_1 = [x[1] for x in table['bi']]
+
+ print "Mapped ports to sides {0} <--> {1}".format(dir_0, dir_1)
# load IMIX profile
profile = STLProfile.load_py('../../../../stl/imix.py')