diff options
| author |   imarom <imarom@cisco.com> | 2016-02-11 03:16:24 -0500 |
|---|---|---|
| committer | imarom <imarom@cisco.com> | 2016-02-11 03:16:24 -0500 |
| commit | 177b486366a44e38538e33b5cd2ac1e9a141aee0 (patch) | |
| tree | d4842857ef3895c0e3e8f5cc9e0e4ec4b639338a /scripts/automation/trex_control_plane/stl/trex_stl_lib/trex_stl_sim.py | |
| parent | c585d631dde54732d04b2f3ee5661f15e7648719 (diff) | |
simulator bug and some YAMLs legacy field
Diffstat (limited to 'scripts/automation/trex_control_plane/stl/trex_stl_lib/trex_stl_sim.py')
| -rw-r--r-- | scripts/automation/trex_control_plane/stl/trex_stl_lib/trex_stl_sim.py | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/scripts/automation/trex_control_plane/stl/trex_stl_lib/trex_stl_sim.py b/scripts/automation/trex_control_plane/stl/trex_stl_lib/trex_stl_sim.py index 71af88d0..357f54bd 100644 --- a/scripts/automation/trex_control_plane/stl/trex_stl_lib/trex_stl_sim.py +++ b/scripts/automation/trex_control_plane/stl/trex_stl_lib/trex_stl_sim.py @@ -143,9 +143,9 @@ class STLSim(object): try: profile = STLProfile.load(input_file) except STLError as e: - print format_text("\nError while loading profile '{0}'\n".format(input_file), 'bold') - print e.brief() + "\n" - return + s = format_text("\nError while loading profile '{0}'\n".format(input_file), 'bold') + s += "\n" + e.brief() + raise STLError(s) stream_list += profile.get_streams() |