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authorimarom <imarom@cisco.com>2016-08-16 10:42:31 +0300
committerimarom <imarom@cisco.com>2016-08-16 10:47:54 +0300
commitc5a9a3c77658f04e9dac066443e3bf6aa7d32b67 (patch)
tree79c4ec77d4c5a1a40295f385cdb068b5991a8dea /scripts/automation/trex_control_plane/stl/trex_stl_lib/trex_stl_sim.py
parent7dbdcb10b440eb7c84aacec463da352a1ea6f7d4 (diff)
simulator breakage fix
Diffstat (limited to 'scripts/automation/trex_control_plane/stl/trex_stl_lib/trex_stl_sim.py')
-rw-r--r--scripts/automation/trex_control_plane/stl/trex_stl_lib/trex_stl_sim.py5
1 files changed, 4 insertions, 1 deletions
diff --git a/scripts/automation/trex_control_plane/stl/trex_stl_lib/trex_stl_sim.py b/scripts/automation/trex_control_plane/stl/trex_stl_lib/trex_stl_sim.py
index 62724e64..3e63c4e2 100644
--- a/scripts/automation/trex_control_plane/stl/trex_stl_lib/trex_stl_sim.py
+++ b/scripts/automation/trex_control_plane/stl/trex_stl_lib/trex_stl_sim.py
@@ -40,6 +40,8 @@ class BpSimException(Exception):
# stateless simulation
class STLSim(object):
+ MASK_ALL = ((1 << 64) - 1)
+
def __init__ (self, bp_sim_path, handler = 0, port_id = 0, api_h = "dummy"):
self.bp_sim_path = os.path.abspath(bp_sim_path)
@@ -61,7 +63,8 @@ class STLSim(object):
"force": force,
"port_id": self.port_id,
"mul": parsing_opts.decode_multiplier(mult),
- "duration": duration}
+ "duration": duration,
+ "core_mask": self.MASK_ALL}
}