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authorimarom <imarom@cisco.com>2016-03-16 11:30:40 +0200
committerimarom <imarom@cisco.com>2016-03-16 11:31:20 +0200
commitf803e5b2b997e02f30bf747ce799f42b7aa61c13 (patch)
tree8c1b92b9d4c3e61fdd55dbe1eff4d7a4b37f9e93 /scripts/automation/trex_control_plane/stl/trex_stl_lib/trex_stl_sim.py
parent9de939585468e18c6aa57f626530841029bb7e86 (diff)
FIX: direction for profile
Diffstat (limited to 'scripts/automation/trex_control_plane/stl/trex_stl_lib/trex_stl_sim.py')
-rw-r--r--scripts/automation/trex_control_plane/stl/trex_stl_lib/trex_stl_sim.py11
1 files changed, 9 insertions, 2 deletions
diff --git a/scripts/automation/trex_control_plane/stl/trex_stl_lib/trex_stl_sim.py b/scripts/automation/trex_control_plane/stl/trex_stl_lib/trex_stl_sim.py
index 614d8b77..42c37e63 100644
--- a/scripts/automation/trex_control_plane/stl/trex_stl_lib/trex_stl_sim.py
+++ b/scripts/automation/trex_control_plane/stl/trex_stl_lib/trex_stl_sim.py
@@ -141,7 +141,7 @@ class STLSim(object):
# handle YAMLs
for input_file in input_files:
try:
- profile = STLProfile.load(input_file)
+ profile = STLProfile.load(input_file, direction = (self.port_id % 2), port = self.port_id)
except STLError as e:
s = format_text("\nError while loading profile '{0}'\n".format(input_file), 'bold')
s += "\n" + e.brief()
@@ -360,6 +360,13 @@ def setParserOptions():
default = None,
type = int)
+ parser.add_argument("-i", "--port",
+ help = "Simulate a specific port ID [default is 0]",
+ dest = "port_id",
+ default = 0,
+ type = int)
+
+
parser.add_argument("-r", "--release",
help = "runs on release image instead of debug [default is False]",
action = "store_true",
@@ -465,7 +472,7 @@ def main (args = None):
mode = 'none'
try:
- r = STLSim(bp_sim_path = options.bp_sim_path)
+ r = STLSim(bp_sim_path = options.bp_sim_path, port_id = options.port_id)
r.run(input_list = options.input_file,
outfile = options.output_file,