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| author |   Hanoh Haim <hhaim@cisco.com> | 2016-06-23 17:23:45 +0300 |
|---|---|---|
| committer | Hanoh Haim <hhaim@cisco.com> | 2016-06-23 17:23:45 +0300 |
| commit | 021f0d49b2607baa05d13f8badfc8f8e51edc43b (patch) | |
| tree | ef687b323d4e1d8c48058d4a39716da495ce3d86 /scripts/automation | |
| parent | a215e9e300bc2870aa644d6c03d63d8d3e4e1644 (diff) | |
enable fcs test
Diffstat (limited to 'scripts/automation')
| -rw-r--r-- | scripts/automation/regression/stateless_tests/stl_rx_test.py | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/scripts/automation/regression/stateless_tests/stl_rx_test.py b/scripts/automation/regression/stateless_tests/stl_rx_test.py index 0dbc7f31..2b6684fd 100644 --- a/scripts/automation/regression/stateless_tests/stl_rx_test.py +++ b/scripts/automation/regression/stateless_tests/stl_rx_test.py @@ -441,13 +441,13 @@ class STLRX_Test(CStlGeneral_Test): def test_fcs_stream(self): """ this test send 1 64 byte packet with latency and check that all counters are reported as 64 bytes""" - self.skip('Skip due to bug trex-213') + #self.skip('Skip due to bug trex-213') all_ports=list(CTRexScenario.stl_ports_map['map'].keys()); for port in all_ports: for l in [True,False]: print(" test port {0} latency : {1} ".format(port,l)) - self.send_1_burst(port,l,100) + self.send_1_burst(port,False,100) # this test adds more and more latency streams and re-test with incremental |