diff options
author | Hanoh Haim <hhaim@cisco.com> | 2016-02-18 16:51:54 +0200 |
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committer | Hanoh Haim <hhaim@cisco.com> | 2016-02-18 16:51:54 +0200 |
commit | 77531f879979de5c261802c88b41a361a18095ab (patch) | |
tree | 511845d62f2e6c9839dcfa98e2db95f1bab3b279 /scripts/automation | |
parent | 8b12867a012f56b92bd3a3797aa2e554c0b71bef (diff) | |
parent | 38defe118db360190121c44a9b65c1477f54afa3 (diff) |
Merge new mask instruction
Diffstat (limited to 'scripts/automation')
3 files changed, 55 insertions, 2 deletions
diff --git a/scripts/automation/regression/unit_tests/functional_tests/stl_basic_tests.py b/scripts/automation/regression/unit_tests/functional_tests/stl_basic_tests.py index 03dbcf82..e6a82cf1 100644 --- a/scripts/automation/regression/unit_tests/functional_tests/stl_basic_tests.py +++ b/scripts/automation/regression/unit_tests/functional_tests/stl_basic_tests.py @@ -177,12 +177,17 @@ class CStlBasic_Test(functional_general_test.CGeneralFunctional_Test): ["udp_1pkt_simple_mac_dst.py","-m 1 -l 1 ",True], ["udp_1pkt_simple_mac_src.py","-m 1 -l 1 ",True], ["udp_1pkt_simple_mac_dst_src.py","-m 1 -l 1 ",True], - ["burst_3st_loop_x_times.py","-m 1 -l 20 ",True] + ["burst_3st_loop_x_times.py","-m 1 -l 20 ",True], + ["udp_1pkt_mac_step.py","-m 1 -l 20 ",True], + ["udp_1pkt_mac_mask1.py","-m 1 -l 20 ",True] , + ["udp_1pkt_mac_mask2.py","-m 1 -l 20 ",True], + ["udp_1pkt_mac_mask3.py","-m 1 -l 20 ",True] + ]; - p1 = [ ["udp_1pkt_mac_step.py","-m 1 -l 20 ",True] ] + p1 = [ ["udp_1pkt_mpls_vm.py","-m 1 ",True] ] for obj in p: diff --git a/scripts/automation/trex_control_plane/stl/trex_stl_lib/api.py b/scripts/automation/trex_control_plane/stl/trex_stl_lib/api.py index 9ce9f7f1..d19dcaf0 100644 --- a/scripts/automation/trex_control_plane/stl/trex_stl_lib/api.py +++ b/scripts/automation/trex_control_plane/stl/trex_stl_lib/api.py @@ -16,6 +16,7 @@ STLPktBuilder = CScapyTRexPktBuilder # VM STLVmFlowVar = CTRexVmDescFlowVar STLVmWrFlowVar = CTRexVmDescWrFlowVar +STLVmWrMaskFlowVar = CTRexVmDescWrMaskFlowVar STLVmFixIpv4 = CTRexVmDescFixIpv4 STLVmTrimPktSize = CTRexVmDescTrimPktSize STLVmTupleGen = CTRexVmDescTupleGen diff --git a/scripts/automation/trex_control_plane/stl/trex_stl_lib/trex_stl_packet_builder_scapy.py b/scripts/automation/trex_control_plane/stl/trex_stl_lib/trex_stl_packet_builder_scapy.py index e028d6d5..24a7301b 100644 --- a/scripts/automation/trex_control_plane/stl/trex_stl_lib/trex_stl_packet_builder_scapy.py +++ b/scripts/automation/trex_control_plane/stl/trex_stl_lib/trex_stl_packet_builder_scapy.py @@ -234,6 +234,22 @@ class CTRexVmInsWrFlowVar(CTRexVmInsBase): self.is_big_endian = is_big_endian assert type(is_big_endian)==bool, 'type of is_big_endian is not bool' +class CTRexVmInsWrMaskFlowVar(CTRexVmInsBase): + def __init__(self, fv_name, pkt_offset,pkt_cast_size,mask,shift, is_big_endian=True): + super(CTRexVmInsWrMaskFlowVar, self).__init__("write_mask_flow_var") + self.name = fv_name + assert type(fv_name)==str, 'type of fv_name is not str' + self.pkt_offset = pkt_offset + assert type(pkt_offset)==int, 'type of pkt_offset is not int' + self.pkt_cast_size = pkt_cast_size + assert type(pkt_cast_size)==int, 'type of pkt_cast_size is not int' + self.mask = mask + assert type(mask)==int, 'type of mask is not int' + self.shift = shift + assert type(shift)==int, 'type of shift is not int' + self.is_big_endian = is_big_endian + assert type(is_big_endian)==bool, 'type of is_big_endian is not bool' + class CTRexVmInsTrimPktSize(CTRexVmInsBase): def __init__(self,fv_name): super(CTRexVmInsTrimPktSize, self).__init__("trim_pkt_size") @@ -562,6 +578,37 @@ class CTRexVmDescWrFlowVar(CTRexVmDescBase): t=parent._name_to_offset(self.pkt_offset) self.pkt_offset = t[0] +class CTRexVmDescWrMaskFlowVar(CTRexVmDescBase): + def __init__(self, fv_name, pkt_offset, pkt_cast_size=1, mask=0xff, shift=0, offset_fixup=0, is_big=True): + super(CTRexVmDescWrMaskFlowVar, self).__init__() + self.name =fv_name + assert type(fv_name)==str, 'type of fv_name is not str' + self.offset_fixup =offset_fixup + assert type(offset_fixup)==int, 'type of offset_fixup is not int' + self.pkt_offset =pkt_offset + self.pkt_cast_size =pkt_cast_size + assert type(pkt_cast_size)==int,'type of pkt_cast_size is not int' + if not (pkt_cast_size in [1,2,4]): + raise CTRexPacketBuildException(-10,"not valid cast size"); + + self.mask = mask + assert type(mask)==int,'type of mask is not int' + self.shift = shift + assert type(shift)==int,'type of shift is not int' + self.is_big =is_big; + assert type(is_big)==bool,'type of is_big_endian is not bool' + + def get_var_ref (self): + return self.name + + def get_obj (self): + return CTRexVmInsWrMaskFlowVar(self.name,self.pkt_offset+self.offset_fixup,self.pkt_cast_size,self.mask,self.shift,self.is_big) + + def compile(self,parent): + if type(self.pkt_offset)==str: + t=parent._name_to_offset(self.pkt_offset) + self.pkt_offset = t[0] + class CTRexVmDescTrimPktSize(CTRexVmDescBase): def __init__(self,fv_name): |