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authorHanoh Haim <hhaim@cisco.com>2016-02-10 14:25:26 +0200
committerHanoh Haim <hhaim@cisco.com>2016-02-10 14:25:26 +0200
commit0c2b005a017a8574a3580e45118069079e9ea7ff (patch)
tree63c9c615df8fe8d0b1e046b3328640a55573bea4 /scripts/stl
parentdfd4db62d8069cb62c9ee7ff4c04f77d125ffe09 (diff)
x client example mac/ip change
Diffstat (limited to 'scripts/stl')
-rw-r--r--scripts/stl/syn_attack.py10
-rw-r--r--scripts/stl/udp_1pkt_1mac.py4
-rw-r--r--scripts/stl/udp_1pkt_1mac_override.py12
-rw-r--r--scripts/stl/udp_1pkt_mac.py4
-rw-r--r--scripts/stl/udp_1pkt_range_clients.py45
5 files changed, 60 insertions, 15 deletions
diff --git a/scripts/stl/syn_attack.py b/scripts/stl/syn_attack.py
index 3e3f70d3..eba11a82 100644
--- a/scripts/stl/syn_attack.py
+++ b/scripts/stl/syn_attack.py
@@ -14,21 +14,21 @@ class STLS1(object):
# vm
- vm = CTRexScRaw( [ CTRexVmDescFlowVar(name="ip_src",
+ vm = CTRexScRaw( [ STLVmFlowVar(name="ip_src",
min_value="16.0.0.0",
max_value="18.0.0.254",
size=4, op="random"),
- CTRexVmDescFlowVar(name="src_port",
+ STLVmFlowVar(name="src_port",
min_value=1025,
max_value=65000,
size=2, op="random"),
- CTRexVmDescWrFlowVar(fv_name="ip_src", pkt_offset= "IP.src" ),
+ STLVmWrFlowVar(fv_name="ip_src", pkt_offset= "IP.src" ),
- CTRexVmDescFixIpv4(offset = "IP"), # fix checksum
+ STLVmFixIpv4(offset = "IP"), # fix checksum
- CTRexVmDescWrFlowVar(fv_name="src_port",
+ STLVmWrFlowVar(fv_name="src_port",
pkt_offset= "TCP.sport") # fix udp len
]
diff --git a/scripts/stl/udp_1pkt_1mac.py b/scripts/stl/udp_1pkt_1mac.py
index f12f8b01..0d2a01a8 100644
--- a/scripts/stl/udp_1pkt_1mac.py
+++ b/scripts/stl/udp_1pkt_1mac.py
@@ -13,8 +13,8 @@ class STLS1(object):
base_pkt = Ether()/IP(src="16.0.0.1",dst="48.0.0.1")/UDP(dport=12,sport=1025)
pad = max(0, size - len(base_pkt)) * 'x'
- vm = CTRexScRaw( [ CTRexVmDescFlowVar(name="mac_src", min_value=1, max_value=1, size=1, op="inc"), # 1 byte varible, range 1-1 ( workaround)
- CTRexVmDescWrFlowVar(fv_name="mac_src", pkt_offset= 11) # write it to LSB of SRC offset it 11
+ vm = CTRexScRaw( [ STLVmFlowVar(name="mac_src", min_value=1, max_value=1, size=1, op="inc"), # 1 byte varible, range 1-1 ( workaround)
+ STLVmWrFlowVar(fv_name="mac_src", pkt_offset= 11) # write it to LSB of SRC offset it 11
]
)
diff --git a/scripts/stl/udp_1pkt_1mac_override.py b/scripts/stl/udp_1pkt_1mac_override.py
index fab4ce99..f1591b80 100644
--- a/scripts/stl/udp_1pkt_1mac_override.py
+++ b/scripts/stl/udp_1pkt_1mac_override.py
@@ -15,15 +15,15 @@ class STLS1(object):
base_pkt = Ether()/IP(src="16.0.0.1",dst="48.0.0.1")/UDP(dport=12,sport=1025)
pad = max(0, size - len(base_pkt)) * 'x'
- vm = CTRexScRaw( [ CTRexVmDescFlowVar(name="dyn_mac_src", min_value=1, max_value=10, size=1, op="inc"), # 1 byte varible, range 1-1 ( workaround)
+ vm = CTRexScRaw( [ STLVmFlowVar(name="dyn_mac_src", min_value=1, max_value=10, size=1, op="inc"), # 1 byte varible, range 1-1 ( workaround)
- CTRexVmDescFlowVar(name="static_mac_src_lsb", min_value=0x12345600, max_value=0x12345600, size=4, op="inc"), # workaround to override the mac 4 LSB byte
- CTRexVmDescFlowVar(name="static_mac_src_msb", min_value=0x00bb, max_value=0x00bb, size=2, op="inc"), # workaround to override the mac 2 MSB byte
+ STLVmFlowVar(name="static_mac_src_lsb", min_value=0x12345600, max_value=0x12345600, size=4, op="inc"), # workaround to override the mac 4 LSB byte
+ STLVmFlowVar(name="static_mac_src_msb", min_value=0x00bb, max_value=0x00bb, size=2, op="inc"), # workaround to override the mac 2 MSB byte
- CTRexVmDescWrFlowVar(fv_name="static_mac_src_msb", pkt_offset= 6),
- CTRexVmDescWrFlowVar(fv_name="static_mac_src_lsb", pkt_offset= 8),
+ STLVmWrFlowVar(fv_name="static_mac_src_msb", pkt_offset= 6),
+ STLVmWrFlowVar(fv_name="static_mac_src_lsb", pkt_offset= 8),
- CTRexVmDescWrFlowVar(fv_name="dyn_mac_src", pkt_offset= 11)
+ STLVmWrFlowVar(fv_name="dyn_mac_src", pkt_offset= 11)
]
)
diff --git a/scripts/stl/udp_1pkt_mac.py b/scripts/stl/udp_1pkt_mac.py
index 375c4a59..a15c286c 100644
--- a/scripts/stl/udp_1pkt_mac.py
+++ b/scripts/stl/udp_1pkt_mac.py
@@ -14,8 +14,8 @@ class STLS1(object):
base_pkt = Ether()/IP(src="16.0.0.1",dst="48.0.0.1")/UDP(dport=12,sport=1025)
pad = max(0, size - len(base_pkt)) * 'x'
- vm = CTRexScRaw( [ CTRexVmDescFlowVar(name="mac_src", min_value=1, max_value=10, size=1, op="inc"), # 1 byte varible, range 1-10
- CTRexVmDescWrFlowVar(fv_name="mac_src", pkt_offset= 11) # write it to LSB of SRC
+ vm = CTRexScRaw( [ STLVmFlowVar(name="mac_src", min_value=1, max_value=10, size=1, op="inc"), # 1 byte varible, range 1-10
+ STLVmWrFlowVar(fv_name="mac_src", pkt_offset= 11) # write it to LSB of SRC
]
)
diff --git a/scripts/stl/udp_1pkt_range_clients.py b/scripts/stl/udp_1pkt_range_clients.py
new file mode 100644
index 00000000..2078b748
--- /dev/null
+++ b/scripts/stl/udp_1pkt_range_clients.py
@@ -0,0 +1,45 @@
+from trex_stl_lib.api import *
+
+
+# x clients override the LSB of destination
+#Base src ip : 55.55.1.1, dst ip: Fixed
+#Increment host port portion starting at 55.55.1.1 for 'n' number of clients (55.55.1.1, 55.55.1.2)
+#Src MAC: start with 0000.dddd.0001, increment mac in steps of 1
+#Dst MAC: Fixed (will be taken from trex_conf.yaml
+
+
+class STLS1(object):
+
+ def __init__ (self):
+ self.num_clients =30000; # max is 16bit
+ self.fsize =64
+
+ def create_stream (self):
+
+ # create a base packet and pad it to size
+ size = self.fsize - 4; # no FCS
+ base_pkt = Ether()/IP(src="55.55.1.1",dst="58.0.0.1")/UDP(dport=12,sport=1025)
+ pad = max(0, size - len(base_pkt)) * 'x'
+
+ vm = CTRexScRaw( [ STLVmFlowVar(name="mac_src", min_value=1, max_value=self.num_clients, size=2, op="inc"), # 1 byte varible, range 1-10
+ STLVmFlowVar(name="mac_src_wa", min_value=0x0000dddd, max_value=0x0000dddd, size=4, op="inc"), # workaround hardcoded the src MAC MSB, will be solved as an option in the stream
+
+ STLVmWrFlowVar(fv_name="mac_src_wa", pkt_offset= 6), # write constrant 0000.ddddd
+ STLVmWrFlowVar(fv_name="mac_src", pkt_offset= 10) # write it to LSB of ethernet.src
+ ]
+ )
+
+ return STLStream(packet = STLPktBuilder(pkt = base_pkt/pad,vm = vm),
+ mode = STLTXCont( pps=10 ))
+
+ def get_streams (self, direction = 0):
+ # create 1 stream
+ return [ self.create_stream() ]
+
+
+# dynamic load - used for trex console or simulator
+def register():
+ return STLS1()
+
+
+