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authorimarom <imarom@cisco.com>2016-09-25 14:58:51 +0300
committerimarom <imarom@cisco.com>2016-09-25 15:08:09 +0300
commitd94e6a00edc22a1dd4946b3603aebb29319ce5ce (patch)
treefebed00c2f93adcc0519fcf9b6ee3c81d66d2178 /scripts/stl
parente768dc68155ba835882733753844a570d8384646 (diff)
split multicore - all tests pass
Diffstat (limited to 'scripts/stl')
-rw-r--r--scripts/stl/tests/multi_core_test.py6
1 files changed, 5 insertions, 1 deletions
diff --git a/scripts/stl/tests/multi_core_test.py b/scripts/stl/tests/multi_core_test.py
index 918a30bf..ccb66cb8 100644
--- a/scripts/stl/tests/multi_core_test.py
+++ b/scripts/stl/tests/multi_core_test.py
@@ -68,9 +68,13 @@ class STLMultiCore(object):
port_min = rng.randint(0, port_bound - 1)
port_max = rng.randint(port_min, port_bound - 1)
+ # 840 is the least common multiple
+ limit_flows = 840 * rng.randint(1, 1000)
vm += [STLVmTupleGen(ip_min = ip_min, ip_max = ip_max,
port_min = port_min, port_max = port_max,
- name = name),
+ name = name,
+ limit_flows = limit_flows),
+
STLVmWrFlowVar (fv_name = name + ".ip", pkt_offset = pkt_offset ), # write ip to packet IP.src]
STLVmWrFlowVar (fv_name = name + ".port", pkt_offset = (pkt_offset + 4) ),
]